i2c: aspeed: Add multi-master use case support
In multi-master environment, this driver's master cannot know exactly when a peer master sends data to this driver's slave so cases can be happened that this master tries sending data through the master_xfer function but slave data from a peer master is still being processed or slave xfer is started by a peer immediately after it queues a master command. To support multi-master use cases properly, this H/W provides arbitration in physical level and it provides priority based command handling too to avoid conflicts in multi-master environment, means that if a master and a slave events happen at the same time, H/W will handle a higher priority event first and a pending event will be handled when bus comes back to the idle state. To support this H/W feature properly, this patch adds the 'pending' state of master and its handling code so that the pending master xfer can be continued after slave operation properly. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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@ -117,6 +117,7 @@
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enum aspeed_i2c_master_state {
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ASPEED_I2C_MASTER_INACTIVE,
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ASPEED_I2C_MASTER_PENDING,
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ASPEED_I2C_MASTER_START,
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ASPEED_I2C_MASTER_TX_FIRST,
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ASPEED_I2C_MASTER_TX,
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@ -126,12 +127,13 @@ enum aspeed_i2c_master_state {
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};
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enum aspeed_i2c_slave_state {
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ASPEED_I2C_SLAVE_STOP,
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ASPEED_I2C_SLAVE_INACTIVE,
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ASPEED_I2C_SLAVE_START,
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ASPEED_I2C_SLAVE_READ_REQUESTED,
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ASPEED_I2C_SLAVE_READ_PROCESSED,
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ASPEED_I2C_SLAVE_WRITE_REQUESTED,
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ASPEED_I2C_SLAVE_WRITE_RECEIVED,
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ASPEED_I2C_SLAVE_STOP,
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};
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struct aspeed_i2c_bus {
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@ -156,6 +158,8 @@ struct aspeed_i2c_bus {
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int cmd_err;
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/* Protected only by i2c_lock_bus */
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int master_xfer_result;
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/* Multi-master */
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bool multi_master;
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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struct i2c_client *slave;
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enum aspeed_i2c_slave_state slave_state;
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@ -251,7 +255,7 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
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}
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/* Slave is not currently active, irq was for someone else. */
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if (bus->slave_state == ASPEED_I2C_SLAVE_STOP)
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if (bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
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return irq_handled;
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dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
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@ -277,16 +281,15 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
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irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
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bus->slave_state = ASPEED_I2C_SLAVE_STOP;
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}
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if (irq_status & ASPEED_I2CD_INTR_TX_NAK) {
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if (irq_status & ASPEED_I2CD_INTR_TX_NAK &&
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bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {
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irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
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bus->slave_state = ASPEED_I2C_SLAVE_STOP;
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}
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if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
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irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
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switch (bus->slave_state) {
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case ASPEED_I2C_SLAVE_READ_REQUESTED:
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if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
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if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_ACK))
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dev_err(bus->dev, "Unexpected ACK on read request.\n");
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bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
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i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
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@ -294,9 +297,12 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
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writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
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break;
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case ASPEED_I2C_SLAVE_READ_PROCESSED:
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if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK))
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if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
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dev_err(bus->dev,
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"Expected ACK after processed read.\n");
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break;
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}
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irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
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i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
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writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
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writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
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@ -310,10 +316,15 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
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break;
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case ASPEED_I2C_SLAVE_STOP:
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i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
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bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
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break;
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case ASPEED_I2C_SLAVE_START:
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/* Slave was just started. Waiting for the next event. */;
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break;
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default:
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dev_err(bus->dev, "unhandled slave_state: %d\n",
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dev_err(bus->dev, "unknown slave_state: %d\n",
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bus->slave_state);
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bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
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break;
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}
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@ -329,6 +340,17 @@ static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
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u8 slave_addr = i2c_8bit_addr_from_msg(msg);
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bus->master_state = ASPEED_I2C_MASTER_START;
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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/*
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* If it's requested in the middle of a slave session, set the master
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* state to 'pending' then H/W will continue handling this master
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* command when the bus comes back to the idle state.
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*/
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if (bus->slave_state != ASPEED_I2C_SLAVE_INACTIVE)
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bus->master_state = ASPEED_I2C_MASTER_PENDING;
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#endif /* CONFIG_I2C_SLAVE */
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bus->buf_index = 0;
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if (msg->flags & I2C_M_RD) {
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@ -384,10 +406,6 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
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bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
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irq_handled |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
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goto out_complete;
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} else {
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/* Master is not currently active, irq was for someone else. */
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if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE)
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goto out_no_complete;
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}
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/*
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@ -399,12 +417,33 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
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if (ret) {
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dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
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irq_status);
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bus->cmd_err = ret;
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bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
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irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS);
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goto out_complete;
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if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
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bus->cmd_err = ret;
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bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
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goto out_complete;
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}
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}
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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/*
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* A pending master command will be started by H/W when the bus comes
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* back to idle state after completing a slave operation so change the
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* master state from 'pending' to 'start' at here if slave is inactive.
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*/
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if (bus->master_state == ASPEED_I2C_MASTER_PENDING) {
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if (bus->slave_state != ASPEED_I2C_SLAVE_INACTIVE)
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goto out_no_complete;
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bus->master_state = ASPEED_I2C_MASTER_START;
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}
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#endif /* CONFIG_I2C_SLAVE */
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/* Master is not currently active, irq was for someone else. */
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if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE ||
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bus->master_state == ASPEED_I2C_MASTER_PENDING)
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goto out_no_complete;
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/* We are in an invalid state; reset bus to a known state. */
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if (!bus->msgs) {
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dev_err(bus->dev, "bus in unknown state. irq_status: 0x%x\n",
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@ -423,6 +462,20 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
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* then update the state and handle the new state below.
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*/
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if (bus->master_state == ASPEED_I2C_MASTER_START) {
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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/*
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* If a peer master starts a xfer immediately after it queues a
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* master command, change its state to 'pending' then H/W will
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* continue the queued master xfer just after completing the
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* slave mode session.
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*/
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if (unlikely(irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH)) {
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bus->master_state = ASPEED_I2C_MASTER_PENDING;
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dev_dbg(bus->dev,
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"master goes pending due to a slave start\n");
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goto out_no_complete;
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}
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#endif /* CONFIG_I2C_SLAVE */
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if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
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if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_NAK))) {
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bus->cmd_err = -ENXIO;
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* interrupt bits. Each case needs to be handled using corresponding
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* handlers depending on the current state.
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*/
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if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
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if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE &&
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bus->master_state != ASPEED_I2C_MASTER_PENDING) {
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irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
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irq_remaining &= ~irq_handled;
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if (irq_remaining)
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@ -601,15 +655,16 @@ static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
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{
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struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
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unsigned long time_left, flags;
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int ret = 0;
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spin_lock_irqsave(&bus->lock, flags);
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bus->cmd_err = 0;
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/* If bus is busy, attempt recovery. We assume a single master
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* environment.
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*/
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if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) {
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/* If bus is busy in a single master environment, attempt recovery. */
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if (!bus->multi_master &&
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(readl(bus->base + ASPEED_I2C_CMD_REG) &
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ASPEED_I2CD_BUS_BUSY_STS)) {
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int ret;
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spin_unlock_irqrestore(&bus->lock, flags);
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ret = aspeed_i2c_recover_bus(bus);
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if (ret)
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@ -629,10 +684,20 @@ static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
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time_left = wait_for_completion_timeout(&bus->cmd_complete,
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bus->adap.timeout);
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if (time_left == 0)
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if (time_left == 0) {
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/*
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* If timed out and bus is still busy in a multi master
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* environment, attempt recovery at here.
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*/
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if (bus->multi_master &&
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(readl(bus->base + ASPEED_I2C_CMD_REG) &
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ASPEED_I2CD_BUS_BUSY_STS))
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aspeed_i2c_recover_bus(bus);
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return -ETIMEDOUT;
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else
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return bus->master_xfer_result;
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}
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return bus->master_xfer_result;
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}
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static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
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@ -672,7 +737,7 @@ static int aspeed_i2c_reg_slave(struct i2c_client *client)
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__aspeed_i2c_reg_slave(bus, client->addr);
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bus->slave = client;
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bus->slave_state = ASPEED_I2C_SLAVE_STOP;
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bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
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spin_unlock_irqrestore(&bus->lock, flags);
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return 0;
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@ -827,7 +892,9 @@ static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
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if (ret < 0)
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return ret;
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if (!of_property_read_bool(pdev->dev.of_node, "multi-master"))
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if (of_property_read_bool(pdev->dev.of_node, "multi-master"))
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bus->multi_master = true;
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else
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fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
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/* Enable Master Mode */
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