ARM: S3C24XX: CPUFREQ: Add core support.
Add the core of the support for enabling the CPUFreq driver on all S3C24XX based systems. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Ben Dooks
Ben Dooks
parent
b0e66522f4
commit
2e4ea6e820
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@ -20,6 +20,8 @@ obj-y += gpiolib.o
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obj-y += clock.o
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obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
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obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o
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# Architecture dependant builds
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obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
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@ -0,0 +1,704 @@
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/* linux/arch/arm/plat-s3c24xx/cpu-freq.c
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*
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* Copyright (c) 2006,2007,2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX CPU Frequency scaling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/cpufreq.h>
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#include <linux/cpu.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/sysdev.h>
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#include <linux/kobject.h>
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#include <linux/sysfs.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include <plat/cpu-freq-core.h>
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#include <mach/regs-clock.h>
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/* note, cpufreq support deals in kHz, no Hz */
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static struct cpufreq_driver s3c24xx_driver;
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static struct s3c_cpufreq_config cpu_cur;
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static struct s3c_iotimings s3c24xx_iotiming;
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static struct cpufreq_frequency_table *pll_reg;
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static unsigned int last_target = ~0;
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static unsigned int ftab_size;
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static struct cpufreq_frequency_table *ftab;
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static struct clk *_clk_mpll;
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static struct clk *_clk_xtal;
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static struct clk *clk_fclk;
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static struct clk *clk_hclk;
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static struct clk *clk_pclk;
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static struct clk *clk_arm;
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static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
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{
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unsigned long fclk, pclk, hclk, armclk;
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cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
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cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
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cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
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cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
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cfg->pll.index = __raw_readl(S3C2410_MPLLCON);
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cfg->pll.frequency = fclk;
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cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
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cfg->divs.h_divisor = fclk / hclk;
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cfg->divs.p_divisor = fclk / pclk;
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}
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static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
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{
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unsigned long pll = cfg->pll.frequency;
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cfg->freq.fclk = pll;
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cfg->freq.hclk = pll / cfg->divs.h_divisor;
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cfg->freq.pclk = pll / cfg->divs.p_divisor;
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/* convert hclk into 10ths of nanoseconds for io calcs */
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cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
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}
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static inline int closer(unsigned int target, unsigned int n, unsigned int c)
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{
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int diff_cur = abs(target - c);
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int diff_new = abs(target - n);
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return (diff_new < diff_cur);
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}
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static void s3c_cpufreq_show(const char *pfx,
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struct s3c_cpufreq_config *cfg)
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{
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s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
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pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
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cfg->freq.hclk, cfg->divs.h_divisor,
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cfg->freq.pclk, cfg->divs.p_divisor);
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}
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/* functions to wrapper the driver info calls to do the cpu specific work */
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static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
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{
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if (cfg->info->set_iotiming)
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(cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
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}
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static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
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{
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if (cfg->info->calc_iotiming)
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return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
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return 0;
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}
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static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
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{
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(cfg->info->set_refresh)(cfg);
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}
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static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
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{
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(cfg->info->set_divs)(cfg);
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}
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static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
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{
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return (cfg->info->calc_divs)(cfg);
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}
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static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
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{
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(cfg->info->set_fvco)(cfg);
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}
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static inline void s3c_cpufreq_resume_clocks(void)
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{
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cpu_cur.info->resume_clocks();
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}
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static inline void s3c_cpufreq_updateclk(struct clk *clk,
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unsigned int freq)
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{
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clk_set_rate(clk, freq);
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}
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static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
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unsigned int target_freq,
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struct cpufreq_frequency_table *pll)
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{
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struct s3c_cpufreq_freqs freqs;
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struct s3c_cpufreq_config cpu_new;
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unsigned long flags;
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cpu_new = cpu_cur; /* copy new from current */
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s3c_cpufreq_show("cur", &cpu_cur);
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/* TODO - check for DMA currently outstanding */
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cpu_new.pll = pll ? *pll : cpu_cur.pll;
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if (pll)
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freqs.pll_changing = 1;
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/* update our frequencies */
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cpu_new.freq.armclk = target_freq;
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cpu_new.freq.fclk = cpu_new.pll.frequency;
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if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
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printk(KERN_ERR "no divisors for %d\n", target_freq);
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goto err_notpossible;
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}
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s3c_freq_dbg("%s: got divs\n", __func__);
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s3c_cpufreq_calc(&cpu_new);
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s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
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if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
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if (s3c_cpufreq_calcio(&cpu_new) < 0) {
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printk(KERN_ERR "%s: no IO timings\n", __func__);
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goto err_notpossible;
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}
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}
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s3c_cpufreq_show("new", &cpu_new);
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/* setup our cpufreq parameters */
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freqs.old = cpu_cur.freq;
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freqs.new = cpu_new.freq;
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freqs.freqs.cpu = 0;
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freqs.freqs.old = cpu_cur.freq.armclk / 1000;
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freqs.freqs.new = cpu_new.freq.armclk / 1000;
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/* update f/h/p clock settings before we issue the change
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* notification, so that drivers do not need to do anything
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* special if they want to recalculate on CPUFREQ_PRECHANGE. */
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s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
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s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
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s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
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s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
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/* start the frequency change */
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if (policy)
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cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE);
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/* If hclk is staying the same, then we do not need to
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* re-write the IO or the refresh timings whilst we are changing
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* speed. */
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local_irq_save(flags);
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/* is our memory clock slowing down? */
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if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
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s3c_cpufreq_setrefresh(&cpu_new);
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s3c_cpufreq_setio(&cpu_new);
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}
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if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
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/* not changing PLL, just set the divisors */
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s3c_cpufreq_setdivs(&cpu_new);
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} else {
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if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
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/* slow the cpu down, then set divisors */
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s3c_cpufreq_setfvco(&cpu_new);
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s3c_cpufreq_setdivs(&cpu_new);
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} else {
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/* set the divisors, then speed up */
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s3c_cpufreq_setdivs(&cpu_new);
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s3c_cpufreq_setfvco(&cpu_new);
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}
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}
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/* did our memory clock speed up */
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if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
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s3c_cpufreq_setrefresh(&cpu_new);
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s3c_cpufreq_setio(&cpu_new);
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}
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/* update our current settings */
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cpu_cur = cpu_new;
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local_irq_restore(flags);
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/* notify everyone we've done this */
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if (policy)
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cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE);
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s3c_freq_dbg("%s: finished\n", __func__);
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return 0;
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err_notpossible:
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printk(KERN_ERR "no compatible settings for %d\n", target_freq);
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return -EINVAL;
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}
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/* s3c_cpufreq_target
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*
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* called by the cpufreq core to adjust the frequency that the CPU
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* is currently running at.
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*/
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static int s3c_cpufreq_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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struct cpufreq_frequency_table *pll;
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unsigned int index;
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/* avoid repeated calls which cause a needless amout of duplicated
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* logging output (and CPU time as the calculation process is
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* done) */
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if (target_freq == last_target)
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return 0;
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last_target = target_freq;
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s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
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__func__, policy, target_freq, relation);
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if (ftab) {
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if (cpufreq_frequency_table_target(policy, ftab,
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target_freq, relation,
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&index)) {
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s3c_freq_dbg("%s: table failed\n", __func__);
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return -EINVAL;
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}
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s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
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target_freq, index, ftab[index].frequency);
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target_freq = ftab[index].frequency;
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}
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target_freq *= 1000; /* convert target to Hz */
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/* find the settings for our new frequency */
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if (!pll_reg || cpu_cur.lock_pll) {
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/* either we've not got any PLL values, or we've locked
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* to the current one. */
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pll = NULL;
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} else {
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struct cpufreq_policy tmp_policy;
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int ret;
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/* we keep the cpu pll table in Hz, to ensure we get an
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* accurate value for the PLL output. */
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tmp_policy.min = policy->min * 1000;
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tmp_policy.max = policy->max * 1000;
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tmp_policy.cpu = policy->cpu;
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/* cpufreq_frequency_table_target uses a pointer to 'index'
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* which is the number of the table entry, not the value of
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* the table entry's index field. */
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ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg,
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target_freq, relation,
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&index);
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if (ret < 0) {
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printk(KERN_ERR "%s: no PLL available\n", __func__);
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goto err_notpossible;
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}
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pll = pll_reg + index;
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s3c_freq_dbg("%s: target %u => %u\n",
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__func__, target_freq, pll->frequency);
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target_freq = pll->frequency;
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}
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return s3c_cpufreq_settarget(policy, target_freq, pll);
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err_notpossible:
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printk(KERN_ERR "no compatible settings for %d\n", target_freq);
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return -EINVAL;
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}
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static unsigned int s3c_cpufreq_get(unsigned int cpu)
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{
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return clk_get_rate(clk_arm) / 1000;
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}
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struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
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{
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struct clk *clk;
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clk = clk_get(dev, name);
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if (IS_ERR(clk))
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printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name);
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return clk;
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}
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static int s3c_cpufreq_init(struct cpufreq_policy *policy)
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{
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printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy);
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if (policy->cpu != 0)
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return -EINVAL;
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policy->cur = s3c_cpufreq_get(0);
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policy->min = policy->cpuinfo.min_freq = 0;
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policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000;
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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/* feed the latency information from the cpu driver */
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policy->cpuinfo.transition_latency = cpu_cur.info->latency;
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if (ftab)
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cpufreq_frequency_table_cpuinfo(policy, ftab);
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return 0;
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}
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static __init int s3c_cpufreq_initclks(void)
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{
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_clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
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_clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
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clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
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clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
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clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
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clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
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if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
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IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
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printk(KERN_ERR "%s: could not get clock(s)\n", __func__);
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return -ENOENT;
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}
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printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__,
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clk_get_rate(clk_fclk) / 1000,
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clk_get_rate(clk_hclk) / 1000,
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clk_get_rate(clk_pclk) / 1000,
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clk_get_rate(clk_arm) / 1000);
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return 0;
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}
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static int s3c_cpufreq_verify(struct cpufreq_policy *policy)
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{
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if (policy->cpu != 0)
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return -EINVAL;
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return 0;
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}
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#ifdef CONFIG_PM
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static struct cpufreq_frequency_table suspend_pll;
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static unsigned int suspend_freq;
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static int s3c_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
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{
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suspend_pll.frequency = clk_get_rate(_clk_mpll);
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suspend_pll.index = __raw_readl(S3C2410_MPLLCON);
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suspend_freq = s3c_cpufreq_get(0) * 1000;
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return 0;
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}
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static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
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{
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int ret;
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s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
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last_target = ~0; /* invalidate last_target setting */
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/* first, find out what speed we resumed at. */
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s3c_cpufreq_resume_clocks();
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/* whilst we will be called later on, we try and re-set the
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* cpu frequencies as soon as possible so that we do not end
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* up resuming devices and then immediatley having to re-set
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* a number of settings once these devices have restarted.
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*
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* as a note, it is expected devices are not used until they
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* have been un-suspended and at that time they should have
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* used the updated clock settings.
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*/
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|
||||
ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define s3c_cpufreq_resume NULL
|
||||
#define s3c_cpufreq_suspend NULL
|
||||
#endif
|
||||
|
||||
static struct cpufreq_driver s3c24xx_driver = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = s3c_cpufreq_verify,
|
||||
.target = s3c_cpufreq_target,
|
||||
.get = s3c_cpufreq_get,
|
||||
.init = s3c_cpufreq_init,
|
||||
.suspend = s3c_cpufreq_suspend,
|
||||
.resume = s3c_cpufreq_resume,
|
||||
.name = "s3c24xx",
|
||||
};
|
||||
|
||||
|
||||
int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info)
|
||||
{
|
||||
if (!info || !info->name) {
|
||||
printk(KERN_ERR "%s: failed to pass valid information\n",
|
||||
__func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n",
|
||||
info->name);
|
||||
|
||||
/* check our driver info has valid data */
|
||||
|
||||
BUG_ON(info->set_refresh == NULL);
|
||||
BUG_ON(info->set_divs == NULL);
|
||||
BUG_ON(info->calc_divs == NULL);
|
||||
|
||||
/* info->set_fvco is optional, depending on whether there
|
||||
* is a need to set the clock code. */
|
||||
|
||||
cpu_cur.info = info;
|
||||
|
||||
/* Note, driver registering should probably update locktime */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
|
||||
{
|
||||
struct s3c_cpufreq_board *ours;
|
||||
|
||||
if (!board) {
|
||||
printk(KERN_INFO "%s: no board data\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Copy the board information so that each board can make this
|
||||
* initdata. */
|
||||
|
||||
ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL);
|
||||
if (ours == NULL) {
|
||||
printk(KERN_ERR "%s: no memory\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
*ours = *board;
|
||||
cpu_cur.board = ours;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init s3c_cpufreq_auto_io(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!cpu_cur.info->get_iotiming) {
|
||||
printk(KERN_ERR "%s: get_iotiming undefined\n", __func__);
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "%s: working out IO settings\n", __func__);
|
||||
|
||||
ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
|
||||
if (ret)
|
||||
printk(KERN_ERR "%s: failed to get timings\n", __func__);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* if one or is zero, then return the other, otherwise return the min */
|
||||
#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
|
||||
|
||||
/**
|
||||
* s3c_cpufreq_freq_min - find the minimum settings for the given freq.
|
||||
* @dst: The destination structure
|
||||
* @a: One argument.
|
||||
* @b: The other argument.
|
||||
*
|
||||
* Create a minimum of each frequency entry in the 'struct s3c_freq',
|
||||
* unless the entry is zero when it is ignored and the non-zero argument
|
||||
* used.
|
||||
*/
|
||||
static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
|
||||
struct s3c_freq *a, struct s3c_freq *b)
|
||||
{
|
||||
dst->fclk = do_min(a->fclk, b->fclk);
|
||||
dst->hclk = do_min(a->hclk, b->hclk);
|
||||
dst->pclk = do_min(a->pclk, b->pclk);
|
||||
dst->armclk = do_min(a->armclk, b->armclk);
|
||||
}
|
||||
|
||||
static inline u32 calc_locktime(u32 freq, u32 time_us)
|
||||
{
|
||||
u32 result;
|
||||
|
||||
result = freq * time_us;
|
||||
result = DIV_ROUND_UP(result, 1000 * 1000);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static void s3c_cpufreq_update_loctkime(void)
|
||||
{
|
||||
unsigned int bits = cpu_cur.info->locktime_bits;
|
||||
u32 rate = (u32)clk_get_rate(_clk_xtal);
|
||||
u32 val;
|
||||
|
||||
if (bits == 0) {
|
||||
WARN_ON(1);
|
||||
return;
|
||||
}
|
||||
|
||||
val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
|
||||
val |= calc_locktime(rate, cpu_cur.info->locktime_m);
|
||||
|
||||
printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val);
|
||||
__raw_writel(val, S3C2410_LOCKTIME);
|
||||
}
|
||||
|
||||
static int s3c_cpufreq_build_freq(void)
|
||||
{
|
||||
int size, ret;
|
||||
|
||||
if (!cpu_cur.info->calc_freqtable)
|
||||
return -EINVAL;
|
||||
|
||||
kfree(ftab);
|
||||
ftab = NULL;
|
||||
|
||||
size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
|
||||
size++;
|
||||
|
||||
ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL);
|
||||
if (!ftab) {
|
||||
printk(KERN_ERR "%s: no memory for tables\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ftab_size = size;
|
||||
|
||||
ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
|
||||
s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init s3c_cpufreq_initcall(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (cpu_cur.info && cpu_cur.board) {
|
||||
ret = s3c_cpufreq_initclks();
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* get current settings */
|
||||
s3c_cpufreq_getcur(&cpu_cur);
|
||||
s3c_cpufreq_show("cur", &cpu_cur);
|
||||
|
||||
if (cpu_cur.board->auto_io) {
|
||||
ret = s3c_cpufreq_auto_io();
|
||||
if (ret) {
|
||||
printk(KERN_ERR "%s: failed to get io timing\n",
|
||||
__func__);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
|
||||
printk(KERN_ERR "%s: no IO support registered\n",
|
||||
__func__);
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (!cpu_cur.info->need_pll)
|
||||
cpu_cur.lock_pll = 1;
|
||||
|
||||
s3c_cpufreq_update_loctkime();
|
||||
|
||||
s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
|
||||
&cpu_cur.info->max);
|
||||
|
||||
if (cpu_cur.info->calc_freqtable)
|
||||
s3c_cpufreq_build_freq();
|
||||
|
||||
ret = cpufreq_register_driver(&s3c24xx_driver);
|
||||
}
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
late_initcall(s3c_cpufreq_initcall);
|
||||
|
||||
/**
|
||||
* s3c_plltab_register - register CPU PLL table.
|
||||
* @plls: The list of PLL entries.
|
||||
* @plls_no: The size of the PLL entries @plls.
|
||||
*
|
||||
* Register the given set of PLLs with the system.
|
||||
*/
|
||||
int __init s3c_plltab_register(struct cpufreq_frequency_table *plls,
|
||||
unsigned int plls_no)
|
||||
{
|
||||
struct cpufreq_frequency_table *vals;
|
||||
unsigned int size;
|
||||
|
||||
size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1);
|
||||
|
||||
vals = kmalloc(size, GFP_KERNEL);
|
||||
if (vals) {
|
||||
memcpy(vals, plls, size);
|
||||
pll_reg = vals;
|
||||
|
||||
/* write a terminating entry, we don't store it in the
|
||||
* table that is stored in the kernel */
|
||||
vals += plls_no;
|
||||
vals->frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no);
|
||||
} else
|
||||
printk(KERN_ERR "cpufreq: no memory for PLL tables\n");
|
||||
|
||||
return vals ? 0 : -ENOMEM;
|
||||
}
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/* arch/arm/plat-s3c/include/plat/cpu-freq.h
|
||||
*
|
||||
* Copyright (c) 2006,2007,2009 Simtec Electronics
|
||||
* http://armlinux.simtec.co.uk/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C CPU frequency scaling support - core support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
|
||||
#define MAX_BANKS (8)
|
||||
#define S3C2412_MAX_IO (8)
|
||||
|
||||
/**
|
||||
* struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
|
||||
* @bankcon: The cached version of settings in this structure.
|
||||
* @tacp:
|
||||
* @tacs: Time from address valid to nCS asserted.
|
||||
* @tcos: Time from nCS asserted to nOE or nWE asserted.
|
||||
* @tacc: Time that nOE or nWE is asserted.
|
||||
* @tcoh: Time nCS is held after nOE or nWE are released.
|
||||
* @tcah: Time address is held for after
|
||||
* @nwait_en: Whether nWAIT is enabled for this bank.
|
||||
*
|
||||
* This structure represents the IO timings for a S3C2410 style IO bank
|
||||
* used by the CPU frequency support if it needs to change the settings
|
||||
* of the IO.
|
||||
*/
|
||||
struct s3c2410_iobank_timing {
|
||||
unsigned long bankcon;
|
||||
unsigned int tacp;
|
||||
unsigned int tacs;
|
||||
unsigned int tcos;
|
||||
unsigned int tacc;
|
||||
unsigned int tcoh; /* nCS hold afrer nOE/nWE */
|
||||
unsigned int tcah; /* Address hold after nCS */
|
||||
unsigned char nwait_en; /* nWait enabled for bank. */
|
||||
};
|
||||
|
||||
union s3c_iobank {
|
||||
struct s3c2410_iobank_timing *io_2410;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct s3c_iotimings - Chip IO timings holder
|
||||
* @bank: The timings for each IO bank.
|
||||
*/
|
||||
struct s3c_iotimings {
|
||||
union s3c_iobank bank[MAX_BANKS];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct s3c_plltab - PLL table information.
|
||||
* @vals: List of PLL values.
|
||||
* @size: Size of the PLL table @vals.
|
||||
*/
|
||||
struct s3c_plltab {
|
||||
struct s3c_pllval *vals;
|
||||
int size;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct s3c_cpufreq_info - Information for the CPU frequency driver.
|
||||
* @name: The name of this implementation.
|
||||
* @max: The maximum frequencies for the system.
|
||||
* @latency: Transition latency to give to cpufreq.
|
||||
* @locktime_m: The lock-time in uS for the MPLL.
|
||||
* @locktime_u: The lock-time in uS for the UPLL.
|
||||
* @locttime_bits: The number of bits each LOCKTIME field.
|
||||
* @need_pll: Set if this driver needs to change the PLL values to acheive
|
||||
* any frequency changes. This is really only need by devices like the
|
||||
* S3C2410 where there is no or limited divider between the PLL and the
|
||||
* ARMCLK.
|
||||
* @resume_clocks: Update the clocks on resume.
|
||||
* @get_iotiming: Get the current IO timing data, mainly for use at start.
|
||||
* @set_iotiming: Update the IO timings from the cached copies calculated
|
||||
* from the @calc_iotiming entry when changing the frequency.
|
||||
* @calc_iotiming: Calculate and update the cached copies of the IO timings
|
||||
* from the newly calculated frequencies.
|
||||
* @calc_freqtable: Calculate (fill in) the given frequency table from the
|
||||
* current frequency configuration. If the table passed in is NULL,
|
||||
* then the return is the number of elements to be filled for allocation
|
||||
* of the table.
|
||||
* @set_refresh: Set the memory refresh configuration.
|
||||
* @set_fvco: Set the PLL frequencies.
|
||||
* @set_divs: Update the clock divisors.
|
||||
* @calc_divs: Calculate the clock divisors.
|
||||
*/
|
||||
struct s3c_cpufreq_info {
|
||||
const char *name;
|
||||
struct s3c_freq max;
|
||||
|
||||
unsigned int latency;
|
||||
|
||||
unsigned int locktime_m;
|
||||
unsigned int locktime_u;
|
||||
unsigned char locktime_bits;
|
||||
|
||||
unsigned int need_pll:1;
|
||||
|
||||
/* driver routines */
|
||||
|
||||
void (*resume_clocks)(void);
|
||||
|
||||
int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
|
||||
struct s3c_iotimings *timings);
|
||||
|
||||
void (*set_iotiming)(struct s3c_cpufreq_config *cfg,
|
||||
struct s3c_iotimings *timings);
|
||||
|
||||
int (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
|
||||
struct s3c_iotimings *timings);
|
||||
|
||||
int (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
|
||||
struct cpufreq_frequency_table *t,
|
||||
size_t table_size);
|
||||
|
||||
void (*set_refresh)(struct s3c_cpufreq_config *cfg);
|
||||
void (*set_fvco)(struct s3c_cpufreq_config *cfg);
|
||||
void (*set_divs)(struct s3c_cpufreq_config *cfg);
|
||||
int (*calc_divs)(struct s3c_cpufreq_config *cfg);
|
||||
};
|
||||
|
||||
extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
|
||||
|
||||
extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no);
|
||||
|
||||
/* Useful utility functions. */
|
||||
|
||||
extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
|
||||
|
||||
/* S3C2410 and compatible exported functions */
|
||||
|
||||
extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
|
||||
|
||||
extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
|
||||
struct s3c_iotimings *iot);
|
||||
|
||||
extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
|
||||
struct s3c_iotimings *timings);
|
||||
|
||||
extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
|
||||
struct s3c_iotimings *iot);
|
||||
|
||||
extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG
|
||||
#define s3c_freq_dbg(x...) printk(KERN_INFO x)
|
||||
#else
|
||||
#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
|
||||
#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG
|
||||
#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
|
||||
#else
|
||||
#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
|
||||
#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */
|
||||
|
||||
static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
|
||||
int index, size_t table_size,
|
||||
unsigned int freq)
|
||||
{
|
||||
if (index < 0)
|
||||
return index;
|
||||
|
||||
if (table) {
|
||||
if (index >= table_size)
|
||||
return -ENOMEM;
|
||||
|
||||
s3c_freq_dbg("%s: { %d = %u kHz }\n",
|
||||
__func__, index, freq);
|
||||
|
||||
table[index].index = index;
|
||||
table[index].frequency = freq;
|
||||
}
|
||||
|
||||
return index + 1;
|
||||
}
|
||||
Loading…
Reference in New Issue