powerpc: Document Freescale power management nodes, and the sleep property.
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -77,10 +77,12 @@ Table of Contents
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3) OpenPIC Interrupt Controllers
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4) ISA Interrupt Controllers
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VIII - Specifying GPIO information for devices
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IX - Specifying GPIO information for devices
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1) gpios property
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2) gpio-controller nodes
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X - Specifying device power management information (sleep property)
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Appendix A - Sample SOC node for MPC8540
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@ -2422,8 +2424,8 @@ encodings listed below:
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2 = high to low edge sensitive type enabled
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3 = low to high edge sensitive type enabled
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VIII - Specifying GPIO information for devices
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==============================================
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IX - Specifying GPIO information for devices
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============================================
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1) gpios property
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-----------------
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@ -2471,6 +2473,37 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
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gpio-controller;
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};
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X - Specifying Device Power Management Information (sleep property)
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===================================================================
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Devices on SOCs often have mechanisms for placing devices into low-power
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states that are decoupled from the devices' own register blocks. Sometimes,
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this information is more complicated than a cell-index property can
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reasonably describe. Thus, each device controlled in such a manner
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may contain a "sleep" property which describes these connections.
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The sleep property consists of one or more sleep resources, each of
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which consists of a phandle to a sleep controller, followed by a
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controller-specific sleep specifier of zero or more cells.
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The semantics of what type of low power modes are possible are defined
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by the sleep controller. Some examples of the types of low power modes
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that may be supported are:
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- Dynamic: The device may be disabled or enabled at any time.
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- System Suspend: The device may request to be disabled or remain
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awake during system suspend, but will not be disabled until then.
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- Permanent: The device is disabled permanently (until the next hard
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reset).
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Some devices may share a clock domain with each other, such that they should
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only be suspended when none of the devices are in use. Where reasonable,
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such nodes should be placed on a virtual bus, where the bus has the sleep
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property. If the clock domain is shared among devices that cannot be
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reasonably grouped in this manner, then create a virtual sleep controller
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(similar to an interrupt nexus, except that defining a standardized
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sleep-map should wait until its necessity is demonstrated).
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Appendix A - Sample SOC node for MPC8540
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========================================
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@ -2487,47 +2520,48 @@ not necessary as they are usually the same as the root node.
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reg = <e0000000 00003000>;
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bus-frequency = <0>;
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mdio@24520 {
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reg = <24520 20>;
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device_type = "mdio";
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compatible = "gianfar";
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ethernet-phy@0 {
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linux,phandle = <2452000>
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interrupt-parent = <40000>;
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interrupts = <35 1>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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ethernet-phy@1 {
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linux,phandle = <2452001>
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interrupt-parent = <40000>;
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interrupts = <35 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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ethernet-phy@3 {
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linux,phandle = <2452002>
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interrupt-parent = <40000>;
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interrupts = <35 1>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@24000 {
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#size-cells = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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compatible = "gianfar", "simple-bus";
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reg = <24000 1000>;
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mac-address = [ 00 E0 0C 00 73 00 ];
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interrupts = <d 3 e 3 12 3>;
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interrupt-parent = <40000>;
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phy-handle = <2452000>;
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sleep = <&pmc 00000080>;
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ranges;
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mdio@24520 {
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reg = <24520 20>;
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compatible = "fsl,gianfar-mdio";
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ethernet-phy@0 {
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linux,phandle = <2452000>
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interrupt-parent = <40000>;
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interrupts = <35 1>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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ethernet-phy@1 {
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linux,phandle = <2452001>
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interrupt-parent = <40000>;
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interrupts = <35 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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ethernet-phy@3 {
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linux,phandle = <2452002>
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interrupt-parent = <40000>;
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interrupts = <35 1>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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};
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};
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ethernet@25000 {
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@ -2541,6 +2575,7 @@ not necessary as they are usually the same as the root node.
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interrupts = <13 3 14 3 18 3>;
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interrupt-parent = <40000>;
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phy-handle = <2452001>;
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sleep = <&pmc 00000040>;
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};
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ethernet@26000 {
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@ -2554,15 +2589,33 @@ not necessary as they are usually the same as the root node.
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interrupts = <19 3>;
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interrupt-parent = <40000>;
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phy-handle = <2452002>;
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sleep = <&pmc 00000020>;
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};
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serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <0>;
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interrupts = <1a 3>;
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interrupt-parent = <40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8540-duart", "simple-bus";
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sleep = <&pmc 00000002>;
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ranges;
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serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <0>;
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interrupts = <1a 3>;
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interrupt-parent = <40000>;
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};
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serial@4600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>;
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clock-frequency = <0>;
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interrupts = <1a 3>;
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interrupt-parent = <40000>;
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};
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};
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pic@40000 {
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@ -2581,6 +2634,11 @@ not necessary as they are usually the same as the root node.
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device_type = "i2c";
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compatible = "fsl-i2c";
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dfsrr;
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sleep = <&pmc 00000004>;
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};
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pmc: power@e0070 {
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compatible = "fsl,mpc8540-pmc", "fsl,mpc8548-pmc";
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reg = <e0070 20>;
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};
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};
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@ -0,0 +1,63 @@
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* Power Management Controller
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Properties:
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- compatible: "fsl,<chip>-pmc".
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"fsl,mpc8349-pmc" should be listed for any chip whose PMC is
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compatible. "fsl,mpc8313-pmc" should also be listed for any chip
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whose PMC is compatible, and implies deep-sleep capability.
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"fsl,mpc8548-pmc" should be listed for any chip whose PMC is
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compatible. "fsl,mpc8536-pmc" should also be listed for any chip
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whose PMC is compatible, and implies deep-sleep capability.
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"fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
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compatible; all statements below that apply to "fsl,mpc8548-pmc" also
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apply to "fsl,mpc8641d-pmc".
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Compatibility does not include bit assigments in SCCR/PMCDR/DEVDISR; these
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bit assigments are indicated via the sleep specifier in each device's
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sleep property.
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- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
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is the PMC block, and the second resource is the Clock Configuration
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block.
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For devices compatible with "fsl,mpc8548-pmc", the first resource
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is a 32-byte block beginning with DEVDISR.
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- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first
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resource is the PMC block interrupt.
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- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices,
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this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
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a wakeup source from deep sleep.
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Sleep specifiers:
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fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit
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that is set in the cell, the corresponding bit in SCCR will be saved
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and cleared on suspend, and restored on resume. This sleep controller
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supports disabling and resuming devices at any time.
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fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
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which will be ORed into PMCDR upon suspend, and cleared from PMCDR
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upon resume. The first two cells are as described for fsl,mpc8578-pmc.
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This sleep controller only supports disabling devices during system
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sleep, or permanently.
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fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
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first of which will be ORed into DEVDISR (and the second into
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DEVDISR2, if present -- this cell should be zero or absent if the
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hardware does not have DEVDISR2) upon a request for permanent device
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disabling. This sleep controller does not support configuring devices
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to disable during system sleep (unless supported by another compatible
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match), or dynamically.
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Example:
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power@b00 {
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compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
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reg = <0xb00 0x100 0xa00 0x100>;
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interrupts = <80 8>;
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};
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