tg3: fix MMIO for PPC 44x platforms
The driver stores the PCI resource addresses into 'unsigned long' variable before calling ioremap_nocache() on them. This warrants kernel oops when the registers are accessed on PPC 44x platforms which (being 32-bit) have PCI memory space mapped beyond 4 GB. The arch/ppc/ kernel has a fixup in ioremap() that creates an illusion that the PCI memory resource is mapped below 4 GB, but arch/powerpc/ code got rid of this trick, having instead CONFIG_RESOURCES_64BIT enabled. [ Bump driver version and release date -DaveM ] Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -64,8 +64,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.89"
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#define DRV_MODULE_RELDATE "April 03, 2008"
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#define DRV_MODULE_VERSION "3.90"
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#define DRV_MODULE_RELDATE "April 12, 2008"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@ -12578,7 +12578,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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static int tg3_version_printed = 0;
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unsigned long tg3reg_base, tg3reg_len;
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resource_size_t tg3reg_base;
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unsigned long tg3reg_len;
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struct net_device *dev;
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struct tg3 *tp;
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int err, pm_cap;
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