[ARM] pata_pxa: DMA-capable PATA driver
This patch adds a driver for a harddrive attached to PXA address and data bus. Unlike pata_platform, this driver allows usage of PXA DMA controller, making the transmission speed 3x higher. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
This commit is contained in:
Marek Vasut
Eric Miao
parent
406c86f11f
commit
2dc6c6f15d
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@ -0,0 +1,33 @@
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/*
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* Generic PXA PATA driver
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __MACH_PATA_PXA_H__
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#define __MACH_PATA_PXA_H__
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struct pata_pxa_pdata {
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/* PXA DMA DREQ<0:2> pin */
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uint32_t dma_dreq;
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/* Register shift */
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uint32_t reg_shift;
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/* IRQ flags */
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uint32_t irq_flags;
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};
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#endif /* __MACH_PATA_PXA_H__ */
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@ -642,6 +642,17 @@ config PATA_VIA
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If unsure, say N.
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config PATA_PXA
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tristate "PXA DMA-capable PATA support"
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depends on ARCH_PXA
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help
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This option enables support for harddrive attached to PXA CPU's bus.
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NOTE: This driver utilizes PXA DMA controller, in case your hardware
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is not capable of doing MWDMA, use pata_platform instead.
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If unsure, say N.
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config PATA_WINBOND
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tristate "Winbond SL82C105 PATA support"
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depends on PCI
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@ -89,6 +89,8 @@ obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
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obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
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obj-$(CONFIG_PATA_WINBOND_VLB) += pata_winbond.o
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obj-$(CONFIG_PATA_PXA) += pata_pxa.o
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# Should be last but two libata driver
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obj-$(CONFIG_PATA_ACPI) += pata_acpi.o
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# Should be last but one libata driver
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@ -0,0 +1,411 @@
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/*
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* Generic PXA PATA driver
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/ata.h>
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#include <linux/libata.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/completion.h>
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#include <scsi/scsi_host.h>
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#include <mach/pxa2xx-regs.h>
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#include <mach/pata_pxa.h>
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#include <mach/dma.h>
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#define DRV_NAME "pata_pxa"
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#define DRV_VERSION "0.1"
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struct pata_pxa_data {
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uint32_t dma_channel;
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struct pxa_dma_desc *dma_desc;
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dma_addr_t dma_desc_addr;
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uint32_t dma_desc_id;
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/* DMA IO physical address */
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uint32_t dma_io_addr;
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/* PXA DREQ<0:2> pin selector */
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uint32_t dma_dreq;
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/* DMA DCSR register value */
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uint32_t dma_dcsr;
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struct completion dma_done;
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};
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/*
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* Setup the DMA descriptors. The size is transfer capped at 4k per descriptor,
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* if the transfer is longer, it is split into multiple chained descriptors.
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*/
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static void pxa_load_dmac(struct scatterlist *sg, struct ata_queued_cmd *qc)
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{
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struct pata_pxa_data *pd = qc->ap->private_data;
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uint32_t cpu_len, seg_len;
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dma_addr_t cpu_addr;
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cpu_addr = sg_dma_address(sg);
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cpu_len = sg_dma_len(sg);
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do {
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seg_len = (cpu_len > 0x1000) ? 0x1000 : cpu_len;
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pd->dma_desc[pd->dma_desc_id].ddadr = pd->dma_desc_addr +
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((pd->dma_desc_id + 1) * sizeof(struct pxa_dma_desc));
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pd->dma_desc[pd->dma_desc_id].dcmd = DCMD_BURST32 |
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DCMD_WIDTH2 | (DCMD_LENGTH & seg_len);
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if (qc->tf.flags & ATA_TFLAG_WRITE) {
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pd->dma_desc[pd->dma_desc_id].dsadr = cpu_addr;
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pd->dma_desc[pd->dma_desc_id].dtadr = pd->dma_io_addr;
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pd->dma_desc[pd->dma_desc_id].dcmd |= DCMD_INCSRCADDR |
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DCMD_FLOWTRG;
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} else {
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pd->dma_desc[pd->dma_desc_id].dsadr = pd->dma_io_addr;
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pd->dma_desc[pd->dma_desc_id].dtadr = cpu_addr;
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pd->dma_desc[pd->dma_desc_id].dcmd |= DCMD_INCTRGADDR |
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DCMD_FLOWSRC;
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}
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cpu_len -= seg_len;
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cpu_addr += seg_len;
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pd->dma_desc_id++;
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} while (cpu_len);
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/* Should not happen */
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if (seg_len & 0x1f)
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DALGN |= (1 << pd->dma_dreq);
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}
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/*
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* Prepare taskfile for submission.
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*/
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static void pxa_qc_prep(struct ata_queued_cmd *qc)
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{
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struct pata_pxa_data *pd = qc->ap->private_data;
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int si = 0;
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struct scatterlist *sg;
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if (!(qc->flags & ATA_QCFLAG_DMAMAP))
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return;
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pd->dma_desc_id = 0;
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DCSR(pd->dma_channel) = 0;
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DALGN &= ~(1 << pd->dma_dreq);
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for_each_sg(qc->sg, sg, qc->n_elem, si)
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pxa_load_dmac(sg, qc);
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pd->dma_desc[pd->dma_desc_id - 1].ddadr = DDADR_STOP;
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/* Fire IRQ only at the end of last block */
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pd->dma_desc[pd->dma_desc_id - 1].dcmd |= DCMD_ENDIRQEN;
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DDADR(pd->dma_channel) = pd->dma_desc_addr;
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DRCMR(pd->dma_dreq) = DRCMR_MAPVLD | pd->dma_channel;
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}
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/*
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* Configure the DMA controller, load the DMA descriptors, but don't start the
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* DMA controller yet. Only issue the ATA command.
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*/
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static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
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{
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qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
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}
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/*
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* Execute the DMA transfer.
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*/
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static void pxa_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct pata_pxa_data *pd = qc->ap->private_data;
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init_completion(&pd->dma_done);
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DCSR(pd->dma_channel) = DCSR_RUN;
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}
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/*
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* Wait until the DMA transfer completes, then stop the DMA controller.
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*/
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static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct pata_pxa_data *pd = qc->ap->private_data;
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if ((DCSR(pd->dma_channel) & DCSR_RUN) &&
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wait_for_completion_timeout(&pd->dma_done, HZ))
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dev_err(qc->ap->dev, "Timeout waiting for DMA completion!");
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DCSR(pd->dma_channel) = 0;
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}
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/*
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* Read DMA status. The bmdma_stop() will take care of properly finishing the
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* DMA transfer so we always have DMA-complete interrupt here.
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*/
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static unsigned char pxa_bmdma_status(struct ata_port *ap)
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{
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struct pata_pxa_data *pd = ap->private_data;
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unsigned char ret = ATA_DMA_INTR;
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if (pd->dma_dcsr & DCSR_BUSERR)
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ret |= ATA_DMA_ERR;
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return ret;
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}
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/*
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* No IRQ register present so we do nothing.
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*/
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static void pxa_irq_clear(struct ata_port *ap)
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{
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}
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/*
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* Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
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* unclear why ATAPI has DMA issues.
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*/
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static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
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{
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return -EOPNOTSUPP;
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}
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static struct scsi_host_template pxa_ata_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations pxa_ata_port_ops = {
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.inherits = &ata_bmdma_port_ops,
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.cable_detect = ata_cable_40wire,
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.bmdma_setup = pxa_bmdma_setup,
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.bmdma_start = pxa_bmdma_start,
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.bmdma_stop = pxa_bmdma_stop,
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.bmdma_status = pxa_bmdma_status,
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.check_atapi_dma = pxa_check_atapi_dma,
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.sff_irq_clear = pxa_irq_clear,
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.qc_prep = pxa_qc_prep,
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};
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/*
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* DMA interrupt handler.
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*/
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static void pxa_ata_dma_irq(int dma, void *port)
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{
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struct ata_port *ap = port;
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struct pata_pxa_data *pd = ap->private_data;
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pd->dma_dcsr = DCSR(dma);
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DCSR(dma) = pd->dma_dcsr;
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if (pd->dma_dcsr & DCSR_STOPSTATE)
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complete(&pd->dma_done);
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}
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static int __devinit pxa_ata_probe(struct platform_device *pdev)
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{
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struct ata_host *host;
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struct ata_port *ap;
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struct pata_pxa_data *data;
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struct resource *cmd_res;
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struct resource *ctl_res;
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struct resource *dma_res;
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struct resource *irq_res;
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struct pata_pxa_pdata *pdata = pdev->dev.platform_data;
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int ret = 0;
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/*
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* Resource validation, three resources are needed:
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* - CMD port base address
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* - CTL port base address
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* - DMA port base address
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* - IRQ pin
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*/
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if (pdev->num_resources != 4) {
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dev_err(&pdev->dev, "invalid number of resources\n");
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return -EINVAL;
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}
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/*
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* CMD port base address
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*/
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cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (unlikely(cmd_res == NULL))
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return -EINVAL;
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/*
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* CTL port base address
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*/
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ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (unlikely(ctl_res == NULL))
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return -EINVAL;
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/*
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* DMA port base address
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*/
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dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (unlikely(dma_res == NULL))
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return -EINVAL;
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/*
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* IRQ pin
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*/
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irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (unlikely(irq_res == NULL))
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return -EINVAL;
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/*
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* Allocate the host
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*/
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host = ata_host_alloc(&pdev->dev, 1);
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if (!host)
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return -ENOMEM;
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ap = host->ports[0];
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ap->ops = &pxa_ata_port_ops;
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ap->pio_mask = ATA_PIO4;
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ap->mwdma_mask = ATA_MWDMA2;
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ap->flags = ATA_FLAG_MMIO;
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ap->ioaddr.cmd_addr = devm_ioremap(&pdev->dev, cmd_res->start,
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resource_size(cmd_res));
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ap->ioaddr.ctl_addr = devm_ioremap(&pdev->dev, ctl_res->start,
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resource_size(ctl_res));
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ap->ioaddr.bmdma_addr = devm_ioremap(&pdev->dev, dma_res->start,
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resource_size(dma_res));
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/*
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* Adjust register offsets
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*/
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ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
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ap->ioaddr.data_addr = ap->ioaddr.cmd_addr +
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(ATA_REG_DATA << pdata->reg_shift);
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ap->ioaddr.error_addr = ap->ioaddr.cmd_addr +
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(ATA_REG_ERR << pdata->reg_shift);
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ap->ioaddr.feature_addr = ap->ioaddr.cmd_addr +
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(ATA_REG_FEATURE << pdata->reg_shift);
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ap->ioaddr.nsect_addr = ap->ioaddr.cmd_addr +
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(ATA_REG_NSECT << pdata->reg_shift);
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ap->ioaddr.lbal_addr = ap->ioaddr.cmd_addr +
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(ATA_REG_LBAL << pdata->reg_shift);
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ap->ioaddr.lbam_addr = ap->ioaddr.cmd_addr +
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(ATA_REG_LBAM << pdata->reg_shift);
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ap->ioaddr.lbah_addr = ap->ioaddr.cmd_addr +
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(ATA_REG_LBAH << pdata->reg_shift);
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ap->ioaddr.device_addr = ap->ioaddr.cmd_addr +
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(ATA_REG_DEVICE << pdata->reg_shift);
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ap->ioaddr.status_addr = ap->ioaddr.cmd_addr +
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(ATA_REG_STATUS << pdata->reg_shift);
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ap->ioaddr.command_addr = ap->ioaddr.cmd_addr +
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(ATA_REG_CMD << pdata->reg_shift);
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/*
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* Allocate and load driver's internal data structure
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*/
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data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
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GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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ap->private_data = data;
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data->dma_dreq = pdata->dma_dreq;
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data->dma_io_addr = dma_res->start;
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/*
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* Allocate space for the DMA descriptors
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*/
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data->dma_desc = dmam_alloc_coherent(&pdev->dev, PAGE_SIZE,
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&data->dma_desc_addr, GFP_KERNEL);
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if (!data->dma_desc)
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return -EINVAL;
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/*
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* Request the DMA channel
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*/
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data->dma_channel = pxa_request_dma(DRV_NAME, DMA_PRIO_LOW,
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pxa_ata_dma_irq, ap);
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if (data->dma_channel < 0)
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return -EBUSY;
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/*
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* Stop and clear the DMA channel
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*/
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DCSR(data->dma_channel) = 0;
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/*
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* Activate the ATA host
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*/
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ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
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pdata->irq_flags, &pxa_ata_sht);
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if (ret)
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pxa_free_dma(data->dma_channel);
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return ret;
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}
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static int __devexit pxa_ata_remove(struct platform_device *pdev)
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{
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struct ata_host *host = dev_get_drvdata(&pdev->dev);
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struct pata_pxa_data *data = host->ports[0]->private_data;
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pxa_free_dma(data->dma_channel);
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ata_host_detach(host);
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return 0;
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}
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static struct platform_driver pxa_ata_driver = {
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.probe = pxa_ata_probe,
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.remove = __devexit_p(pxa_ata_remove),
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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};
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static int __init pxa_ata_init(void)
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{
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return platform_driver_register(&pxa_ata_driver);
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}
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static void __exit pxa_ata_exit(void)
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{
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platform_driver_unregister(&pxa_ata_driver);
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}
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|
||||
module_init(pxa_ata_init);
|
||||
module_exit(pxa_ata_exit);
|
||||
|
||||
MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
|
||||
MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
Loading…
Reference in New Issue