drm/tegra: dsi: Adjust D-PHY timing
Compliance testing shows that HS Trail is off by -12%. Increase the HS Trail time to make this test pass. Signed-off-by: David Ung <davidu@nvidia.com> [treding@nvidia.com: update specification references, add comment] Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -12,9 +12,9 @@
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#include "mipi-phy.h"
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/*
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* Default D-PHY timings based on MIPI D-PHY specification. Derived from
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* the valid ranges specified in Section 5.9 of the D-PHY specification
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* with minor adjustments.
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* Default D-PHY timings based on MIPI D-PHY specification. Derived from the
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* valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
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* specification (v1.2) with minor adjustments.
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*/
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int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
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unsigned long period)
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@ -34,7 +34,20 @@ int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
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timing->hszero = 145 + 5 * period;
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timing->hssettle = 85 + 6 * period;
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timing->hsskip = 40;
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timing->hstrail = max(8 * period, 60 + 4 * period);
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/*
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* The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
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* contains this formula as:
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*
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* T_HS-TRAIL = max(n * 8 * period, 60 + n * 4 * period)
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*
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* where n = 1 for forward-direction HS mode and n = 4 for reverse-
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* direction HS mode. There's only one setting and this function does
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* not parameterize on anything other that period, so this code will
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* assumes that reverse-direction HS mode is supported and uses n = 4.
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*/
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timing->hstrail = max(4 * 8 * period, 60 + 4 * 4 * period);
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timing->init = 100000;
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timing->lpx = 60;
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timing->taget = 5 * timing->lpx;
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@ -46,8 +59,8 @@ int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
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}
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/*
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* Validate D-PHY timing according to MIPI Alliance Specification for D-PHY,
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* Section 5.9 "Global Operation Timing Parameters".
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* Validate D-PHY timing according to MIPI D-PHY specification (v1.2, Section
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* Section 6.9 "Global Operation Timing Parameters").
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*/
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int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
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unsigned long period)
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