arm: dra7: add DESHDCP clock
Add a new Linux clock for DRA7 based SoCs to control DESHDCP clock. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com>
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@ -131,6 +131,11 @@
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regulator-max-microvolt = <3000000>;
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};
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};
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scm_conf_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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dra7_pmx_core: pinmux@1400 {
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@ -2136,3 +2136,13 @@
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clocks = <&dpll_usb_ck>;
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};
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};
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&scm_conf_clocks {
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dss_deshdcp_clk: dss_deshdcp_clk {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3_iclk_div>;
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ti,bit-shift = <0>;
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reg = <0x558>;
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};
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};
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@ -438,6 +438,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
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{ .role = "video2_clk", .clk = "dss_video2_clk" },
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{ .role = "video1_clk", .clk = "dss_video1_clk" },
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{ .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
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{ .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
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};
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static struct omap_hwmod dra7xx_dss_hwmod = {
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@ -305,6 +305,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
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DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
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DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
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DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
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DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"),
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{ .node_name = NULL },
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};
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