hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

x86/MCE: Export memory_error() 

Export the function which checks whether an MCE is a memory error to
other users so that we can reuse the logic. Drop the boot_cpu_data use,
while at it, as mce.cpuvendor already has the CPU vendor in there.

Integrate a piece from a patch from Vishal Verma
<vishal.l.verma@intel.com> to export it for modules (nfit).

The main reason we're exporting it is that the nfit handler
nfit_handle_mce() needs to detect a memory error properly before doing
its recovery actions.

Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: <stable@vger.kernel.org>
Link: http://lkml.kernel.org/r/20170519093915.15413-2-bp@alien8.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Borislav Petkov 2017-05-19 11:39:09 +02:00 committed by Thomas Gleixner
parent 56f410cf45
commit 2d1f406139
2 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/x86/include/asm/mce.h
View File

@ -266,6 +266,7 @@ static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *s
#endif #endif
int mce_available(struct cpuinfo_x86 *c); int mce_available(struct cpuinfo_x86 *c);
bool mce_is_memory_error(struct mce *m);
DECLARE_PER_CPU(unsigned, mce_exception_count); DECLARE_PER_CPU(unsigned, mce_exception_count);
DECLARE_PER_CPU(unsigned, mce_poll_count); DECLARE_PER_CPU(unsigned, mce_poll_count);

13
arch/x86/kernel/cpu/mcheck/mce.c
View File

@ -499,16 +499,14 @@ static int mce_usable_address(struct mce *m)
return 1; return 1;
} }
static bool memory_error(struct mce *m) bool mce_is_memory_error(struct mce *m)
{ {
struct cpuinfo_x86 *c = &boot_cpu_data; if (m->cpuvendor == X86_VENDOR_AMD) {
if (c->x86_vendor == X86_VENDOR_AMD) {
/* ErrCodeExt[20:16] */ /* ErrCodeExt[20:16] */
u8 xec = (m->status >> 16) & 0x1f; u8 xec = (m->status >> 16) & 0x1f;
return (xec == 0x0 || xec == 0x8); return (xec == 0x0 || xec == 0x8);
} else if (c->x86_vendor == X86_VENDOR_INTEL) { } else if (m->cpuvendor == X86_VENDOR_INTEL) {
/* /*
* Intel SDM Volume 3B - 15.9.2 Compound Error Codes * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
* *
@ -529,6 +527,7 @@ static bool memory_error(struct mce *m)
return false; return false;
} }
EXPORT_SYMBOL_GPL(mce_is_memory_error);
static bool cec_add_mce(struct mce *m) static bool cec_add_mce(struct mce *m)
{ {
@ -536,7 +535,7 @@ static bool cec_add_mce(struct mce *m)
return false; return false;
/* We eat only correctable DRAM errors with usable addresses. */ /* We eat only correctable DRAM errors with usable addresses. */
if (memory_error(m) && if (mce_is_memory_error(m) &&
!(m->status & MCI_STATUS_UC) && !(m->status & MCI_STATUS_UC) &&
mce_usable_address(m)) mce_usable_address(m))
if (!cec_add_elem(m->addr >> PAGE_SHIFT)) if (!cec_add_elem(m->addr >> PAGE_SHIFT))
@ -713,7 +712,7 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) if (severity == MCE_DEFERRED_SEVERITY && mce_is_memory_error(&m))
if (m.status & MCI_STATUS_ADDRV) if (m.status & MCI_STATUS_ADDRV)
m.severity = severity; m.severity = severity;