IOMMU Fixes for Linux v5.9-rc3
Including: - Three Intel VT-d fixes to fix address handling on 32bit, fix a NULL pointer dereference bug and serialize a hardware register access as required by the VT-d spec. - Two patches for AMD IOMMU to force AMD GPUs into translation mode when memory encryption is active and disallow using IOMMUv2 functionality. This makes the AMDGPU driver working when memory encryption is active. - Two more fixes for AMD IOMMU to fix updating the Interrupt Remapping Table Entries. - MAINTAINERS file update for the Qualcom IOMMU driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAl9U+Q4ACgkQK/BELZcB GuOkexAA14LsYG8QWd1lwgf3Yh6/xGwhw/vDTHCMCNqFCMUHTLjte6uLZ9QH/Pxy fvwyX73ZOjsrKXOwkKvEFD9fCJDyMsPsfH3ssYNgOZfTFculcGdNc6NhLWhoKCc8 pmM0tVikRKxhAMxWgc9EX4dwu9WRe8vobvZj0cAPFlMAkY2ZY3lDtl8bniX9cygW Oo2hmhud1CeLE3ffUWhWgT9T7GfTL1i6KFF8wUqrNFE53+b7pS4LbJaCWuHKjtKu MaBC0eE0rG0qvSng6ArdZx22a47o2j57zc0mG6IeHtGe7eUAgwNkRLQmL1RU35xW cDniCJXosQ7DJ0Hel12ahk1HlUQFFqMlZVZbNpYP04v8xqHNEsWvWHw2NS6xZg2T FozBWdnhw8HzaXpWmg14WQ+e9+rnsK/FndRxBjXP9H9bKQQNKQV8PaiUEQCZin0s QJohAgqyjyPLB3a/B9q1jzG5HHI2pK2s2/4ry9XBdijZ7MhADq9pAvAe9k8baU/5 gEy6pa4PmZEMibbrfUNjIoeYz80hDaHIxIbW/fFgl5n1JJJoz+qsfZlYaddrN6nc XFWDg9dDgQjDaYDjK9uG2vJkbMFiqE0kRxtJdWfqZNGgSWxqVIMtf42ZvYlqH+Wb Zc9nBEuH27o4NZ//2mXzynwBooBTmOsLRw/kqSPOuBVMki08fqk= =2uqs -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v5.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu fixes from Joerg Roedel: - three Intel VT-d fixes to fix address handling on 32bit, fix a NULL pointer dereference bug and serialize a hardware register access as required by the VT-d spec. - two patches for AMD IOMMU to force AMD GPUs into translation mode when memory encryption is active and disallow using IOMMUv2 functionality. This makes the AMDGPU driver work when memory encryption is active. - two more fixes for AMD IOMMU to fix updating the Interrupt Remapping Table Entries. - MAINTAINERS file update for the Qualcom IOMMU driver. * tag 'iommu-fixes-v5.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/vt-d: Handle 36bit addressing for x86-32 iommu/amd: Do not use IOMMUv2 functionality when SME is active iommu/amd: Do not force direct mapping when SME is active iommu/amd: Use cmpxchg_double() when updating 128-bit IRTE iommu/amd: Restore IRTE.RemapEn bit after programming IRTE iommu/vt-d: Fix NULL pointer dereference in dev_iommu_priv_set() iommu/vt-d: Serialize IOMMU GCMD register modifications MAINTAINERS: Update QUALCOMM IOMMU after Arm SMMU drivers move
This commit is contained in:
Linus Torvalds
commit
2ccdd9f8b2
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@ -14388,7 +14388,7 @@ M: Rob Clark <robdclark@gmail.com>
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L: iommu@lists.linux-foundation.org
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L: linux-arm-msm@vger.kernel.org
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S: Maintained
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F: drivers/iommu/qcom_iommu.c
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F: drivers/iommu/arm/arm-smmu/qcom_iommu.c
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QUALCOMM IPCC MAILBOX DRIVER
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M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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@ -10,7 +10,7 @@ config AMD_IOMMU
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select IOMMU_API
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select IOMMU_IOVA
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select IOMMU_DMA
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depends on X86_64 && PCI && ACPI
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depends on X86_64 && PCI && ACPI && HAVE_CMPXCHG_DOUBLE
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help
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With this option you can enable support for AMD IOMMU hardware in
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your system. An IOMMU is a hardware component which provides
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@ -1511,7 +1511,14 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
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iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
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else
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iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
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if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
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/*
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* Note: GA (128-bit IRTE) mode requires cmpxchg16b supports.
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* GAM also requires GA mode. Therefore, we need to
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* check cmpxchg16b support before enabling it.
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*/
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if (!boot_cpu_has(X86_FEATURE_CX16) ||
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((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
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break;
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case 0x11:
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@ -1520,8 +1527,18 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
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iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
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else
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iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
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if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
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/*
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* Note: GA (128-bit IRTE) mode requires cmpxchg16b supports.
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* XT, GAM also requires GA mode. Therefore, we need to
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* check cmpxchg16b support before enabling them.
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*/
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if (!boot_cpu_has(X86_FEATURE_CX16) ||
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((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) {
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
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break;
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}
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/*
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* Note: Since iommu_update_intcapxt() leverages
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* the IOMMU MMIO access to MSI capability block registers
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@ -2659,7 +2659,12 @@ static int amd_iommu_def_domain_type(struct device *dev)
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if (!dev_data)
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return 0;
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if (dev_data->iommu_v2)
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/*
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* Do not identity map IOMMUv2 capable devices when memory encryption is
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* active, because some of those devices (AMD GPUs) don't have the
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* encryption bit in their DMA-mask and require remapping.
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*/
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if (!mem_encrypt_active() && dev_data->iommu_v2)
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return IOMMU_DOMAIN_IDENTITY;
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return 0;
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@ -3292,6 +3297,7 @@ out:
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static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
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struct amd_ir_data *data)
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{
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bool ret;
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struct irq_remap_table *table;
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struct amd_iommu *iommu;
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unsigned long flags;
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@ -3309,10 +3315,18 @@ static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
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entry = (struct irte_ga *)table->table;
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entry = &entry[index];
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entry->lo.fields_remap.valid = 0;
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entry->hi.val = irte->hi.val;
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entry->lo.val = irte->lo.val;
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entry->lo.fields_remap.valid = 1;
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ret = cmpxchg_double(&entry->lo.val, &entry->hi.val,
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entry->lo.val, entry->hi.val,
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irte->lo.val, irte->hi.val);
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/*
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* We use cmpxchg16 to atomically update the 128-bit IRTE,
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* and it cannot be updated by the hardware or other processors
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* behind us, so the return value of cmpxchg16 should be the
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* same as the old value.
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*/
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WARN_ON(!ret);
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if (data)
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data->ref = entry;
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@ -3850,6 +3864,7 @@ int amd_iommu_deactivate_guest_mode(void *data)
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struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
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struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
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struct irq_cfg *cfg = ir_data->cfg;
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u64 valid = entry->lo.fields_remap.valid;
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if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
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!entry || !entry->lo.fields_vapic.guest_mode)
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@ -3858,6 +3873,7 @@ int amd_iommu_deactivate_guest_mode(void *data)
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entry->lo.val = 0;
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entry->hi.val = 0;
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entry->lo.fields_remap.valid = valid;
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entry->lo.fields_remap.dm = apic->irq_dest_mode;
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entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
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entry->hi.fields.vector = cfg->vector;
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@ -737,6 +737,13 @@ int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
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might_sleep();
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/*
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* When memory encryption is active the device is likely not in a
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* direct-mapped domain. Forbid using IOMMUv2 functionality for now.
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*/
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if (mem_encrypt_active())
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return -ENODEV;
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if (!amd_iommu_v2_supported())
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return -ENODEV;
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@ -123,29 +123,29 @@ static inline unsigned int level_to_offset_bits(int level)
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return (level - 1) * LEVEL_STRIDE;
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}
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static inline int pfn_level_offset(unsigned long pfn, int level)
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static inline int pfn_level_offset(u64 pfn, int level)
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{
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return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
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}
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static inline unsigned long level_mask(int level)
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static inline u64 level_mask(int level)
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{
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return -1UL << level_to_offset_bits(level);
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return -1ULL << level_to_offset_bits(level);
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}
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static inline unsigned long level_size(int level)
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static inline u64 level_size(int level)
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{
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return 1UL << level_to_offset_bits(level);
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return 1ULL << level_to_offset_bits(level);
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}
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static inline unsigned long align_to_level(unsigned long pfn, int level)
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static inline u64 align_to_level(u64 pfn, int level)
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{
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return (pfn + level_size(level) - 1) & level_mask(level);
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}
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static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
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{
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return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
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return 1UL << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
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}
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/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
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@ -364,7 +364,6 @@ static int iommu_skip_te_disable;
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int intel_iommu_gfx_mapped;
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EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
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#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
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#define DEFER_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-2))
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struct device_domain_info *get_domain_info(struct device *dev)
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{
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@ -374,8 +373,7 @@ struct device_domain_info *get_domain_info(struct device *dev)
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return NULL;
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info = dev_iommu_priv_get(dev);
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if (unlikely(info == DUMMY_DEVICE_DOMAIN_INFO ||
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info == DEFER_DEVICE_DOMAIN_INFO))
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if (unlikely(info == DEFER_DEVICE_DOMAIN_INFO))
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return NULL;
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return info;
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@ -742,11 +740,6 @@ struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
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return &context[devfn];
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}
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static int iommu_dummy(struct device *dev)
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{
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return dev_iommu_priv_get(dev) == DUMMY_DEVICE_DOMAIN_INFO;
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}
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static bool attach_deferred(struct device *dev)
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{
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return dev_iommu_priv_get(dev) == DEFER_DEVICE_DOMAIN_INFO;
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@ -779,6 +772,53 @@ is_downstream_to_pci_bridge(struct device *dev, struct device *bridge)
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return false;
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}
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static bool quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
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{
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struct dmar_drhd_unit *drhd;
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u32 vtbar;
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int rc;
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/* We know that this device on this chipset has its own IOMMU.
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* If we find it under a different IOMMU, then the BIOS is lying
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* to us. Hope that the IOMMU for this device is actually
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* disabled, and it needs no translation...
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*/
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rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
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if (rc) {
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/* "can't" happen */
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dev_info(&pdev->dev, "failed to run vt-d quirk\n");
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return false;
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}
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vtbar &= 0xffff0000;
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/* we know that the this iommu should be at offset 0xa000 from vtbar */
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drhd = dmar_find_matched_drhd_unit(pdev);
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if (!drhd || drhd->reg_base_addr - vtbar != 0xa000) {
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pr_warn_once(FW_BUG "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n");
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add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
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return true;
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}
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return false;
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}
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static bool iommu_is_dummy(struct intel_iommu *iommu, struct device *dev)
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{
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if (!iommu || iommu->drhd->ignored)
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return true;
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if (dev_is_pci(dev)) {
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struct pci_dev *pdev = to_pci_dev(dev);
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SNB &&
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quirk_ioat_snb_local_iommu(pdev))
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return true;
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}
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return false;
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}
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struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
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{
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struct dmar_drhd_unit *drhd = NULL;
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@ -788,7 +828,7 @@ struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
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u16 segment = 0;
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int i;
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if (!dev || iommu_dummy(dev))
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if (!dev)
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return NULL;
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if (dev_is_pci(dev)) {
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@ -805,7 +845,7 @@ struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
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dev = &ACPI_COMPANION(dev)->dev;
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rcu_read_lock();
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for_each_active_iommu(iommu, drhd) {
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for_each_iommu(iommu, drhd) {
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if (pdev && segment != drhd->segment)
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continue;
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|
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@ -841,6 +881,9 @@ struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
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}
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iommu = NULL;
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out:
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if (iommu_is_dummy(iommu, dev))
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iommu = NULL;
|
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|
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rcu_read_unlock();
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|
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return iommu;
|
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|
|
@ -2447,7 +2490,7 @@ struct dmar_domain *find_domain(struct device *dev)
|
|||
{
|
||||
struct device_domain_info *info;
|
||||
|
||||
if (unlikely(attach_deferred(dev) || iommu_dummy(dev)))
|
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if (unlikely(attach_deferred(dev)))
|
||||
return NULL;
|
||||
|
||||
/* No lock here, assumes no domain exit in normal case */
|
||||
|
|
@ -3989,35 +4032,6 @@ static void __init iommu_exit_mempool(void)
|
|||
iova_cache_put();
|
||||
}
|
||||
|
||||
static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
|
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{
|
||||
struct dmar_drhd_unit *drhd;
|
||||
u32 vtbar;
|
||||
int rc;
|
||||
|
||||
/* We know that this device on this chipset has its own IOMMU.
|
||||
* If we find it under a different IOMMU, then the BIOS is lying
|
||||
* to us. Hope that the IOMMU for this device is actually
|
||||
* disabled, and it needs no translation...
|
||||
*/
|
||||
rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
|
||||
if (rc) {
|
||||
/* "can't" happen */
|
||||
dev_info(&pdev->dev, "failed to run vt-d quirk\n");
|
||||
return;
|
||||
}
|
||||
vtbar &= 0xffff0000;
|
||||
|
||||
/* we know that the this iommu should be at offset 0xa000 from vtbar */
|
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drhd = dmar_find_matched_drhd_unit(pdev);
|
||||
if (!drhd || drhd->reg_base_addr - vtbar != 0xa000) {
|
||||
pr_warn_once(FW_BUG "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n");
|
||||
add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
|
||||
dev_iommu_priv_set(&pdev->dev, DUMMY_DEVICE_DOMAIN_INFO);
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
|
||||
|
||||
static void __init init_no_remapping_devices(void)
|
||||
{
|
||||
struct dmar_drhd_unit *drhd;
|
||||
|
|
@ -4049,12 +4063,8 @@ static void __init init_no_remapping_devices(void)
|
|||
/* This IOMMU has *only* gfx devices. Either bypass it or
|
||||
set the gfx_mapped flag, as appropriate */
|
||||
drhd->gfx_dedicated = 1;
|
||||
if (!dmar_map_gfx) {
|
||||
if (!dmar_map_gfx)
|
||||
drhd->ignored = 1;
|
||||
for_each_active_dev_scope(drhd->devices,
|
||||
drhd->devices_cnt, i, dev)
|
||||
dev_iommu_priv_set(dev, DUMMY_DEVICE_DOMAIN_INFO);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -508,12 +508,18 @@ static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
|
|||
|
||||
/* Enable interrupt-remapping */
|
||||
iommu->gcmd |= DMA_GCMD_IRE;
|
||||
iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
|
||||
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
|
||||
|
||||
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
||||
readl, (sts & DMA_GSTS_IRES), sts);
|
||||
|
||||
/* Block compatibility-format MSIs */
|
||||
if (sts & DMA_GSTS_CFIS) {
|
||||
iommu->gcmd &= ~DMA_GCMD_CFI;
|
||||
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
|
||||
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
||||
readl, !(sts & DMA_GSTS_CFIS), sts);
|
||||
}
|
||||
|
||||
/*
|
||||
* With CFI clear in the Global Command register, we should be
|
||||
* protected from dangerous (i.e. compatibility) interrupts
|
||||
|
|
|
|||
Loading…
Reference in New Issue