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Renesas ARM Based SoC DT Updates for v4.16 

* Convert to named i2c-gpio bindings
 
   Geert Uytterhoeven says "Commits 7d29f509d2 ("dt-bindings: i2c:
   i2c-gpio: Add support for named gpios") and 05c7477885 ("i2c: gpio:
   Add support for named gpios in DT") introduced named i2c-gpio DT
   bindings, and deprecated the more error-prone unnamed variant.
 
   This patch series switches all Renesas boards to the new bindings, and
   adds the missing GPIO_OPEN_DRAIN I/O flags, which were implicitly
   assumed before..."
 
   ...  Note that after this series is applied, the i2c-gpio buses are no
   longer detected when booting new DTBs on old (v4.14 and older) kernels,
   which should not be an issue.  Booting old DTBs on new kernels is not
   affected."
 
 * Update DTS for CMT DT binding rework
 
   Geert Uytterhoeven says "This patch series updates the CMT device nodes
   in the various Renesas DTS files sh_cmt clocksource driver for the recent
   DT binding rework that was merged in v4.14-rc1 and v4.15-rc1..."
 
 * Add SMP support to r8a7794 (R-Car E2) SoC
 
   Sergei Shtylyov says "Add the device tree node for the Advanced Power
   Management Unit (APMU).  Use the "enable-method" prop to  point out that
   the APMU should be used for the SMP support."
 
 * Correct primary compatible value for eeprom
   on r7s72100 (RZ/A1H) genmai and r8a7791 (R-Car M2-W) koelsh boards
 
   Geert Uytterhoeven says "The Renesas part numbers of the two-wire serial
   interface EEPROMs do not follow the 24Cxx pattern, but the R1EX24xxx
   pattern.
 
   Hence change the primary compatible values to the appropriate variant of
   "renesas,r1ex24xxx", like is already done on Gose.""
 
 * Move cec_clock to root node on r8a7791 (R-Car M2-W) koelsh board
   r8a7791 (R-Car M2-W) koelsh board
 
 * Use R-Car SDHI and Ether Gen1 and 2 fallback compat strings
 
   Use recently posted R-Car SDHI and Ether Gen 1 and 2 fallback
   compat strings in the DT of Renesas ARM based SoCs.
 
 * Add IIC cores to dtsi of r8a7745 (RZ/G1E) SoC
 
 * Rework DT architecture for r8a7745 (RZ/G1E) iW-RainboW-G22D development
   platform and add serial support.
 
   Fabrizio Castro says "... define a new DT architecture for the
   iW-RainboW-G22D SODIMM Development Platform to include the configuration
   with the HDMI daughter board and to define the serial interfaces."
 
 * Add USB function support to
   r8a7745 (RZ/G1E) iW-RainboW-G22D development platform
 
 * Add PCIEC and ttySC3 support to r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM
 
 * Add VIN support to r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs
 
 * Add CAN and HDMI support to r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and
   r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms
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Merge tag 'renesas-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Renesas ARM Based SoC DT Updates for v4.16" from Simon Horman:

* Convert to named i2c-gpio bindings

  Geert Uytterhoeven says "Commits 7d29f509d2 ("dt-bindings: i2c:
  i2c-gpio: Add support for named gpios") and 05c7477885 ("i2c: gpio:
  Add support for named gpios in DT") introduced named i2c-gpio DT
  bindings, and deprecated the more error-prone unnamed variant.

  This patch series switches all Renesas boards to the new bindings, and
  adds the missing GPIO_OPEN_DRAIN I/O flags, which were implicitly
  assumed before..."

  ...  Note that after this series is applied, the i2c-gpio buses are no
  longer detected when booting new DTBs on old (v4.14 and older) kernels,
  which should not be an issue.  Booting old DTBs on new kernels is not
  affected."

* Update DTS for CMT DT binding rework

  Geert Uytterhoeven says "This patch series updates the CMT device nodes
  in the various Renesas DTS files sh_cmt clocksource driver for the recent
  DT binding rework that was merged in v4.14-rc1 and v4.15-rc1..."

* Add SMP support to r8a7794 (R-Car E2) SoC

  Sergei Shtylyov says "Add the device tree node for the Advanced Power
  Management Unit (APMU).  Use the "enable-method" prop to  point out that
  the APMU should be used for the SMP support."

* Correct primary compatible value for eeprom
  on r7s72100 (RZ/A1H) genmai and r8a7791 (R-Car M2-W) koelsh boards

  Geert Uytterhoeven says "The Renesas part numbers of the two-wire serial
  interface EEPROMs do not follow the 24Cxx pattern, but the R1EX24xxx
  pattern.

  Hence change the primary compatible values to the appropriate variant of
  "renesas,r1ex24xxx", like is already done on Gose.""

* Move cec_clock to root node on r8a7791 (R-Car M2-W) koelsh board
  r8a7791 (R-Car M2-W) koelsh board

* Use R-Car SDHI and Ether Gen1 and 2 fallback compat strings

  Use recently posted R-Car SDHI and Ether Gen 1 and 2 fallback
  compat strings in the DT of Renesas ARM based SoCs.

* Add IIC cores to dtsi of r8a7745 (RZ/G1E) SoC

* Rework DT architecture for r8a7745 (RZ/G1E) iW-RainboW-G22D development
  platform and add serial support.

  Fabrizio Castro says "... define a new DT architecture for the
  iW-RainboW-G22D SODIMM Development Platform to include the configuration
  with the HDMI daughter board and to define the serial interfaces."

* Add USB function support to
  r8a7745 (RZ/G1E) iW-RainboW-G22D development platform

* Add PCIEC and ttySC3 support to r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM

* Add VIN support to r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs

* Add CAN and HDMI support to r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and
  r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms

* tag 'renesas-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (61 commits)
  ARM: dts: alt: Convert to named i2c-gpio bindings
  ARM: dts: koelsch: Convert to named i2c-gpio bindings
  ARM: dts: lager: Convert to named i2c-gpio bindings
  ARM: dts: armadillo800eva: Convert to named i2c-gpio bindings
  ARM: dts: sh73a0: Remove CMT renesas,channels-mask
  ARM: dts: r8a7794: Remove CMT renesas,channels-mask
  ARM: dts: r8a7793: Remove CMT renesas,channels-mask
  ARM: dts: r8a7791: Remove CMT renesas,channels-mask
  ARM: dts: r8a7790: Remove CMT renesas,channels-mask
  ARM: dts: r8a7740: Remove CMT renesas,channels-mask
  ARM: dts: r8a73a4: Remove CMT renesas,channels-mask
  ARM: dts: r8a7794: Update CMT compat strings
  ARM: dts: r8a7793: Update CMT compat strings
  ARM: dts: r8a7791: Update CMT compat strings
  ARM: dts: r8a7790: Update CMT compat strings
  ARM: dts: r8a73a4: Update CMT compat string
  ARM: dts: r8a7794: Add SMP support
  ARM: dts: genmai: Correct primary compatible value for eeprom
  ARM: dts: koelsch: Correct primary compatible value for eeprom
  ARM: dts: r8a7745: add VIN dt support
  ...
This commit is contained in:
Arnd Bergmann 2017-12-21 16:19:42 +01:00
parent 74f256a5cc 7f32eddb81
commit 2c25291762
22 changed files with 760 additions and 126 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@ -754,6 +754,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \

34
arch/arm/boot/dts/iwg20d-q7-common.dtsi
View File

@ -11,6 +11,7 @@
/ {
aliases {
serial0 = &scif0;
serial3 = &scifb1;
ethernet0 = &avb;
};
@ -58,6 +59,13 @@
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&hsusb {
status = "okay";
pinctrl-0 = <&usb0_pins>;
@ -88,7 +96,20 @@
pinctrl-names = "default";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pciec {
status = "okay";
};
&pfc {
can0_pins: can0 {
groups = "can0_data_d";
function = "can0";
};
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
@ -104,6 +125,11 @@
function = "scif0";
};
scifb1_pins: scifb1 {
groups = "scifb1_data_d", "scifb1_ctrl";
function = "scifb1";
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
@ -134,6 +160,14 @@
status = "okay";
};
&scifb1 {
pinctrl-0 = <&scifb1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;

87
arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
View File

@ -13,6 +13,44 @@
serial1 = &scif1;
serial4 = &hscif1;
};
cec_clock: cec-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
&hscif1 {
@ -23,7 +61,56 @@
status = "okay";
};
&i2c5 {
status = "okay";
clock-frequency = <400000>;
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio0>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cec_clock>;
clock-names = "cec";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
};
&pfc {
can1_pins: can1 {
groups = "can1_data_d";
function = "can1";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
function = "du";
};
hscif1_pins: hscif1 {
groups = "hscif1_data_c", "hscif1_ctrl_c";
function = "hscif1";

2
arch/arm/boot/dts/r7s72100-genmai.dts
View File

@ -123,7 +123,7 @@
pinctrl-0 = <&i2c2_pins>;
eeprom@50 {
compatible = "renesas,24c128", "atmel,24c128";
compatible = "renesas,r1ex24128", "atmel,24c128";
reg = <0x50>;
pagesize = <64>;
};

5
arch/arm/boot/dts/r8a73a4.dtsi
View File

@ -132,15 +132,12 @@
};
cmt1: timer@e6130000 {
compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
clock-names = "fck";
power-domains = <&pd_c5>;
renesas,channels-mask = <0xff>;
status = "disabled";
};

5
arch/arm/boot/dts/r8a7740-armadillo800eva.dts
View File

@ -131,9 +131,8 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
&pfc 91 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&pfc 208 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&pfc 91 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};

3
arch/arm/boot/dts/r8a7740.dtsi
View File

@ -74,9 +74,6 @@
clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
clock-names = "fck";
power-domains = <&pd_c5>;
renesas,channels-mask = <0x3f>;
status = "disabled";
};

149
arch/arm/boot/dts/r8a7743.dtsi
View File

@ -32,6 +32,9 @@
spi1 = &msiof0;
spi2 = &msiof1;
spi3 = &msiof2;
vin0 = &vin0;
vin1 = &vin1;
vin2 = &vin2;
};
cpus {
@ -827,7 +830,8 @@
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7743";
compatible = "renesas,ether-r8a7743",
"renesas,rcar-gen2-ether";
reg = <0 0xee700000 0 0x400>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;
@ -953,7 +957,8 @@
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7743";
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
@ -967,7 +972,8 @@
};
sdhi1: sd@ee140000 {
compatible = "renesas,sdhi-r8a7743";
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
@ -981,7 +987,8 @@
};
sdhi2: sd@ee160000 {
compatible = "renesas,sdhi-r8a7743";
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
@ -1033,6 +1040,97 @@
};
};
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7743",
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 811>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 811>;
status = "disabled";
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7743",
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 810>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 810>;
status = "disabled";
};
vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a7743",
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 809>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 809>;
status = "disabled";
};
du: display@feb00000 {
compatible = "renesas,du-r8a7743";
reg = <0 0xfeb00000 0 0x40000>,
<0 0xfeb90000 0 0x1c>;
reg-names = "du", "lvds.0";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 726>;
clock-names = "du.0", "du.1", "lvds.0";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
};
};
};
};
can0: can@e6e80000 {
compatible = "renesas,can-r8a7743",
"renesas,rcar-gen2-can";
reg = <0 0xe6e80000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A7743_CLK_RCAN>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
can1: can@e6e88000 {
compatible = "renesas,can-r8a7743",
"renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A7743_CLK_RCAN>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7743",
"renesas,pci-rcar-gen2";
@ -1102,6 +1200,34 @@
phy-names = "usb";
};
};
pciec: pcie@fe000000 {
compatible = "renesas,pcie-r8a7743",
"renesas,pcie-rcar-gen2";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 319>;
status = "disabled";
};
};
/* External root clock */
@ -1119,6 +1245,21 @@
clock-frequency = <48000000>;
};
/* External CAN clock */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";

158
arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts Normal file
View File

@ -0,0 +1,158 @@
/*
* Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter
* board
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "r8a7745-iwg22d-sodimm.dts"
/ {
model = "iWave RainboW-G22D-SODIMM RZ/G1E based board with HDMI add-on";
compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";
aliases {
serial0 = &scif1;
serial4 = &scif5;
serial6 = &hscif2;
};
cec_clock: cec-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
};
&du {
pinctrl-0 = <&du0_pins>;
pinctrl-names = "default";
status = "okay";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&hscif2 {
pinctrl-0 = <&hscif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cec_clock>;
clock-names = "cec";
pd-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb0>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&pfc {
can1_pins: can1 {
groups = "can1_data_b";
function = "can1";
};
du0_pins: du0 {
groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
function = "du0";
};
hscif2_pins: hscif2 {
groups = "hscif2_data";
function = "hscif2";
};
i2c1_pins: i2c1 {
groups = "i2c1_d";
function = "i2c1";
};
scif1_pins: scif1 {
groups = "scif1_data";
function = "scif1";
};
scif5_pins: scif5 {
groups = "scif5_data_d";
function = "scif5";
};
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif5 {
pinctrl-0 = <&scif5_pins>;
pinctrl-names = "default";
status = "okay";
};

113
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
View File

@ -16,13 +16,14 @@
compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";
aliases {
serial0 = &scif4;
ethernet0 = &avb;
serial3 = &scif4;
serial5 = &hscif1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
stdout-path = "serial3:115200n8";
};
vccq_sdhi0: regulator-vccq-sdhi0 {
@ -39,36 +40,6 @@
};
};
&pfc {
scif4_pins: scif4 {
groups = "scif4_data_b";
function = "scif4";
};
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
};
};
&scif4 {
pinctrl-0 = <&scif4_pins>;
pinctrl-names = "default";
status = "okay";
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
@ -88,6 +59,78 @@
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&hsusb {
status = "okay";
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
};
&pci1 {
status = "okay";
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
};
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
};
can0_pins: can0 {
groups = "can0_data";
function = "can0";
};
hscif1_pins: hscif1 {
groups = "hscif1_data", "hscif1_ctrl";
function = "hscif1";
};
scif4_pins: scif4 {
groups = "scif4_data_b";
function = "scif4";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
};
};
&scif4 {
pinctrl-0 = <&scif4_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
@ -98,12 +141,6 @@
status = "okay";
};
&pci1 {
status = "okay";
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
};
&usbphy {
status = "okay";
};

180
arch/arm/boot/dts/r8a7745.dtsi
View File

@ -25,10 +25,14 @@
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &iic0;
i2c7 = &iic1;
spi0 = &qspi;
spi1 = &msiof0;
spi2 = &msiof1;
spi3 = &msiof2;
vin0 = &vin0;
vin1 = &vin1;
};
cpus {
@ -312,6 +316,34 @@
dma-channels = <15>;
};
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a7745-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 330>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb_dmac1: dma-controller@e65b0000 {
compatible = "renesas,r8a7745-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 331>;
#dma-cells = <1>;
dma-channels = <2>;
};
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7745",
"renesas,rcar-gen2-scifa", "renesas,scifa";
@ -615,7 +647,8 @@
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7745";
compatible = "renesas,ether-r8a7745",
"renesas,rcar-gen2-ether";
reg = <0 0xee700000 0 0x400>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;
@ -724,6 +757,40 @@
status = "disabled";
};
iic0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7745",
"renesas,rcar-gen2-iic",
"renesas,rmobile-iic";
reg = <0 0xe6500000 0 0x425>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 318>;
dmas = <&dmac0 0x61>, <&dmac0 0x62>,
<&dmac1 0x61>, <&dmac1 0x62>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 318>;
status = "disabled";
};
iic1: i2c@e6510000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7745",
"renesas,rcar-gen2-iic",
"renesas,rmobile-iic";
reg = <0 0xe6510000 0 0x425>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 323>;
dmas = <&dmac0 0x65>, <&dmac0 0x66>,
<&dmac1 0x65>, <&dmac1 0x66>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 323>;
status = "disabled";
};
mmcif0: mmc@ee200000 {
compatible = "renesas,mmcif-r8a7745",
"renesas,sh-mmcif";
@ -756,6 +823,55 @@
status = "disabled";
};
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7745",
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 811>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 811>;
status = "disabled";
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7745",
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 810>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 810>;
status = "disabled";
};
du: display@feb00000 {
compatible = "renesas,du-r8a7745";
reg = <0 0xfeb00000 0 0x40000>;
reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb0: endpoint {
};
};
port@1 {
reg = <1>;
du_out_rgb1: endpoint {
};
};
};
};
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7745",
"renesas,rcar-gen2-msiof";
@ -805,7 +921,8 @@
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7745";
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
@ -819,7 +936,8 @@
};
sdhi1: sd@ee140000 {
compatible = "renesas,sdhi-r8a7745";
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
@ -833,7 +951,8 @@
};
sdhi2: sd@ee160000 {
compatible = "renesas,sdhi-r8a7745";
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
@ -916,6 +1035,23 @@
};
};
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7745",
"renesas,rcar-gen2-usbhs";
reg = <0 0xe6590000 0 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 704>;
renesas,buswait = <4>;
phys = <&usb0 1>;
phy-names = "usb";
status = "disabled";
};
usbphy: usb-phy@e6590100 {
compatible = "renesas,usb-phy-r8a7745",
"renesas,rcar-gen2-usb-phy";
@ -937,6 +1073,34 @@
#phy-cells = <1>;
};
};
can0: can@e6e80000 {
compatible = "renesas,can-r8a7745",
"renesas,rcar-gen2-can";
reg = <0 0xe6e80000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A7745_CLK_RCAN>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
can1: can@e6e88000 {
compatible = "renesas,can-r8a7745",
"renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A7745_CLK_RCAN>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
};
/* External root clock */
@ -954,6 +1118,14 @@
clock-frequency = <48000000>;
};
/* External CAN clock */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";

12
arch/arm/boot/dts/r8a7778.dtsi
View File

@ -51,7 +51,8 @@
};
ether: ethernet@fde00000 {
compatible = "renesas,ether-r8a7778";
compatible = "renesas,ether-r8a7778",
"renesas,rcar-gen1-ether";
reg = <0xfde00000 0x400>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
@ -379,7 +380,8 @@
};
sdhi0: sd@ffe4c000 {
compatible = "renesas,sdhi-r8a7778";
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4c000 0x100>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
@ -388,7 +390,8 @@
};
sdhi1: sd@ffe4d000 {
compatible = "renesas,sdhi-r8a7778";
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4d000 0x100>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
@ -397,7 +400,8 @@
};
sdhi2: sd@ffe4f000 {
compatible = "renesas,sdhi-r8a7778";
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4f000 0x100>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;

12
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -355,7 +355,8 @@
};
sdhi0: sd@ffe4c000 {
compatible = "renesas,sdhi-r8a7779";
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4c000 0x100>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
@ -364,7 +365,8 @@
};
sdhi1: sd@ffe4d000 {
compatible = "renesas,sdhi-r8a7779";
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4d000 0x100>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
@ -373,7 +375,8 @@
};
sdhi2: sd@ffe4e000 {
compatible = "renesas,sdhi-r8a7779";
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4e000 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
@ -382,7 +385,8 @@
};
sdhi3: sd@ffe4f000 {
compatible = "renesas,sdhi-r8a7779";
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4f000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;

5
arch/arm/boot/dts/r8a7790-lager.dts
View File

@ -272,9 +272,8 @@
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
&gpio1 16 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};

23
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -311,7 +311,7 @@
};
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
@ -320,13 +320,11 @@
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 124>;
renesas,channels-mask = <0x60>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
@ -341,8 +339,6 @@
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 329>;
renesas,channels-mask = <0xff>;
status = "disabled";
};
@ -662,7 +658,8 @@
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7790";
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
@ -676,7 +673,8 @@
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a7790";
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee120000 0 0x328>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
@ -690,7 +688,8 @@
};
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a7790";
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
@ -704,7 +703,8 @@
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a7790";
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
@ -906,7 +906,8 @@
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7790";
compatible = "renesas,ether-r8a7790",
"renesas,rcar-gen2-ether";
reg = <0 0xee700000 0 0x400>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;

19
arch/arm/boot/dts/r8a7791-koelsch.dts
View File

@ -278,6 +278,12 @@
};
};
cec_clock: cec-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
@ -306,9 +312,8 @@
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */
&gpio7 15 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
@ -640,12 +645,6 @@
};
};
cec_clock: cec-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
@ -708,7 +707,7 @@
};
eeprom@50 {
compatible = "renesas,24c02", "atmel,24c02";
compatible = "renesas,r1ex24002", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};

20
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -257,7 +257,7 @@
};
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
compatible = "renesas,r8a7791-cmt0", "renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
@ -266,13 +266,11 @@
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 124>;
renesas,channels-mask = <0x60>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
compatible = "renesas,r8a7791-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
@ -287,8 +285,6 @@
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 329>;
renesas,channels-mask = <0xff>;
status = "disabled";
};
@ -612,7 +608,8 @@
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7791";
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
@ -626,7 +623,8 @@
};
sdhi1: sd@ee140000 {
compatible = "renesas,sdhi-r8a7791";
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
@ -640,7 +638,8 @@
};
sdhi2: sd@ee160000 {
compatible = "renesas,sdhi-r8a7791";
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
@ -961,7 +960,8 @@
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7791";
compatible = "renesas,ether-r8a7791",
"renesas,rcar-gen2-ether";
reg = <0 0xee700000 0 0x400>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;

3
arch/arm/boot/dts/r8a7792.dtsi
View File

@ -507,7 +507,8 @@
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7792";
compatible = "renesas,sdhi-r8a7792",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,

20
arch/arm/boot/dts/r8a7793.dtsi
View File

@ -248,7 +248,7 @@
};
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
compatible = "renesas,r8a7793-cmt0", "renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
@ -257,13 +257,11 @@
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 124>;
renesas,channels-mask = <0x60>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
compatible = "renesas,r8a7793-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
@ -278,8 +276,6 @@
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 329>;
renesas,channels-mask = <0xff>;
status = "disabled";
};
@ -562,7 +558,8 @@
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7793";
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
@ -576,7 +573,8 @@
};
sdhi1: sd@ee140000 {
compatible = "renesas,sdhi-r8a7793";
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
@ -590,7 +588,8 @@
};
sdhi2: sd@ee160000 {
compatible = "renesas,sdhi-r8a7793";
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
@ -916,7 +915,8 @@
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7793";
compatible = "renesas,ether-r8a7793",
"renesas,rcar-gen2-ether";
reg = <0 0xee700000 0 0x400>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;

5
arch/arm/boot/dts/r8a7794-alt.dts
View File

@ -143,9 +143,8 @@
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
&gpio4 8 GPIO_ACTIVE_HIGH /* scl */
>;
sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};

27
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -37,6 +37,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -66,6 +67,12 @@
};
};
apmu@e6151000 {
compatible = "renesas,r8a7794-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -181,7 +188,7 @@
};
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-gen2";
compatible = "renesas,r8a7794-cmt0", "renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
@ -190,13 +197,11 @@
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 124>;
renesas,channels-mask = <0x60>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,cmt-48-gen2";
compatible = "renesas,r8a7794-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
@ -211,8 +216,6 @@
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 329>;
renesas,channels-mask = <0xff>;
status = "disabled";
};
@ -640,7 +643,8 @@
};
ether: ethernet@ee700000 {
compatible = "renesas,ether-r8a7794";
compatible = "renesas,ether-r8a7794",
"renesas,rcar-gen2-ether";
reg = <0 0xee700000 0 0x400>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;
@ -791,7 +795,8 @@
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7794";
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
@ -805,7 +810,8 @@
};
sdhi1: sd@ee140000 {
compatible = "renesas,sdhi-r8a7794";
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
@ -819,7 +825,8 @@
};
sdhi2: sd@ee160000 {
compatible = "renesas,sdhi-r8a7794";
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;

3
arch/arm/boot/dts/sh73a0.dtsi
View File

@ -100,9 +100,6 @@
clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
clock-names = "fck";
power-domains = <&pd_c5>;
renesas,channels-mask = <0x3f>;
status = "disabled";
};