ARM: kirkwood: use fixed PCI i/o mapping
Move kirkwood PCI to fixed i/o mapping and remove io.h. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Lennert Buytenhek <kernel@wantstofly.org> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: Jason Cooper <jason@lakedaemon.net> Tested-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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@ -547,7 +547,6 @@ config ARCH_KIRKWOOD
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select PCI
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select NEED_MACH_IO_H
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select PLAT_ORION
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help
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Support for the following Marvell Kirkwood series SoCs:
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@ -41,16 +41,6 @@
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****************************************************************************/
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static struct map_desc kirkwood_io_desc[] __initdata = {
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{
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.virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
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.length = KIRKWOOD_PCIE_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
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.length = KIRKWOOD_PCIE1_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = KIRKWOOD_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
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.length = KIRKWOOD_REGS_SIZE,
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@ -1,24 +0,0 @@
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/*
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* arch/arm/mach-kirkwood/include/mach/io.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IO_H
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#define __ASM_ARCH_IO_H
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#include "kirkwood.h"
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#define IO_SPACE_LIMIT 0xffffffff
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static inline void __iomem *__io(unsigned long addr)
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{
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return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE)
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+ KIRKWOOD_PCIE_IO_VIRT_BASE);
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}
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#define __io(a) __io(a)
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#endif
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@ -37,14 +37,12 @@
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#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
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#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
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#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
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#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000
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#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
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#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000
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#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K
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#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
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#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000
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#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
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#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
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#define KIRKWOOD_PCIE_IO_SIZE SZ_64K
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#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
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#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
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@ -56,7 +56,7 @@ struct pcie_port {
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void __iomem *base;
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spinlock_t conf_lock;
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int irq;
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struct resource res[2];
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struct resource res;
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};
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static int pcie_port_map[2];
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@ -136,21 +136,13 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
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pp->base = (void __iomem *)PCIE_VIRT_BASE;
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pp->irq = IRQ_KIRKWOOD_PCIE;
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/*
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* IORESOURCE_IO
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*/
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pp->res[0].name = "PCIe 0 I/O Space";
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pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
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pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
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pp->res[0].flags = IORESOURCE_IO;
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/*
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* IORESOURCE_MEM
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*/
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pp->res[1].name = "PCIe 0 MEM";
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pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
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pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
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pp->res[1].flags = IORESOURCE_MEM;
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pp->res.name = "PCIe 0 MEM";
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pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
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pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
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pp->res.flags = IORESOURCE_MEM;
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}
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static void __init pcie1_ioresources_init(struct pcie_port *pp)
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@ -158,21 +150,13 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
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pp->base = (void __iomem *)PCIE1_VIRT_BASE;
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pp->irq = IRQ_KIRKWOOD_PCIE1;
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/*
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* IORESOURCE_IO
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*/
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pp->res[0].name = "PCIe 1 I/O Space";
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pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
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pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
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pp->res[0].flags = IORESOURCE_IO;
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/*
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* IORESOURCE_MEM
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*/
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pp->res[1].name = "PCIe 1 MEM";
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pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
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pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
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pp->res[1].flags = IORESOURCE_MEM;
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pp->res.name = "PCIe 1 MEM";
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pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
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pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
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pp->res.flags = IORESOURCE_MEM;
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}
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static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
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@ -197,23 +181,21 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
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case 0:
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kirkwood_enable_pcie_clk("0");
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pcie0_ioresources_init(pp);
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pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
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break;
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case 1:
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kirkwood_enable_pcie_clk("1");
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pcie1_ioresources_init(pp);
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pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE);
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break;
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default:
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panic("PCIe setup: invalid controller %d", index);
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}
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if (request_resource(&ioport_resource, &pp->res[0]))
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panic("Request PCIe%d IO resource failed\n", index);
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if (request_resource(&iomem_resource, &pp->res[1]))
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if (request_resource(&iomem_resource, &pp->res))
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panic("Request PCIe%d Memory resource failed\n", index);
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sys->io_offset = 0;
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pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
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pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
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pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
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/*
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* Generic PCIe unit setup.
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