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Blackfin: BF54x: tweak DMAC MMR naming to match other ports 

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2010-07-29 02:04:42 +00:00
parent ba3f5973ce
commit 2b73a19f2d
2 changed files with 12 additions and 12 deletions
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16
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
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@ -301,10 +301,10 @@
/* DMAC0 Registers */
#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
/* DMA Channel 0 Registers */
@ -1155,10 +1155,10 @@
/* DMAC1 Registers */
#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
/* DMA Channel 12 Registers */

8
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
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@ -198,8 +198,8 @@
/* DMAC0 Registers */
#define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
#define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
/* DMA Channel 0 Registers */
@ -688,8 +688,8 @@
/* DMAC1 Registers */
#define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
#define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
/* DMA Channel 12 Registers */