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Documentation: fpga: dfl: add link address of feature id table 

This patch adds the link address of feature id table in documentation.

Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
Acked-by: Wu Hao <hao.wu@intel.com>
Link: https://lore.kernel.org/r/20220419032942.427429-3-tianfei.zhang@intel.com
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
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Tianfei zhang 2022-04-18 23:29:42 -04:00 committed by Xu Yilun
parent 88b3f3ff38
commit 2b28c9e0fe
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Documentation/fpga/dfl.rst
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@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id.
FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
could be a reference.
Please refer to below link to existing feature id table and guide for new feature
ids application.
https://github.com/OPAE/dfl-feature-id
Location of DFLs on a PCI Device
================================
The original method for finding a DFL on a PCI device assumed the start of the