First rc pull request
A set of small driver and core code fixes: - Small series fixing longtime user triggerable bugs in the ODP processing inside mlx5 and core code - Various small driver malfunctions and crashes (use after, free, error unwind, implementation bugs) - A misfunction of the RDMA GID cache that can be triggered by the administrator -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEfB7FMLh+8QxL+6i3OG33FX4gmxoFAlwAbPgACgkQOG33FX4g mxpMCg/8DMvxyz5byYhLbreKuMCeG8+L5PuvR8myeeA5ycbPUo+HYCFe7fkqpHUH tlgLWm0PoMnGh1s8pjD2OvFU2xHAl9tydk1tU8XLBpEjC3XvrD5ZTvd/i2rHdvDy hKDGRouU6QnDiNwTR5HrSlqH5OVVZ0K0Oyl3YjAbGItL4xJEEPbiRCWA+SN8tuBl mkFEkGr+MKZIDEieatf9KT2cLQbhVbtjG58rTxA1jOVL1ZM+PT0FZ/J7JsQAD2FO MVkw2NQrgu/bLiqr2d679rShWRetctap9iYiGna2ftVghCHqXajN477Dv0w01pQu 5k9JaSPA2j7rGaFql4fyyuHBMqHF+pqwC/p1ExgUpbOTShcibUCIfJbIHhjLVTCl sszZculTfCiYnJBiBkSp1G1L784Z6QPnDRacxeHRuV2yUd5MhrW2KCTwk0ZkPV9F PKwKCNC90TeD3STUAk0GXouzuZYvqjxDdwiE5ohYgCCR5CNRBS/fdmmRK/PnRb1Y ekTYHStoBFT1tkAG5NqAcfKm3qs/tdxlcdo+3sS9n5XWNwyUwUP2buKKnaXu9ACf yD3+vDaBCEcGhQXaw6lUm8sTF2P5eD67lMvJiteLJr9dsnk7bUd6+d1sXB3TjJss bX5FQx2CwNMnRQ7hKrBqZa3dhCA578Hq0AgmH+1jw/7mD5Ay6Hw= =QrHg -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma Pull rdma fixes from Jason Gunthorpe: "This is a bit later than usual for our first -rc but I'm not seeing anything worry-some in the RDMA tree right now. Quiet so far this -rc cycle, only a few internal driver related bugs and a small series fixing ODP bugs found by more advanced testing. A set of small driver and core code fixes: - Small series fixing longtime user triggerable bugs in the ODP processing inside mlx5 and core code - Various small driver malfunctions and crashes (use after, free, error unwind, implementation bugs) - A misfunction of the RDMA GID cache that can be triggered by the administrator" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: RDMA/mlx5: Initialize return variable in case pagefault was skipped IB/mlx5: Fix page fault handling for MW IB/umem: Set correct address to the invalidation function IB/mlx5: Skip non-ODP MR when handling a page fault RDMA/hns: Bugfix pbl configuration for rereg mr iser: set sector for ambiguous mr status errors RDMA/rdmavt: Fix rvt_create_ah function signature IB/mlx5: Avoid load failure due to unknown link width IB/mlx5: Fix XRC QP support after introducing extended atomic RDMA/bnxt_re: Avoid accessing the device structure after it is freed RDMA/bnxt_re: Fix system hang when registration with L2 driver fails RDMA/core: Add GIDs while changing MAC addr only for registered ndev RDMA/mlx5: Fix fence type for IB_WR_LOCAL_INV WR net/mlx5: Fix XRC SRQ umem valid bits
This commit is contained in:
commit
2b17992f6f
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@ -767,8 +767,10 @@ static int netdevice_event(struct notifier_block *this, unsigned long event,
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case NETDEV_CHANGEADDR:
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cmds[0] = netdev_del_cmd;
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if (ndev->reg_state == NETREG_REGISTERED) {
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cmds[1] = add_default_gid_cmd;
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cmds[2] = add_cmd;
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}
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break;
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case NETDEV_CHANGEUPPER:
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@ -137,15 +137,6 @@ static void ib_umem_notifier_release(struct mmu_notifier *mn,
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up_read(&per_mm->umem_rwsem);
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}
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static int invalidate_page_trampoline(struct ib_umem_odp *item, u64 start,
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u64 end, void *cookie)
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{
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ib_umem_notifier_start_account(item);
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item->umem.context->invalidate_range(item, start, start + PAGE_SIZE);
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ib_umem_notifier_end_account(item);
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return 0;
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}
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static int invalidate_range_start_trampoline(struct ib_umem_odp *item,
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u64 start, u64 end, void *cookie)
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{
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@ -553,12 +544,13 @@ out:
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put_page(page);
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if (remove_existing_mapping && umem->context->invalidate_range) {
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invalidate_page_trampoline(
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ib_umem_notifier_start_account(umem_odp);
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umem->context->invalidate_range(
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umem_odp,
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ib_umem_start(umem) + (page_index >> umem->page_shift),
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ib_umem_start(umem) + ((page_index + 1) >>
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umem->page_shift),
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NULL);
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ib_umem_start(umem) + (page_index << umem->page_shift),
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ib_umem_start(umem) +
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((page_index + 1) << umem->page_shift));
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ib_umem_notifier_end_account(umem_odp);
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ret = -EAGAIN;
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}
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@ -1268,6 +1268,7 @@ static int bnxt_re_ib_reg(struct bnxt_re_dev *rdev)
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/* Registered a new RoCE device instance to netdev */
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rc = bnxt_re_register_netdev(rdev);
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if (rc) {
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rtnl_unlock();
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pr_err("Failed to register with netedev: %#x\n", rc);
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return -EINVAL;
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}
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@ -1466,6 +1467,7 @@ static void bnxt_re_task(struct work_struct *work)
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"Failed to register with IB: %#x", rc);
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bnxt_re_remove_one(rdev);
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bnxt_re_dev_unreg(rdev);
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goto exit;
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}
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break;
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case NETDEV_UP:
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@ -1489,6 +1491,7 @@ static void bnxt_re_task(struct work_struct *work)
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}
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smp_mb__before_atomic();
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atomic_dec(&rdev->sched_count);
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exit:
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kfree(re_work);
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}
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@ -1756,10 +1756,9 @@ static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
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return hns_roce_cmq_send(hr_dev, &desc, 1);
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}
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static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
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unsigned long mtpt_idx)
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static int set_mtpt_pbl(struct hns_roce_v2_mpt_entry *mpt_entry,
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struct hns_roce_mr *mr)
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{
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struct hns_roce_v2_mpt_entry *mpt_entry;
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struct scatterlist *sg;
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u64 page_addr;
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u64 *pages;
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@ -1767,6 +1766,53 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
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int len;
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int entry;
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mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
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mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
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roce_set_field(mpt_entry->byte_48_mode_ba,
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V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S,
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upper_32_bits(mr->pbl_ba >> 3));
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pages = (u64 *)__get_free_page(GFP_KERNEL);
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if (!pages)
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return -ENOMEM;
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i = 0;
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for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
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len = sg_dma_len(sg) >> PAGE_SHIFT;
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for (j = 0; j < len; ++j) {
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page_addr = sg_dma_address(sg) +
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(j << mr->umem->page_shift);
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pages[i] = page_addr >> 6;
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/* Record the first 2 entry directly to MTPT table */
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if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
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goto found;
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i++;
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}
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}
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found:
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mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
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roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
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V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0]));
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mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
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roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
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V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
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roce_set_field(mpt_entry->byte_64_buf_pa1,
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V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
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V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
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mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
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free_page((unsigned long)pages);
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return 0;
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}
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static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
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unsigned long mtpt_idx)
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{
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struct hns_roce_v2_mpt_entry *mpt_entry;
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int ret;
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mpt_entry = mb_buf;
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memset(mpt_entry, 0, sizeof(*mpt_entry));
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@ -1781,7 +1827,6 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
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mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
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roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
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V2_MPT_BYTE_4_PD_S, mr->pd);
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mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st);
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roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
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roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
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@ -1796,13 +1841,11 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
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(mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
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roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
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(mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
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mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en);
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roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
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mr->type == MR_TYPE_MR ? 0 : 1);
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roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
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1);
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mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa);
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mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
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mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
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@ -1813,53 +1856,9 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
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if (mr->type == MR_TYPE_DMA)
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return 0;
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mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
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ret = set_mtpt_pbl(mpt_entry, mr);
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mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
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roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
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V2_MPT_BYTE_48_PBL_BA_H_S,
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upper_32_bits(mr->pbl_ba >> 3));
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mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba);
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pages = (u64 *)__get_free_page(GFP_KERNEL);
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if (!pages)
|
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return -ENOMEM;
|
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|
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i = 0;
|
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for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
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len = sg_dma_len(sg) >> PAGE_SHIFT;
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for (j = 0; j < len; ++j) {
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page_addr = sg_dma_address(sg) +
|
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(j << mr->umem->page_shift);
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pages[i] = page_addr >> 6;
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|
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/* Record the first 2 entry directly to MTPT table */
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if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
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goto found;
|
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i++;
|
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}
|
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}
|
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|
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found:
|
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mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
|
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roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
|
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V2_MPT_BYTE_56_PA0_H_S,
|
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upper_32_bits(pages[0]));
|
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mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h);
|
||||
|
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mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
|
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roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
|
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V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
|
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|
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free_page((unsigned long)pages);
|
||||
|
||||
roce_set_field(mpt_entry->byte_64_buf_pa1,
|
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V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
|
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V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
|
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mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
|
||||
mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
|
||||
|
@ -1868,6 +1867,7 @@ static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
|
|||
u64 size, void *mb_buf)
|
||||
{
|
||||
struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
|
||||
int ret = 0;
|
||||
|
||||
if (flags & IB_MR_REREG_PD) {
|
||||
roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
|
||||
|
@ -1881,13 +1881,13 @@ static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
|
|||
(mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
|
||||
roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
|
||||
V2_MPT_BYTE_8_ATOMIC_EN_S,
|
||||
(mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0));
|
||||
mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
|
||||
roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
|
||||
(mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0));
|
||||
mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
|
||||
roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
|
||||
(mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
|
||||
mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
|
||||
roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
|
||||
(mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
|
||||
mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
|
||||
}
|
||||
|
||||
if (flags & IB_MR_REREG_TRANS) {
|
||||
|
@ -1896,21 +1896,13 @@ static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
|
|||
mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
|
||||
mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
|
||||
|
||||
mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
|
||||
mpt_entry->pbl_ba_l =
|
||||
cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
|
||||
roce_set_field(mpt_entry->byte_48_mode_ba,
|
||||
V2_MPT_BYTE_48_PBL_BA_H_M,
|
||||
V2_MPT_BYTE_48_PBL_BA_H_S,
|
||||
upper_32_bits(mr->pbl_ba >> 3));
|
||||
mpt_entry->byte_48_mode_ba =
|
||||
cpu_to_le32(mpt_entry->byte_48_mode_ba);
|
||||
|
||||
mr->iova = iova;
|
||||
mr->size = size;
|
||||
|
||||
ret = set_mtpt_pbl(mpt_entry, mr);
|
||||
}
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
|
||||
|
|
|
@ -1094,31 +1094,26 @@ enum mlx5_ib_width {
|
|||
MLX5_IB_WIDTH_12X = 1 << 4
|
||||
};
|
||||
|
||||
static int translate_active_width(struct ib_device *ibdev, u8 active_width,
|
||||
static void translate_active_width(struct ib_device *ibdev, u8 active_width,
|
||||
u8 *ib_width)
|
||||
{
|
||||
struct mlx5_ib_dev *dev = to_mdev(ibdev);
|
||||
int err = 0;
|
||||
|
||||
if (active_width & MLX5_IB_WIDTH_1X) {
|
||||
if (active_width & MLX5_IB_WIDTH_1X)
|
||||
*ib_width = IB_WIDTH_1X;
|
||||
} else if (active_width & MLX5_IB_WIDTH_2X) {
|
||||
mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
|
||||
(int)active_width);
|
||||
err = -EINVAL;
|
||||
} else if (active_width & MLX5_IB_WIDTH_4X) {
|
||||
else if (active_width & MLX5_IB_WIDTH_4X)
|
||||
*ib_width = IB_WIDTH_4X;
|
||||
} else if (active_width & MLX5_IB_WIDTH_8X) {
|
||||
else if (active_width & MLX5_IB_WIDTH_8X)
|
||||
*ib_width = IB_WIDTH_8X;
|
||||
} else if (active_width & MLX5_IB_WIDTH_12X) {
|
||||
else if (active_width & MLX5_IB_WIDTH_12X)
|
||||
*ib_width = IB_WIDTH_12X;
|
||||
} else {
|
||||
mlx5_ib_dbg(dev, "Invalid active_width %d\n",
|
||||
else {
|
||||
mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
|
||||
(int)active_width);
|
||||
err = -EINVAL;
|
||||
*ib_width = IB_WIDTH_4X;
|
||||
}
|
||||
|
||||
return err;
|
||||
return;
|
||||
}
|
||||
|
||||
static int mlx5_mtu_to_ib_mtu(int mtu)
|
||||
|
@ -1225,10 +1220,8 @@ static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
|
|||
if (err)
|
||||
goto out;
|
||||
|
||||
err = translate_active_width(ibdev, ib_link_width_oper,
|
||||
&props->active_width);
|
||||
if (err)
|
||||
goto out;
|
||||
translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
|
||||
|
||||
err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
|
||||
if (err)
|
||||
goto out;
|
||||
|
|
|
@ -674,6 +674,15 @@ next_mr:
|
|||
goto srcu_unlock;
|
||||
}
|
||||
|
||||
if (!mr->umem->is_odp) {
|
||||
mlx5_ib_dbg(dev, "skipping non ODP MR (lkey=0x%06x) in page fault handler.\n",
|
||||
key);
|
||||
if (bytes_mapped)
|
||||
*bytes_mapped += bcnt;
|
||||
ret = 0;
|
||||
goto srcu_unlock;
|
||||
}
|
||||
|
||||
ret = pagefault_mr(dev, mr, io_virt, bcnt, bytes_mapped);
|
||||
if (ret < 0)
|
||||
goto srcu_unlock;
|
||||
|
@ -735,6 +744,7 @@ next_mr:
|
|||
head = frame;
|
||||
|
||||
bcnt -= frame->bcnt;
|
||||
offset = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
|
@ -2633,8 +2633,7 @@ static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
|
|||
|
||||
if (access_flags & IB_ACCESS_REMOTE_READ)
|
||||
*hw_access_flags |= MLX5_QP_BIT_RRE;
|
||||
if ((access_flags & IB_ACCESS_REMOTE_ATOMIC) &&
|
||||
qp->ibqp.qp_type == IB_QPT_RC) {
|
||||
if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
|
||||
int atomic_mode;
|
||||
|
||||
atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
|
||||
|
@ -4678,11 +4677,11 @@ static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
|
|||
goto out;
|
||||
}
|
||||
|
||||
if (wr->opcode == IB_WR_LOCAL_INV ||
|
||||
wr->opcode == IB_WR_REG_MR) {
|
||||
if (wr->opcode == IB_WR_REG_MR) {
|
||||
fence = dev->umr_fence;
|
||||
next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
|
||||
} else if (wr->send_flags & IB_SEND_FENCE) {
|
||||
} else {
|
||||
if (wr->send_flags & IB_SEND_FENCE) {
|
||||
if (qp->next_fence)
|
||||
fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
|
||||
else
|
||||
|
@ -4690,6 +4689,7 @@ static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
|
|||
} else {
|
||||
fence = qp->next_fence;
|
||||
}
|
||||
}
|
||||
|
||||
switch (ibqp->qp_type) {
|
||||
case IB_QPT_XRC_INI:
|
||||
|
|
|
@ -91,13 +91,15 @@ EXPORT_SYMBOL(rvt_check_ah);
|
|||
* rvt_create_ah - create an address handle
|
||||
* @pd: the protection domain
|
||||
* @ah_attr: the attributes of the AH
|
||||
* @udata: pointer to user's input output buffer information.
|
||||
*
|
||||
* This may be called from interrupt context.
|
||||
*
|
||||
* Return: newly allocated ah
|
||||
*/
|
||||
struct ib_ah *rvt_create_ah(struct ib_pd *pd,
|
||||
struct rdma_ah_attr *ah_attr)
|
||||
struct rdma_ah_attr *ah_attr,
|
||||
struct ib_udata *udata)
|
||||
{
|
||||
struct rvt_ah *ah;
|
||||
struct rvt_dev_info *dev = ib_to_rvt(pd->device);
|
||||
|
|
|
@ -51,7 +51,8 @@
|
|||
#include <rdma/rdma_vt.h>
|
||||
|
||||
struct ib_ah *rvt_create_ah(struct ib_pd *pd,
|
||||
struct rdma_ah_attr *ah_attr);
|
||||
struct rdma_ah_attr *ah_attr,
|
||||
struct ib_udata *udata);
|
||||
int rvt_destroy_ah(struct ib_ah *ibah);
|
||||
int rvt_modify_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
|
||||
int rvt_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
|
||||
|
|
|
@ -1124,7 +1124,9 @@ u8 iser_check_task_pi_status(struct iscsi_iser_task *iser_task,
|
|||
IB_MR_CHECK_SIG_STATUS, &mr_status);
|
||||
if (ret) {
|
||||
pr_err("ib_check_mr_status failed, ret %d\n", ret);
|
||||
goto err;
|
||||
/* Not a lot we can do, return ambiguous guard error */
|
||||
*sector = 0;
|
||||
return 0x1;
|
||||
}
|
||||
|
||||
if (mr_status.fail_status & IB_MR_CHECK_SIG_STATUS) {
|
||||
|
@ -1152,9 +1154,6 @@ u8 iser_check_task_pi_status(struct iscsi_iser_task *iser_task,
|
|||
}
|
||||
|
||||
return 0;
|
||||
err:
|
||||
/* Not alot we can do here, return ambiguous guard error */
|
||||
return 0x1;
|
||||
}
|
||||
|
||||
void iser_err_comp(struct ib_wc *wc, const char *type)
|
||||
|
|
|
@ -2473,14 +2473,15 @@ struct mlx5_ifc_xrc_srqc_bits {
|
|||
|
||||
u8 wq_signature[0x1];
|
||||
u8 cont_srq[0x1];
|
||||
u8 dbr_umem_valid[0x1];
|
||||
u8 reserved_at_22[0x1];
|
||||
u8 rlky[0x1];
|
||||
u8 basic_cyclic_rcv_wqe[0x1];
|
||||
u8 log_rq_stride[0x3];
|
||||
u8 xrcd[0x18];
|
||||
|
||||
u8 page_offset[0x6];
|
||||
u8 reserved_at_46[0x2];
|
||||
u8 reserved_at_46[0x1];
|
||||
u8 dbr_umem_valid[0x1];
|
||||
u8 cqn[0x18];
|
||||
|
||||
u8 reserved_at_60[0x20];
|
||||
|
@ -6689,9 +6690,12 @@ struct mlx5_ifc_create_xrc_srq_in_bits {
|
|||
|
||||
struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
|
||||
|
||||
u8 reserved_at_280[0x40];
|
||||
u8 reserved_at_280[0x60];
|
||||
|
||||
u8 xrc_srq_umem_valid[0x1];
|
||||
u8 reserved_at_2c1[0x5bf];
|
||||
u8 reserved_at_2e1[0x1f];
|
||||
|
||||
u8 reserved_at_300[0x580];
|
||||
|
||||
u8 pas[0][0x40];
|
||||
};
|
||||
|
|
Loading…
Reference in New Issue