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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (62 commits)
  Blackfin: fix sparseirq/kstat_irqs fallout
  Blackfin: fix unused warnings after nommu update
  Blackfin: export the last exception cause via debugfs
  Blackfin: fix length checking in kgdb_ebin2mem
  Blackfin: kgdb: fix up error return values
  Blackfin: push access_ok() L1 attribute down
  Blackfin: punt duplicated search_exception_table() prototype
  Blackfin: add missing access_ok() checks to user functions
  Blackfin: convert early_printk EVT init to a loop
  Blackfin: document the lsl variants of the L1 allocator
  Blackfin: rename Blackfin relocs according to the toolchain
  Blackfin: check SIC defines rather than variant names
  Blackfin: add SSYNC to set_dma_sg() for descriptor fetching
  Blackfin: convert SMP to only use generic time framework
  Blackfin: bf548-ezkit/bf537-stamp: add resources for ADXL345/346
  Blackfin: override default uClinux MTD addr/size
  Blackfin: fix command line corruption with DEBUG_DOUBLEFAULT
  Blackfin: fix handling of initial L1 reservation
  Blackfin: merge sram init functions
  Blackfin: drop unused reserve_pda() function
  ...
This commit is contained in:
Linus Torvalds 2009-06-12 13:14:30 -07:00
parent 47ea421af7 bf664c0a3a
commit 2b10dc45d1
104 changed files with 3020 additions and 1969 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

84
arch/blackfin/Kconfig
View File

@ -223,6 +223,7 @@ endchoice
config SMP
depends on BF561
select GENERIC_TIME
bool "Symmetric multi-processing support"
---help---
This enables support for systems with more than one CPU,
@ -241,12 +242,6 @@ config IRQ_PER_CPU
depends on SMP
default y
config TICK_SOURCE_SYSTMR0
bool
select BFIN_GPTIMERS
depends on SMP
default y
config BF_REV_MIN
int
default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
@ -263,8 +258,8 @@ config BF_REV_MAX
choice
prompt "Silicon Rev"
default BF_REV_0_1 if (BF51x || BF52x || (BF54x && !BF54xM))
default BF_REV_0_2 if (BF534 || BF536 || BF537)
default BF_REV_0_0 if (BF51x || BF52x)
default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
config BF_REV_0_0
@ -607,7 +602,6 @@ source kernel/Kconfig.hz
config GENERIC_TIME
bool "Generic time"
depends on !SMP
default y
config GENERIC_CLOCKEVENTS
@ -615,12 +609,26 @@ config GENERIC_CLOCKEVENTS
depends on GENERIC_TIME
default y
choice
prompt "Kernel Tick Source"
depends on GENERIC_CLOCKEVENTS
default TICKSOURCE_CORETMR
config TICKSOURCE_GPTMR0
bool "Gptimer0 (SCLK domain)"
select BFIN_GPTIMERS
depends on !IPIPE
config TICKSOURCE_CORETMR
bool "Core timer (CCLK domain)"
endchoice
config CYCLES_CLOCKSOURCE
bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
depends on EXPERIMENTAL
bool "Use 'CYCLES' as a clocksource"
depends on GENERIC_CLOCKEVENTS
depends on !BFIN_SCRATCH_REG_CYCLES
default n
depends on !SMP
help
If you say Y here, you will enable support for using the 'cycles'
registers as a clock source. Doing so means you will be unable to
@ -628,6 +636,11 @@ config CYCLES_CLOCKSOURCE
still be able to read it (such as for performance monitoring), but
writing the registers will most likely crash the kernel.
config GPTMR0_CLOCKSOURCE
bool "Use GPTimer0 as a clocksource (higher rating)"
depends on GENERIC_CLOCKEVENTS
depends on !TICKSOURCE_GPTMR0
source kernel/time/Kconfig
comment "Misc"
@ -808,7 +821,7 @@ config APP_STACK_L1
config EXCEPTION_L1_SCRATCH
bool "Locate exception stack in L1 Scratch Memory"
default n
depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
depends on !APP_STACK_L1
help
Whenever an exception occurs, use the L1 Scratch memory for
stack storage. You cannot place the stacks of FLAT binaries
@ -901,7 +914,7 @@ config BFIN_ICACHE_LOCK
bool "Enable Instruction Cache Locking"
choice
prompt "Policy"
prompt "External memory cache policy"
depends on BFIN_DCACHE
default BFIN_WB if !SMP
default BFIN_WT if SMP
@ -942,12 +955,22 @@ config BFIN_WT
endchoice
config BFIN_L2_CACHEABLE
bool "Cache L2 SRAM"
depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
default n
help
Select to make L2 SRAM cacheable in L1 data and instruction cache.
choice
prompt "L2 SRAM cache policy"
depends on (BF54x || BF561)
default BFIN_L2_WT
config BFIN_L2_WB
bool "Write back"
depends on !SMP
config BFIN_L2_WT
bool "Write through"
depends on !SMP
config BFIN_L2_NOT_CACHED
bool "Not cached"
endchoice
config MPU
bool "Enable the memory protection unit (EXPERIMENTAL)"
@ -1011,21 +1034,34 @@ endmenu
menu "EBIU_AMBCTL Control"
config BANK_0
hex "Bank 0"
hex "Bank 0 (AMBCTL0.L)"
default 0x7BB0
help
These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
used to control the Asynchronous Memory Bank 0 settings.
config BANK_1
hex "Bank 1"
hex "Bank 1 (AMBCTL0.H)"
default 0x7BB0
default 0x5558 if BF54x
help
These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
used to control the Asynchronous Memory Bank 1 settings.
config BANK_2
hex "Bank 2"
hex "Bank 2 (AMBCTL1.L)"
default 0x7BB0
help
These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
used to control the Asynchronous Memory Bank 2 settings.
config BANK_3
hex "Bank 3"
hex "Bank 3 (AMBCTL1.H)"
default 0x99B3
help
These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
used to control the Asynchronous Memory Bank 3 settings.
endmenu
config EBIU_MBSCTLVAL

13
arch/blackfin/Kconfig.debug
View File

@ -54,6 +54,19 @@ config DEBUG_HWERR
hardware error interrupts and need to know where they are coming
from.
config EXACT_HWERR
bool "Try to make Hardware errors exact"
depends on DEBUG_HWERR
help
By default, the Blackfin hardware errors are not exact - the error
be reported multiple cycles after the error happens. This delay
can cause the wrong application, or even the kernel to receive a
signal to be killed. If you are getting HW errors in your system,
try turning this on to ensure they are at least comming from the
proper thread.
On production systems, it is safe (and a small optimization) to say N.
config DEBUG_DOUBLEFAULT
bool "Debug Double Faults"
default n

101
arch/blackfin/configs/BF518F-EZBRD_defconfig
View File

@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28.7
# Linux kernel version: 2.6.28.10
# Thu May 21 05:50:01 2009
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
@ -71,7 +72,6 @@ CONFIG_SLAB=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
@ -259,7 +259,10 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@ -404,7 +407,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -688,14 +691,14 @@ CONFIG_INPUT_MISC=y
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
# CONFIG_BF5xx_PPI is not set
# CONFIG_BFIN_SPI_ADC is not set
# CONFIG_BFIN_SPORT is not set
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_TWI_LCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_TWI_LCD is not set
CONFIG_SIMPLE_GPIO=m
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
@ -802,7 +805,30 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
@ -831,6 +857,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_REGULATOR is not set
@ -962,7 +989,8 @@ CONFIG_RTC_DRV_BFIN=y
#
# File systems
#
# CONFIG_EXT2_FS is not set
CONFIG_EXT2_FS=m
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
# CONFIG_REISERFS_FS is not set
@ -988,8 +1016,11 @@ CONFIG_INOTIFY_USER=y
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=m
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
@ -1012,8 +1043,8 @@ CONFIG_SYSFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_YAFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_YAFFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -1048,9 +1079,9 @@ CONFIG_SMB_FS=m
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_NLS=y
CONFIG_NLS=m
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_437=m
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
@ -1065,7 +1096,7 @@ CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
CONFIG_NLS_CODEPAGE_936=m
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
@ -1074,7 +1105,7 @@ CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_1=m
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
@ -1087,7 +1118,7 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
CONFIG_NLS_UTF8=m
# CONFIG_DLM is not set
#
@ -1102,7 +1133,7 @@ CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
@ -1111,8 +1142,6 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
@ -1132,7 +1161,6 @@ CONFIG_DEBUG_INFO=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
#
# Tracers
@ -1148,16 +1176,20 @@ CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_MMRS=y
# CONFIG_DEBUG_HWERR is not set
# CONFIG_DEBUG_DOUBLEFAULT is not set
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_DOUBLEFAULT_PRINT=y
# CONFIG_DEBUG_DOUBLEFAULT_RESET is not set
# CONFIG_DEBUG_ICACHE_CHECK is not set
CONFIG_DEBUG_HUNT_FOR_ZERO=y
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1
# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
@ -1269,7 +1301,6 @@ CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

219
arch/blackfin/configs/BF526-EZBRD_defconfig
View File

@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28.7
# Linux kernel version: 2.6.28.10
# Thu May 21 05:50:01 2009
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
@ -71,7 +72,6 @@ CONFIG_SLAB=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
@ -144,8 +144,8 @@ CONFIG_BF526=y
# CONFIG_BF561 is not set
CONFIG_BF_REV_MIN=0
CONFIG_BF_REV_MAX=2
# CONFIG_BF_REV_0_0 is not set
CONFIG_BF_REV_0_1=y
CONFIG_BF_REV_0_0=y
# CONFIG_BF_REV_0_1 is not set
# CONFIG_BF_REV_0_2 is not set
# CONFIG_BF_REV_0_3 is not set
# CONFIG_BF_REV_0_4 is not set
@ -264,7 +264,10 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@ -409,7 +412,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -491,7 +494,7 @@ CONFIG_MTD_PARTITIONS=y
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=m
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
@ -504,9 +507,9 @@ CONFIG_MTD_BLOCK=y
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
CONFIG_MTD_JEDECPROBE=m
CONFIG_MTD_GEN_PROBE=m
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
@ -518,9 +521,10 @@ CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=m
# CONFIG_MTD_ABSENT is not set
@ -529,7 +533,8 @@ CONFIG_MTD_ROM=m
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_PHYSMAP=y
# CONFIG_MTD_PHYSMAP_COMPAT is not set
# CONFIG_MTD_GPIO_ADDR is not set
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
@ -597,9 +602,42 @@ CONFIG_HAVE_IDE=y
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_PROC_FS is not set
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=m
# CONFIG_BLK_DEV_SR_VENDOR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_DH is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
@ -644,9 +682,8 @@ CONFIG_BFIN_MAC_RMII=y
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -715,14 +752,14 @@ CONFIG_INPUT_MISC=y
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
# CONFIG_BF5xx_PPI is not set
# CONFIG_BFIN_SPI_ADC is not set
# CONFIG_BFIN_SPORT is not set
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_TWI_LCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_TWI_LCD is not set
CONFIG_SIMPLE_GPIO=m
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
@ -832,11 +869,35 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_AD5252 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADCXX is not set
@ -920,6 +981,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_REGULATOR is not set
@ -1008,8 +1070,8 @@ CONFIG_USB=y
#
# Miscellaneous USB options
#
# CONFIG_USB_DEVICEFS is not set
CONFIG_USB_DEVICE_CLASS=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
@ -1037,10 +1099,10 @@ CONFIG_USB_MUSB_SOC=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_USB_MUSB_PERIPHERAL is not set
# CONFIG_USB_MUSB_OTG is not set
# CONFIG_USB_GADGET_MUSB_HDRC is not set
CONFIG_USB_MUSB_HDRC_HCD=y
CONFIG_MUSB_PIO_ONLY=y
CONFIG_MUSB_DMA_POLL=y
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_INVENTRA_DMA=y
# CONFIG_USB_TI_CPPI_DMA is not set
# CONFIG_USB_MUSB_DEBUG is not set
#
@ -1058,7 +1120,7 @@ CONFIG_MUSB_DMA_POLL=y
#
# see USB_STORAGE Help for more information
#
CONFIG_USB_STORAGE=m
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
@ -1107,33 +1169,10 @@ CONFIG_USB_STORAGE=m
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_VST is not set
# CONFIG_USB_GADGET is not set
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_PXA25X is not set
# CONFIG_USB_GADGET_PXA27X is not set
# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_FSL_QE is not set
# CONFIG_USB_GADGET_NET2272 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_ZERO is not set
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_CDC_COMPOSITE is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
@ -1206,7 +1245,8 @@ CONFIG_RTC_DRV_BFIN=y
#
# File systems
#
# CONFIG_EXT2_FS is not set
CONFIG_EXT2_FS=m
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
# CONFIG_REISERFS_FS is not set
@ -1226,14 +1266,19 @@ CONFIG_INOTIFY_USER=y
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
# CONFIG_ZISOFS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=m
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
@ -1256,16 +1301,6 @@ CONFIG_SYSFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
@ -1277,6 +1312,16 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -1313,7 +1358,7 @@ CONFIG_SMB_FS=m
CONFIG_MSDOS_PARTITION=y
CONFIG_NLS=m
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
CONFIG_NLS_CODEPAGE_437=m
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
@ -1328,7 +1373,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
CONFIG_NLS_CODEPAGE_936=m
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
@ -1337,7 +1382,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set
CONFIG_NLS_ISO8859_1=m
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
@ -1350,7 +1395,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
CONFIG_NLS_UTF8=m
# CONFIG_DLM is not set
#
@ -1365,7 +1410,7 @@ CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
@ -1374,8 +1419,6 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
@ -1395,7 +1438,6 @@ CONFIG_DEBUG_INFO=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
#
# Tracers
@ -1411,16 +1453,20 @@ CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_MMRS=y
# CONFIG_DEBUG_HWERR is not set
# CONFIG_DEBUG_DOUBLEFAULT is not set
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_DOUBLEFAULT_PRINT=y
# CONFIG_DEBUG_DOUBLEFAULT_RESET is not set
# CONFIG_DEBUG_ICACHE_CHECK is not set
CONFIG_DEBUG_HUNT_FOR_ZERO=y
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1
# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
@ -1534,7 +1580,6 @@ CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

211
arch/blackfin/configs/BF527-EZKIT_defconfig
View File

@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28.7
# Linux kernel version: 2.6.28.10
# Thu May 21 05:50:01 2009
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
@ -71,7 +72,6 @@ CONFIG_SLAB=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
@ -145,8 +145,8 @@ CONFIG_BF527=y
CONFIG_BF_REV_MIN=0
CONFIG_BF_REV_MAX=2
# CONFIG_BF_REV_0_0 is not set
CONFIG_BF_REV_0_1=y
# CONFIG_BF_REV_0_2 is not set
# CONFIG_BF_REV_0_1 is not set
CONFIG_BF_REV_0_2=y
# CONFIG_BF_REV_0_3 is not set
# CONFIG_BF_REV_0_4 is not set
# CONFIG_BF_REV_0_5 is not set
@ -264,7 +264,10 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@ -318,7 +321,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_VIRT_TO_BUS=y
CONFIG_BFIN_GPTIMERS=m
CONFIG_BFIN_GPTIMERS=y
# CONFIG_DMA_UNCACHED_4M is not set
# CONFIG_DMA_UNCACHED_2M is not set
CONFIG_DMA_UNCACHED_1M=y
@ -409,7 +412,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -639,9 +642,42 @@ CONFIG_HAVE_IDE=y
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_PROC_FS is not set
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=m
# CONFIG_BLK_DEV_SR_VENDOR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_DH is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
@ -687,9 +723,8 @@ CONFIG_BFIN_MAC_RMII=y
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -758,14 +793,14 @@ CONFIG_INPUT_MISC=y
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
CONFIG_BF5xx_PPI=m
# CONFIG_BFIN_SPI_ADC is not set
CONFIG_BFIN_SPORT=m
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_TWI_LCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_TWI_LCD is not set
CONFIG_SIMPLE_GPIO=m
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
@ -875,7 +910,30 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
@ -909,6 +967,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_REGULATOR is not set
@ -1091,8 +1150,8 @@ CONFIG_USB=y
#
# Miscellaneous USB options
#
# CONFIG_USB_DEVICEFS is not set
CONFIG_USB_DEVICE_CLASS=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
@ -1120,10 +1179,10 @@ CONFIG_USB_MUSB_SOC=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_USB_MUSB_PERIPHERAL is not set
# CONFIG_USB_MUSB_OTG is not set
# CONFIG_USB_GADGET_MUSB_HDRC is not set
CONFIG_USB_MUSB_HDRC_HCD=y
CONFIG_MUSB_PIO_ONLY=y
CONFIG_MUSB_DMA_POLL=y
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_INVENTRA_DMA=y
# CONFIG_USB_TI_CPPI_DMA is not set
# CONFIG_USB_MUSB_DEBUG is not set
#
@ -1141,7 +1200,7 @@ CONFIG_MUSB_DMA_POLL=y
#
# see USB_STORAGE Help for more information
#
CONFIG_USB_STORAGE=m
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
@ -1190,33 +1249,10 @@ CONFIG_USB_STORAGE=m
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_VST is not set
# CONFIG_USB_GADGET is not set
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_PXA25X is not set
# CONFIG_USB_GADGET_PXA27X is not set
# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_FSL_QE is not set
# CONFIG_USB_GADGET_NET2272 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_ZERO is not set
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_CDC_COMPOSITE is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
@ -1289,7 +1325,8 @@ CONFIG_RTC_DRV_BFIN=y
#
# File systems
#
# CONFIG_EXT2_FS is not set
CONFIG_EXT2_FS=m
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
# CONFIG_REISERFS_FS is not set
@ -1309,14 +1346,20 @@ CONFIG_INOTIFY_USER=y
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
# CONFIG_ZISOFS is not set
CONFIG_UDF_FS=m
CONFIG_UDF_NLS=y
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=m
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
@ -1339,16 +1382,6 @@ CONFIG_SYSFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
@ -1360,6 +1393,16 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -1396,7 +1439,7 @@ CONFIG_SMB_FS=m
CONFIG_MSDOS_PARTITION=y
CONFIG_NLS=m
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
CONFIG_NLS_CODEPAGE_437=m
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
@ -1411,7 +1454,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
CONFIG_NLS_CODEPAGE_936=m
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
@ -1420,7 +1463,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set
CONFIG_NLS_ISO8859_1=m
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
@ -1433,7 +1476,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
CONFIG_NLS_UTF8=m
# CONFIG_DLM is not set
#
@ -1448,7 +1491,7 @@ CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
@ -1457,8 +1500,6 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
@ -1478,7 +1519,6 @@ CONFIG_DEBUG_INFO=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
#
# Tracers
@ -1494,16 +1534,20 @@ CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_MMRS=y
# CONFIG_DEBUG_HWERR is not set
# CONFIG_DEBUG_DOUBLEFAULT is not set
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_DOUBLEFAULT_PRINT=y
# CONFIG_DEBUG_DOUBLEFAULT_RESET is not set
# CONFIG_DEBUG_ICACHE_CHECK is not set
CONFIG_DEBUG_HUNT_FOR_ZERO=y
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1
# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
@ -1611,13 +1655,12 @@ CONFIG_BITREVERSE=y
CONFIG_CRC_CCITT=m
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC_ITU_T=m
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

103
arch/blackfin/configs/BF533-EZKIT_defconfig
View File

@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28.7
# Linux kernel version: 2.6.28.10
# Thu May 21 05:50:01 2009
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
@ -71,7 +72,6 @@ CONFIG_SLAB=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
@ -225,7 +225,10 @@ CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
CONFIG_TICK_ONESHOT=y
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
@ -382,7 +385,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -613,9 +616,8 @@ CONFIG_SMC91X=y
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -667,13 +669,13 @@ CONFIG_INPUT_EVDEV=m
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
# CONFIG_BF5xx_PPI is not set
# CONFIG_BFIN_SPI_ADC is not set
CONFIG_BFIN_SPORT=y
# CONFIG_BFIN_TIMER_LATENCY is not set
CONFIG_BFIN_DMA_INTERFACE=m
CONFIG_SIMPLE_GPIO=m
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
@ -729,7 +731,30 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
@ -904,16 +929,6 @@ CONFIG_SYSFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
@ -925,6 +940,16 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -1013,7 +1038,7 @@ CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
@ -1022,8 +1047,6 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
@ -1043,7 +1066,6 @@ CONFIG_DEBUG_INFO=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
#
# Tracers
@ -1059,16 +1081,20 @@ CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_MMRS=y
# CONFIG_DEBUG_HWERR is not set
# CONFIG_DEBUG_DOUBLEFAULT is not set
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_DOUBLEFAULT_PRINT=y
# CONFIG_DEBUG_DOUBLEFAULT_RESET is not set
# CONFIG_DEBUG_ICACHE_CHECK is not set
CONFIG_DEBUG_HUNT_FOR_ZERO=y
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1
# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
@ -1181,7 +1207,6 @@ CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

105
arch/blackfin/configs/BF533-STAMP_defconfig
View File

@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28.7
# Linux kernel version: 2.6.28.10
# Thu May 21 05:50:01 2009
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
@ -71,7 +72,6 @@ CONFIG_SLAB=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
@ -225,7 +225,10 @@ CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
CONFIG_TICK_ONESHOT=y
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
@ -382,7 +385,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -618,9 +621,8 @@ CONFIG_SMC91X=y
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -674,14 +676,14 @@ CONFIG_CONFIG_INPUT_PCF8574=m
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
CONFIG_BF5xx_PPI=m
# CONFIG_BFIN_SPI_ADC is not set
CONFIG_BFIN_SPORT=m
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_TWI_LCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_TWI_LCD is not set
CONFIG_SIMPLE_GPIO=m
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
@ -781,7 +783,30 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
@ -1068,16 +1093,6 @@ CONFIG_SYSFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
@ -1089,6 +1104,16 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -1177,7 +1202,7 @@ CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
@ -1186,8 +1211,6 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
@ -1207,7 +1230,6 @@ CONFIG_DEBUG_INFO=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
#
# Tracers
@ -1223,16 +1245,20 @@ CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_MMRS=y
# CONFIG_DEBUG_HWERR is not set
# CONFIG_DEBUG_DOUBLEFAULT is not set
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_DOUBLEFAULT_PRINT=y
# CONFIG_DEBUG_DOUBLEFAULT_RESET is not set
# CONFIG_DEBUG_ICACHE_CHECK is not set
CONFIG_DEBUG_HUNT_FOR_ZERO=y
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1
# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
@ -1345,7 +1371,6 @@ CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

109
arch/blackfin/configs/BF537-STAMP_defconfig
View File

@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28.7
# Linux kernel version: 2.6.28.10
# Thu May 21 05:50:01 2009
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
@ -71,7 +72,6 @@ CONFIG_SLAB=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
@ -232,7 +232,10 @@ CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
CONFIG_TICK_ONESHOT=y
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
@ -390,7 +393,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -548,9 +551,7 @@ CONFIG_MTD_ROM=m
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_PHYSMAP_START=0x20000000
CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_PHYSMAP_COMPAT is not set
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
@ -649,9 +650,8 @@ CONFIG_BFIN_RX_DESC_NUM=20
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -708,14 +708,14 @@ CONFIG_SERIO_LIBPS2=y
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
CONFIG_BF5xx_PPI=m
# CONFIG_BFIN_SPI_ADC is not set
CONFIG_BFIN_SPORT=m
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_TWI_LCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_TWI_LCD is not set
CONFIG_SIMPLE_GPIO=m
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
@ -823,7 +823,30 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
@ -1123,16 +1146,6 @@ CONFIG_SYSFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
@ -1144,6 +1157,16 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -1232,7 +1255,7 @@ CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
@ -1241,8 +1264,6 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
@ -1262,7 +1283,6 @@ CONFIG_DEBUG_INFO=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
#
# Tracers
@ -1278,16 +1298,20 @@ CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_MMRS=y
# CONFIG_DEBUG_HWERR is not set
# CONFIG_DEBUG_DOUBLEFAULT is not set
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_DOUBLEFAULT_PRINT=y
# CONFIG_DEBUG_DOUBLEFAULT_RESET is not set
# CONFIG_DEBUG_ICACHE_CHECK is not set
CONFIG_DEBUG_HUNT_FOR_ZERO=y
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1
# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
@ -1400,7 +1424,6 @@ CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

106
arch/blackfin/configs/BF538-EZKIT_defconfig
View File

@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28.7
# Linux kernel version: 2.6.28.10
# Thu May 21 05:50:01 2009
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
@ -71,7 +72,6 @@ CONFIG_SLAB=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
@ -243,7 +243,10 @@ CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
CONFIG_TICK_ONESHOT=y
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
@ -389,7 +392,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -546,9 +549,7 @@ CONFIG_MTD_ROM=m
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_PHYSMAP_START=0x20000000
CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_PHYSMAP_COMPAT is not set
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
@ -691,11 +692,11 @@ CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
CONFIG_TOUCHSCREEN_AD7879_SPI=y
CONFIG_TOUCHSCREEN_AD7879=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
@ -720,14 +721,14 @@ CONFIG_INPUT_MISC=y
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
CONFIG_BF5xx_PPI=m
# CONFIG_BFIN_SPI_ADC is not set
CONFIG_BFIN_SPORT=m
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_TWI_LCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_TWI_LCD is not set
CONFIG_SIMPLE_GPIO=m
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
@ -833,7 +834,30 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
@ -1056,16 +1080,6 @@ CONFIG_SYSFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
@ -1077,6 +1091,16 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -1165,7 +1189,7 @@ CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
@ -1174,8 +1198,6 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
@ -1195,7 +1217,6 @@ CONFIG_DEBUG_INFO=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
#
# Tracers
@ -1211,16 +1232,20 @@ CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_MMRS=y
# CONFIG_DEBUG_HWERR is not set
# CONFIG_DEBUG_DOUBLEFAULT is not set
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_DOUBLEFAULT_PRINT=y
# CONFIG_DEBUG_DOUBLEFAULT_RESET is not set
# CONFIG_DEBUG_ICACHE_CHECK is not set
CONFIG_DEBUG_HUNT_FOR_ZERO=y
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1
# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
@ -1333,7 +1358,6 @@ CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

253
arch/blackfin/configs/BF548-EZKIT_defconfig
View File

@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28.7
# Linux kernel version: 2.6.28.10
# Thu May 21 05:50:01 2009
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
@ -71,7 +72,6 @@ CONFIG_SLAB=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
@ -196,6 +196,7 @@ CONFIG_BFIN548_EZKIT=y
# BF548 Specific Configuration
#
# CONFIG_DEB_DMA_URGENT is not set
# CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set
#
# Interrupt Priority Assignment
@ -298,7 +299,10 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@ -367,7 +371,9 @@ CONFIG_BFIN_DCACHE=y
# CONFIG_BFIN_ICACHE_LOCK is not set
CONFIG_BFIN_WB=y
# CONFIG_BFIN_WT is not set
# CONFIG_BFIN_L2_CACHEABLE is not set
# CONFIG_BFIN_L2_WB is not set
CONFIG_BFIN_L2_WT=y
# CONFIG_BFIN_L2_NOT_CACHED is not set
# CONFIG_MPU is not set
#
@ -447,7 +453,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -616,9 +622,7 @@ CONFIG_MTD_RAM=y
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0x20000000
CONFIG_MTD_PHYSMAP_LEN=0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_PHYSMAP_COMPAT is not set
# CONFIG_MTD_GPIO_ADDR is not set
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
@ -696,7 +700,7 @@ CONFIG_SCSI_DMA=y
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
CONFIG_BLK_DEV_SR=m
# CONFIG_BLK_DEV_SR_VENDOR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
@ -718,9 +722,7 @@ CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_DH is not set
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
@ -752,9 +754,8 @@ CONFIG_SMSC911X=y
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -821,11 +822,11 @@ CONFIG_KEYBOARD_BFIN=y
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
CONFIG_TOUCHSCREEN_AD7877=m
# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
@ -858,14 +859,14 @@ CONFIG_INPUT_MISC=y
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
CONFIG_BF5xx_PPI=m
# CONFIG_BFIN_SPI_ADC is not set
CONFIG_BFIN_SPORT=m
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_TWI_LCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_TWI_LCD is not set
CONFIG_SIMPLE_GPIO=m
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
@ -977,7 +978,30 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
@ -1011,6 +1035,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_REGULATOR is not set
@ -1193,8 +1218,8 @@ CONFIG_USB=y
#
# Miscellaneous USB options
#
# CONFIG_USB_DEVICEFS is not set
CONFIG_USB_DEVICE_CLASS=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
@ -1222,10 +1247,10 @@ CONFIG_USB_MUSB_SOC=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_USB_MUSB_PERIPHERAL is not set
# CONFIG_USB_MUSB_OTG is not set
# CONFIG_USB_GADGET_MUSB_HDRC is not set
CONFIG_USB_MUSB_HDRC_HCD=y
CONFIG_MUSB_PIO_ONLY=y
CONFIG_MUSB_DMA_POLL=y
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_INVENTRA_DMA=y
# CONFIG_USB_TI_CPPI_DMA is not set
# CONFIG_USB_MUSB_DEBUG is not set
#
@ -1243,7 +1268,7 @@ CONFIG_MUSB_DMA_POLL=y
#
# see USB_STORAGE Help for more information
#
CONFIG_USB_STORAGE=m
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
@ -1292,33 +1317,10 @@ CONFIG_USB_STORAGE=m
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_VST is not set
# CONFIG_USB_GADGET is not set
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_PXA25X is not set
# CONFIG_USB_GADGET_PXA27X is not set
# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_FSL_QE is not set
# CONFIG_USB_GADGET_NET2272 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_ZERO is not set
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_CDC_COMPOSITE is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set
@ -1414,13 +1416,8 @@ CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
# CONFIG_EXT2_FS_POSIX_ACL is not set
# CONFIG_EXT2_FS_SECURITY is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
# CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
@ -1476,16 +1473,6 @@ CONFIG_SYSFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
@ -1497,6 +1484,16 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -1539,63 +1536,47 @@ CONFIG_CIFS=y
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
# CONFIG_SYSV68_PARTITION is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=m
# CONFIG_DLM is not set
@ -1611,7 +1592,7 @@ CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
@ -1620,8 +1601,6 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
@ -1641,7 +1620,6 @@ CONFIG_DEBUG_INFO=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
#
# Tracers
@ -1657,16 +1635,20 @@ CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_MMRS=y
# CONFIG_DEBUG_HWERR is not set
# CONFIG_DEBUG_DOUBLEFAULT is not set
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_DOUBLEFAULT_PRINT=y
# CONFIG_DEBUG_DOUBLEFAULT_RESET is not set
# CONFIG_DEBUG_ICACHE_CHECK is not set
CONFIG_DEBUG_HUNT_FOR_ZERO=y
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1
# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
@ -1780,7 +1762,6 @@ CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

116
arch/blackfin/configs/BF561-EZKIT_defconfig
View File

@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28.7
# Linux kernel version: 2.6.28.10
# Thu May 21 05:50:01 2009
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -42,10 +43,11 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -53,16 +55,15 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
@ -71,7 +72,6 @@ CONFIG_SLAB=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
@ -148,9 +148,9 @@ CONFIG_BF_REV_MAX=5
# CONFIG_BF_REV_0_0 is not set
# CONFIG_BF_REV_0_1 is not set
# CONFIG_BF_REV_0_2 is not set
CONFIG_BF_REV_0_3=y
# CONFIG_BF_REV_0_3 is not set
# CONFIG_BF_REV_0_4 is not set
# CONFIG_BF_REV_0_5 is not set
CONFIG_BF_REV_0_5=y
# CONFIG_BF_REV_0_6 is not set
# CONFIG_BF_REV_ANY is not set
# CONFIG_BF_REV_NONE is not set
@ -179,7 +179,6 @@ CONFIG_BFIN561_EZKIT=y
# Core B Support
#
CONFIG_BF561_COREB=y
CONFIG_BF561_COREB_RESET=y
#
# Interrupt Priority Assignment
@ -264,7 +263,10 @@ CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
CONFIG_TICK_ONESHOT=y
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
@ -334,7 +336,9 @@ CONFIG_BFIN_DCACHE=y
# CONFIG_BFIN_ICACHE_LOCK is not set
CONFIG_BFIN_WB=y
# CONFIG_BFIN_WT is not set
# CONFIG_BFIN_L2_CACHEABLE is not set
# CONFIG_BFIN_L2_WB is not set
CONFIG_BFIN_L2_WT=y
# CONFIG_BFIN_L2_NOT_CACHED is not set
# CONFIG_MPU is not set
#
@ -415,7 +419,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -570,9 +574,7 @@ CONFIG_MTD_ROM=m
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_PHYSMAP_START=0x20000000
CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_PHYSMAP_COMPAT is not set
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
@ -649,9 +651,8 @@ CONFIG_SMC91X=y
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -703,13 +704,13 @@ CONFIG_INPUT_EVDEV=m
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
# CONFIG_BF5xx_PPI is not set
# CONFIG_BFIN_SPI_ADC is not set
# CONFIG_BFIN_SPORT is not set
# CONFIG_BFIN_TIMER_LATENCY is not set
CONFIG_BFIN_DMA_INTERFACE=m
CONFIG_SIMPLE_GPIO=m
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
@ -765,7 +766,30 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
@ -897,16 +921,6 @@ CONFIG_SYSFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
@ -918,6 +932,16 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_YAFFS_FS=m
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
# CONFIG_YAFFS_DOES_ECC is not set
CONFIG_YAFFS_YAFFS2=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -1006,7 +1030,7 @@ CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
@ -1015,8 +1039,6 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
@ -1036,7 +1058,6 @@ CONFIG_DEBUG_INFO=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
#
# Tracers
@ -1052,16 +1073,20 @@ CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_MMRS=y
# CONFIG_DEBUG_HWERR is not set
# CONFIG_DEBUG_DOUBLEFAULT is not set
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_DOUBLEFAULT_PRINT=y
# CONFIG_DEBUG_DOUBLEFAULT_RESET is not set
# CONFIG_DEBUG_ICACHE_CHECK is not set
CONFIG_DEBUG_HUNT_FOR_ZERO=y
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=1
# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
@ -1174,7 +1199,6 @@ CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

4
arch/blackfin/configs/BlackStamp_defconfig
View File

@ -46,7 +46,7 @@ CONFIG_INITRAMFS_SOURCE=""
# CONFIG_SYSCTL is not set
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -381,7 +381,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set

29
arch/blackfin/configs/CM-BF527_defconfig
View File

@ -46,7 +46,7 @@ CONFIG_INITRAMFS_SOURCE=""
# CONFIG_SYSCTL is not set
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -411,7 +411,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -783,7 +783,30 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y

12
arch/blackfin/configs/CM-BF533_defconfig
View File

@ -49,7 +49,7 @@ CONFIG_LOG_BUF_SHIFT=14
# CONFIG_SYSCTL is not set
CONFIG_EMBEDDED=y
# CONFIG_UID16 is not set
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_HOTPLUG is not set
@ -347,7 +347,7 @@ CONFIG_IP_FIB_HASH=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -547,9 +547,9 @@ CONFIG_MII=y
CONFIG_SMC91X=y
# CONFIG_SMSC911X is not set
# CONFIG_DM9000 is not set
CONFIG_NETDEV_1000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -641,6 +641,10 @@ CONFIG_UNIX98_PTYS=y
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
#
# SPI support
#

505
arch/blackfin/configs/CM-BF537E_defconfig
View File

@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.22.16
# Linux kernel version: 2.6.28.10
# Wed Jun 3 06:27:41 2009
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -8,48 +9,44 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
CONFIG_BLACKFIN=y
CONFIG_ZONE_DMA=y
CONFIG_SEMAPHORE_SLEEPERS=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_GPIO=y
CONFIG_FORCE_MAX_ZONEORDER=14
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_UTS_NS is not set
# CONFIG_AUDIT is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_CGROUPS is not set
# CONFIG_GROUP_SCHED is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
# CONFIG_UID16 is not set
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_HOTPLUG is not set
@ -58,37 +55,36 @@ CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
# CONFIG_NP2 is not set
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
#
# Loadable module support
#
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
@ -102,9 +98,11 @@ CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
CONFIG_CLASSIC_RCU=y
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
# CONFIG_FREEZER is not set
#
# Blackfin Processor Options
@ -113,6 +111,10 @@ CONFIG_PREEMPT_NONE=y
#
# Processor and Board Settings
#
# CONFIG_BF512 is not set
# CONFIG_BF514 is not set
# CONFIG_BF516 is not set
# CONFIG_BF518 is not set
# CONFIG_BF522 is not set
# CONFIG_BF523 is not set
# CONFIG_BF524 is not set
@ -125,22 +127,31 @@ CONFIG_PREEMPT_NONE=y
# CONFIG_BF534 is not set
# CONFIG_BF536 is not set
CONFIG_BF537=y
# CONFIG_BF538 is not set
# CONFIG_BF539 is not set
# CONFIG_BF542 is not set
# CONFIG_BF542M is not set
# CONFIG_BF544 is not set
# CONFIG_BF544M is not set
# CONFIG_BF547 is not set
# CONFIG_BF547M is not set
# CONFIG_BF548 is not set
# CONFIG_BF548M is not set
# CONFIG_BF549 is not set
# CONFIG_BF549M is not set
# CONFIG_BF561 is not set
CONFIG_BF_REV_MIN=2
CONFIG_BF_REV_MAX=3
# CONFIG_BF_REV_0_0 is not set
# CONFIG_BF_REV_0_1 is not set
CONFIG_BF_REV_0_2=y
# CONFIG_BF_REV_0_3 is not set
# CONFIG_BF_REV_0_4 is not set
# CONFIG_BF_REV_0_5 is not set
# CONFIG_BF_REV_0_6 is not set
# CONFIG_BF_REV_ANY is not set
# CONFIG_BF_REV_NONE is not set
CONFIG_BF53x=y
CONFIG_BFIN_SINGLE_CORE=y
CONFIG_MEM_MT48LC16M16A2TG_75=y
CONFIG_IRQ_PLL_WAKEUP=7
CONFIG_IRQ_RTC=8
@ -150,7 +161,6 @@ CONFIG_IRQ_SPORT0_TX=9
CONFIG_IRQ_SPORT1_RX=9
CONFIG_IRQ_SPORT1_TX=9
CONFIG_IRQ_TWI=10
CONFIG_IRQ_SPI=10
CONFIG_IRQ_UART0_RX=10
CONFIG_IRQ_UART0_TX=10
CONFIG_IRQ_UART1_RX=10
@ -169,11 +179,12 @@ CONFIG_IRQ_PORTG_INTB=12
CONFIG_IRQ_MEM_DMA0=13
CONFIG_IRQ_MEM_DMA1=13
CONFIG_IRQ_WATCH=13
CONFIG_IRQ_SPI=10
# CONFIG_BFIN537_STAMP is not set
CONFIG_BFIN537_BLUETECHNIX_CM=y
# CONFIG_BFIN537_BLUETECHNIX_TCM is not set
# CONFIG_PNAV10 is not set
# CONFIG_CAMSIG_MINOTAUR is not set
# CONFIG_GENERIC_BF537_BOARD is not set
#
# BF537 Specific Configuration
@ -196,6 +207,7 @@ CONFIG_IRQ_PROG_INTA=12
# Board customizations
#
# CONFIG_CMDLINE_BOOL is not set
CONFIG_BOOT_LOAD=0x1000
#
# Clock/PLL Setup
@ -215,13 +227,20 @@ CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
#
# Memory Setup
# Misc
#
CONFIG_MAX_MEM_SIZE=32
CONFIG_MEM_ADD_WIDTH=9
CONFIG_BOOT_LOAD=0x1000
CONFIG_BFIN_SCRATCH_REG_RETN=y
# CONFIG_BFIN_SCRATCH_REG_RETE is not set
# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@ -248,6 +267,12 @@ CONFIG_IP_CHECKSUM_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
CONFIG_SYSCALL_TAB_L1=y
CONFIG_CPLB_SWITCH_TAB_L1=y
CONFIG_APP_STACK_L1=y
#
# Speed Optimizations
#
CONFIG_BFIN_INS_LOWOVERHEAD=y
CONFIG_RAMKERNEL=y
# CONFIG_ROMKERNEL is not set
CONFIG_SELECT_MEMORY_MODEL=y
@ -256,12 +281,14 @@ CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_LARGE_ALLOCS=y
CONFIG_VIRT_TO_BUS=y
# CONFIG_BFIN_GPTIMERS is not set
# CONFIG_DMA_UNCACHED_4M is not set
# CONFIG_DMA_UNCACHED_2M is not set
CONFIG_DMA_UNCACHED_1M=y
# CONFIG_DMA_UNCACHED_NONE is not set
@ -275,7 +302,6 @@ CONFIG_BFIN_DCACHE=y
# CONFIG_BFIN_ICACHE_LOCK is not set
CONFIG_BFIN_WB=y
# CONFIG_BFIN_WT is not set
CONFIG_L1_MAX_PIECE=16
# CONFIG_MPU is not set
#
@ -304,13 +330,8 @@ CONFIG_BANK_3=0xFFC2
#
# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
#
# CONFIG_PCI is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
# PCCARD (PCMCIA/CardBus) support
#
#
# Executable file formats
#
@ -318,22 +339,19 @@ CONFIG_BINFMT_ELF_FDPIC=y
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y
CONFIG_BINFMT_SHARED_FLAT=y
# CONFIG_HAVE_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options
#
# CONFIG_PM is not set
# CONFIG_PM_WAKEUP_BY_GPIO is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
#
# Networking
#
CONFIG_NET=y
#
@ -346,6 +364,7 @@ CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
@ -358,7 +377,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -367,6 +386,7 @@ CONFIG_SYN_COOKIES=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
@ -374,8 +394,6 @@ CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETLABEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
@ -384,6 +402,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
@ -393,10 +412,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
@ -404,18 +419,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_PHONET is not set
# CONFIG_WIRELESS is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
@ -427,10 +438,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
@ -438,6 +445,7 @@ CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set
#
# User Modules And Translation Layers
@ -450,12 +458,15 @@ CONFIG_MTD_BLOCK=y
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
@ -466,6 +477,10 @@ CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
@ -473,7 +488,8 @@ CONFIG_MTD_RAM=y
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_GPIO_ADDR=y
CONFIG_MTD_UCLINUX=y
# CONFIG_MTD_PLATRAM is not set
@ -498,33 +514,23 @@ CONFIG_MTD_UCLINUX=y
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNPACPI is not set
#
# Block devices
#
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
#
# Misc devices
#
# CONFIG_BLK_DEV_HD is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_C2PORT is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
@ -532,22 +538,17 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
CONFIG_PHYLIB=y
#
@ -561,46 +562,44 @@ CONFIG_PHYLIB=y
# CONFIG_VITESSE_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_FIXED_PHY is not set
#
# Ethernet (10 or 100Mbit)
#
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_SMC91X is not set
CONFIG_BFIN_MAC=y
CONFIG_BFIN_MAC_USE_L1=y
CONFIG_BFIN_TX_DESC_NUM=10
CONFIG_BFIN_RX_DESC_NUM=20
# CONFIG_BFIN_MAC_RMII is not set
# CONFIG_SMC91X is not set
# CONFIG_SMSC911X is not set
# CONFIG_DM9000 is not set
CONFIG_NETDEV_1000=y
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_IWLWIFI_LEDS is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
@ -618,15 +617,17 @@ CONFIG_NETDEV_10000=y
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PFLAGS is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
# CONFIG_BF5xx_PPI is not set
# CONFIG_BFIN_SPI_ADC is not set
CONFIG_BFIN_SPORT=y
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_SIMPLE_GPIO is not set
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
# CONFIG_BFIN_JTAG_COMM is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
@ -655,138 +656,119 @@ CONFIG_UNIX98_PTYS=y
# CAN, the car bus and industrial fieldbus
#
# CONFIG_CAN4LINUX is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
#
# Dallas's 1-wire bus
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_ABITUGURU is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_REGULATOR is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
# CONFIG_FB is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
#
# Enable Host or Gadget support to see Inventra options
#
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
#
# LED devices
#
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# InfiniBand support
#
#
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
#
#
# Real Time Clock
#
# CONFIG_ACCESSIBILITY is not set
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# PBX support
#
# CONFIG_PBX is not set
# CONFIG_DMADEVICES is not set
# CONFIG_UIO is not set
# CONFIG_STAGING is not set
#
# File systems
@ -796,20 +778,18 @@ CONFIG_EXT2_FS_XATTR=y
# CONFIG_EXT2_FS_POSIX_ACL is not set
# CONFIG_EXT2_FS_SECURITY is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_EXT4_FS is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
CONFIG_FILE_LOCKING=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
# CONFIG_DNOTIFY is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
@ -835,7 +815,6 @@ CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
@ -848,60 +827,53 @@ CONFIG_RAMFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_YAFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_YAFFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
# CONFIG_NFS_FS is not set
# CONFIG_NFSD is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_SECTION_MISMATCH=y
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
#
# Tracers
#
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_MMRS=y
# CONFIG_DEBUG_DOUBLEFAULT is not set
CONFIG_DEBUG_HUNT_FOR_ZERO=y
CONFIG_DEBUG_BFIN_HWTRACE_ON=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@ -919,13 +891,95 @@ CONFIG_ACCESS_CHECK=y
#
# CONFIG_KEYS is not set
CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
CONFIG_SECURITY_CAPABILITIES=y
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
CONFIG_CRYPTO=y
#
# Cryptographic options
# Crypto core or helper
#
# CONFIG_CRYPTO is not set
# CONFIG_CRYPTO_FIPS is not set
# CONFIG_CRYPTO_MANAGER is not set
# CONFIG_CRYPTO_MANAGER2 is not set
# CONFIG_CRYPTO_GF128MUL is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_TEST is not set
#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_SEQIV is not set
#
# Block modes
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set
#
# Hash modes
#
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
#
# Digest
#
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set
#
# Ciphers
#
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set
#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_LZO is not set
#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_HW=y
#
# Library routines
@ -933,11 +987,12 @@ CONFIG_SECURITY_CAPABILITIES=y
CONFIG_BITREVERSE=y
CONFIG_CRC_CCITT=m
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

12
arch/blackfin/configs/CM-BF537U_defconfig
View File

@ -49,7 +49,7 @@ CONFIG_LOG_BUF_SHIFT=14
# CONFIG_SYSCTL is not set
CONFIG_EMBEDDED=y
# CONFIG_UID16 is not set
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_HOTPLUG is not set
@ -355,7 +355,7 @@ CONFIG_IP_FIB_HASH=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -556,9 +556,9 @@ CONFIG_SMC91X=y
# CONFIG_BFIN_MAC is not set
# CONFIG_SMSC911X is not set
# CONFIG_DM9000 is not set
CONFIG_NETDEV_1000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -652,6 +652,10 @@ CONFIG_UNIX98_PTYS=y
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
#
# SPI support
#

12
arch/blackfin/configs/CM-BF548_defconfig
View File

@ -49,7 +49,7 @@ CONFIG_INITRAMFS_SOURCE=""
# CONFIG_SYSCTL is not set
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
@ -125,9 +125,9 @@ CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_BF548=y
# CONFIG_BF549 is not set
# CONFIG_BF561 is not set
CONFIG_BF_REV_0_0=y
# CONFIG_BF_REV_0_0 is not set
# CONFIG_BF_REV_0_1 is not set
# CONFIG_BF_REV_0_2 is not set
CONFIG_BF_REV_0_2=y
# CONFIG_BF_REV_0_3 is not set
# CONFIG_BF_REV_0_4 is not set
# CONFIG_BF_REV_0_5 is not set
@ -422,7 +422,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -811,6 +811,10 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
#
# SPI support
#

12
arch/blackfin/configs/CM-BF561_defconfig
View File

@ -49,7 +49,7 @@ CONFIG_FAIR_USER_SCHED=y
# CONFIG_SYSCTL is not set
CONFIG_EMBEDDED=y
# CONFIG_UID16 is not set
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_HOTPLUG is not set
@ -389,7 +389,7 @@ CONFIG_IP_FIB_HASH=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -569,9 +569,9 @@ CONFIG_SMC91X=y
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -646,6 +646,10 @@ CONFIG_UNIX98_PTYS=y
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
#
# SPI support
#

8
arch/blackfin/configs/H8606_defconfig
View File

@ -48,7 +48,7 @@ CONFIG_SYSFS_DEPRECATED=y
# CONFIG_SYSCTL is not set
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
@ -347,7 +347,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -594,8 +594,8 @@ CONFIG_MII=y
# CONFIG_SMC91X is not set
# CONFIG_SMSC911X is not set
CONFIG_DM9000=y
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_AX88180 is not set
#

8
arch/blackfin/configs/IP0X_defconfig
View File

@ -49,7 +49,7 @@ CONFIG_INITRAMFS_SOURCE=""
# CONFIG_SYSCTL is not set
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_HOTPLUG is not set
@ -355,7 +355,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -672,9 +672,9 @@ CONFIG_MII=y
# CONFIG_SMC91X is not set
# CONFIG_SMSC911X is not set
CONFIG_DM9000=y
CONFIG_NETDEV_1000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN

39
arch/blackfin/configs/PNAV-10_defconfig
View File

@ -1,6 +1,6 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28.7
# Linux kernel version: 2.6.28.10
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -40,26 +40,26 @@ CONFIG_LOG_BUF_SHIFT=14
# CONFIG_NAMESPACES is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_AIO is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
@ -68,7 +68,6 @@ CONFIG_SLAB=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
@ -229,7 +228,10 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@ -374,7 +376,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
@ -598,9 +600,8 @@ CONFIG_BFIN_MAC_RMII=y
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
# CONFIG_AX88180 is not set
CONFIG_NETDEV_10000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
@ -640,11 +641,11 @@ CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
CONFIG_TOUCHSCREEN_AD7877=y
# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
@ -676,14 +677,14 @@ CONFIG_INPUT_UINPUT=y
# Character devices
#
# CONFIG_AD9960 is not set
# CONFIG_SPI_ADC_BF533 is not set
# CONFIG_BF5xx_PPIFCD is not set
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_PPI is not set
# CONFIG_BFIN_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
# CONFIG_BF5xx_PPI is not set
# CONFIG_BFIN_SPI_ADC is not set
CONFIG_BFIN_SPORT=y
# CONFIG_BFIN_TIMER_LATENCY is not set
CONFIG_TWI_LCD=m
CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_TWI_LCD is not set
# CONFIG_SIMPLE_GPIO is not set
# CONFIG_VT is not set
CONFIG_DEVKMEM=y
@ -796,6 +797,7 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_AD5252 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADCXX is not set
@ -867,6 +869,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_REGULATOR is not set
@ -1111,6 +1114,7 @@ CONFIG_SYSFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_YAFFS_FS=y
CONFIG_YAFFS_YAFFS1=y
# CONFIG_YAFFS_9BYTE_TAGS is not set
@ -1121,7 +1125,6 @@ CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -1213,7 +1216,6 @@ CONFIG_FRAME_WARN=1024
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
#
# Tracers
@ -1343,7 +1345,6 @@ CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

4
arch/blackfin/configs/SRV1_defconfig
View File

@ -52,7 +52,7 @@ CONFIG_INITRAMFS_SOURCE=""
# CONFIG_SYSCTL is not set
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -373,7 +373,7 @@ CONFIG_IP_PNP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set

27
arch/blackfin/configs/TCM-BF537_defconfig
View File

@ -42,7 +42,7 @@ CONFIG_LOG_BUF_SHIFT=14
# CONFIG_SYSCTL is not set
CONFIG_EMBEDDED=y
# CONFIG_UID16 is not set
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_HOTPLUG is not set
@ -537,7 +537,30 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set

40
arch/blackfin/include/asm/cacheflush.h
View File

@ -30,7 +30,8 @@
#ifndef _BLACKFIN_CACHEFLUSH_H
#define _BLACKFIN_CACHEFLUSH_H
extern void blackfin_icache_dcache_flush_range(unsigned long start_address, unsigned long end_address);
#include <asm/blackfin.h> /* for SSYNC() */
extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
@ -54,32 +55,28 @@ extern void blackfin_invalidate_entire_dcache(void);
static inline void flush_icache_range(unsigned start, unsigned end)
{
#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
#if defined(CONFIG_BFIN_WB)
blackfin_dcache_flush_range(start, end);
#endif
# if defined(CONFIG_BFIN_WT)
blackfin_icache_flush_range((start), (end));
/* Make sure all write buffers in the data side of the core
* are flushed before trying to invalidate the icache. This
* needs to be after the data flush and before the icache
* flush so that the SSYNC does the right thing in preventing
* the instruction prefetcher from hitting things in cached
* memory at the wrong time -- it runs much further ahead than
* the pipeline.
*/
SSYNC();
#if defined(CONFIG_BFIN_ICACHE)
blackfin_icache_flush_range(start, end);
flush_icache_range_others(start, end);
# else
blackfin_icache_dcache_flush_range((start), (end));
# endif
#else
# if defined(CONFIG_BFIN_ICACHE)
blackfin_icache_flush_range((start), (end));
flush_icache_range_others(start, end);
# endif
# if defined(CONFIG_BFIN_DCACHE)
blackfin_dcache_flush_range((start), (end));
# endif
#endif
}
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { memcpy(dst, src, len); \
flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
flush_icache_range_others((unsigned long) (dst), (unsigned long) (dst) + (len));\
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
@ -111,6 +108,11 @@ static inline int bfin_addr_dcachable(unsigned long addr)
addr >= _ramend && addr < physical_mem_end)
return 1;
#ifndef CONFIG_BFIN_L2_NOT_CACHED
if (addr >= L2_START && addr < L2_START + L2_LENGTH)
return 1;
#endif
return 0;
}

41
arch/blackfin/include/asm/cplb.h
View File

@ -53,29 +53,32 @@
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
#endif
#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
#ifdef CONFIG_SMP
#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
#define L2_IMEMORY (CPLB_COMMON | CPLB_LOCK)
#define L2_DMEMORY (CPLB_COMMON | CPLB_LOCK)
#else
#ifdef CONFIG_BFIN_L2_CACHEABLE
#define L2_IMEMORY (SDRAM_IGENERIC)
#define L2_DMEMORY (SDRAM_DGENERIC)
#else
#define L2_IMEMORY (CPLB_COMMON)
#define L2_DMEMORY (CPLB_COMMON)
#endif /* CONFIG_BFIN_L2_CACHEABLE */
#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
#endif /* CONFIG_SMP */
#define SDRAM_DNON_CHBL (CPLB_COMMON)
#define SDRAM_EBIU (CPLB_COMMON)
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
#ifdef CONFIG_SMP
#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
#define L2_IMEMORY (CPLB_COMMON)
#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON)
#else
#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
#define L2_IMEMORY (SDRAM_IGENERIC)
# if defined(CONFIG_BFIN_L2_WB)
# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON)
# elif defined(CONFIG_BFIN_L2_WT)
# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
# elif defined(CONFIG_BFIN_L2_NOT_CACHED)
# define L2_DMEMORY (CPLB_COMMON)
# else
# define L2_DMEMORY (0)
# endif
#endif /* CONFIG_SMP */
#define SIZE_1K 0x00000400 /* 1K */
#define SIZE_4K 0x00001000 /* 4K */
#define SIZE_1M 0x00100000 /* 1M */

10
arch/blackfin/include/asm/dma.h
View File

@ -206,10 +206,16 @@ static inline unsigned long get_dma_curr_addr(unsigned int channel)
static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
{
/* Make sure the internal data buffers in the core are drained
* so that the DMA descriptors are completely written when the
* DMA engine goes to fetch them below.
*/
SSYNC();
dma_ch[channel].regs->next_desc_ptr = sg;
dma_ch[channel].regs->cfg =
(dma_ch[channel].regs->cfg & ~(0xf << 8)) |
((ndsize & 0xf) << 8);
dma_ch[channel].regs->next_desc_ptr = sg;
}
static inline int dma_channel_active(unsigned int channel)
@ -253,5 +259,7 @@ static inline void clear_dma_irqstat(unsigned int channel)
void *dma_memcpy(void *dest, const void *src, size_t count);
void *safe_dma_memcpy(void *dest, const void *src, size_t count);
void blackfin_dma_early_init(void);
void early_dma_memcpy(void *dest, const void *src, size_t count);
void early_dma_memcpy_done(void);
#endif

84
arch/blackfin/include/asm/elf.h
View File

@ -55,50 +55,50 @@ do { \
#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC
#define ELF_EXEC_PAGESIZE 4096
#define R_unused0 0 /* relocation type 0 is not defined */
#define R_pcrel5m2 1 /*LSETUP part a */
#define R_unused1 2 /* relocation type 2 is not defined */
#define R_pcrel10 3 /* type 3, if cc jump <target> */
#define R_pcrel12_jump 4 /* type 4, jump <target> */
#define R_rimm16 5 /* type 0x5, rN = <target> */
#define R_luimm16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */
#define R_huimm16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */
#define R_pcrel12_jump_s 8 /* # 0x8 jump.s <target> */
#define R_pcrel24_jump_x 9 /* # 0x9 jump.x <target> */
#define R_pcrel24 10 /* # 0xa call <target> , not expandable */
#define R_unusedb 11 /* # 0xb not generated */
#define R_unusedc 12 /* # 0xc not used */
#define R_pcrel24_jump_l 13 /*0xd jump.l <target> */
#define R_pcrel24_call_x 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
#define R_var_eq_symb 15 /* 0xf, linker should treat it same as 0x12 */
#define R_byte_data 16 /* 0x10, .byte var = symbol */
#define R_byte2_data 17 /* 0x11, .byte2 var = symbol */
#define R_byte4_data 18 /* 0x12, .byte4 var = symbol and .var var=symbol */
#define R_pcrel11 19 /* 0x13, lsetup part b */
#define R_unused14 20 /* 0x14, undefined */
#define R_unused15 21 /* not generated by VDSP 3.5 */
#define R_BFIN_UNUSED0 0 /* relocation type 0 is not defined */
#define R_BFIN_PCREL5M2 1 /* LSETUP part a */
#define R_BFIN_UNUSED1 2 /* relocation type 2 is not defined */
#define R_BFIN_PCREL10 3 /* type 3, if cc jump <target> */
#define R_BFIN_PCREL12_JUMP 4 /* type 4, jump <target> */
#define R_BFIN_RIMM16 5 /* type 0x5, rN = <target> */
#define R_BFIN_LUIMM16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */
#define R_BFIN_HUIMM16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */
#define R_BFIN_PCREL12_JUMP_S 8 /* # 0x8 jump.s <target> */
#define R_BFIN_PCREL24_JUMP_X 9 /* # 0x9 jump.x <target> */
#define R_BFIN_PCREL24 10 /* # 0xa call <target> , not expandable */
#define R_BFIN_UNUSEDB 11 /* # 0xb not generated */
#define R_BFIN_UNUSEDC 12 /* # 0xc not used */
#define R_BFIN_PCREL24_JUMP_L 13 /* 0xd jump.l <target> */
#define R_BFIN_PCREL24_CALL_X 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
#define R_BFIN_VAR_EQ_SYMB 15 /* 0xf, linker should treat it same as 0x12 */
#define R_BFIN_BYTE_DATA 16 /* 0x10, .byte var = symbol */
#define R_BFIN_BYTE2_DATA 17 /* 0x11, .byte2 var = symbol */
#define R_BFIN_BYTE4_DATA 18 /* 0x12, .byte4 var = symbol and .var var=symbol */
#define R_BFIN_PCREL11 19 /* 0x13, lsetup part b */
#define R_BFIN_UNUSED14 20 /* 0x14, undefined */
#define R_BFIN_UNUSED15 21 /* not generated by VDSP 3.5 */
/* arithmetic relocations */
#define R_push 0xE0
#define R_const 0xE1
#define R_add 0xE2
#define R_sub 0xE3
#define R_mult 0xE4
#define R_div 0xE5
#define R_mod 0xE6
#define R_lshift 0xE7
#define R_rshift 0xE8
#define R_and 0xE9
#define R_or 0xEA
#define R_xor 0xEB
#define R_land 0xEC
#define R_lor 0xED
#define R_len 0xEE
#define R_neg 0xEF
#define R_comp 0xF0
#define R_page 0xF1
#define R_hwpage 0xF2
#define R_addr 0xF3
#define R_BFIN_PUSH 0xE0
#define R_BFIN_CONST 0xE1
#define R_BFIN_ADD 0xE2
#define R_BFIN_SUB 0xE3
#define R_BFIN_MULT 0xE4
#define R_BFIN_DIV 0xE5
#define R_BFIN_MOD 0xE6
#define R_BFIN_LSHIFT 0xE7
#define R_BFIN_RSHIFT 0xE8
#define R_BFIN_AND 0xE9
#define R_BFIN_OR 0xEA
#define R_BFIN_XOR 0xEB
#define R_BFIN_LAND 0xEC
#define R_BFIN_LOR 0xED
#define R_BFIN_LEN 0xEE
#define R_BFIN_NEG 0xEF
#define R_BFIN_COMP 0xF0
#define R_BFIN_PAGE 0xF1
#define R_BFIN_HWPAGE 0xF2
#define R_BFIN_ADDR 0xF3
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of

92
arch/blackfin/include/asm/entry.h
View File

@ -35,21 +35,39 @@
#else
# define LOAD_IPIPE_IPEND
#endif
#ifndef CONFIG_EXACT_HWERR
/* As a debugging aid - we save IPEND when DEBUG_KERNEL is on,
* otherwise it is a waste of cycles.
*/
# ifndef CONFIG_DEBUG_KERNEL
#define INTERRUPT_ENTRY(N) \
[--sp] = SYSCFG; \
\
[--sp] = P0; /*orig_p0*/ \
[--sp] = R0; /*orig_r0*/ \
[--sp] = (R7:0,P5:0); \
R0 = (N); \
LOAD_IPIPE_IPEND \
jump __common_int_entry;
# else /* CONFIG_DEBUG_KERNEL */
#define INTERRUPT_ENTRY(N) \
[--sp] = SYSCFG; \
[--sp] = P0; /*orig_p0*/ \
[--sp] = R0; /*orig_r0*/ \
[--sp] = (R7:0,P5:0); \
p0.l = lo(IPEND); \
p0.h = hi(IPEND); \
r1 = [p0]; \
R0 = (N); \
LOAD_IPIPE_IPEND \
jump __common_int_entry;
# endif /* CONFIG_DEBUG_KERNEL */
/* For timer interrupts, we need to save IPEND, since the user_mode
macro accesses it to determine where to account time. */
*macro accesses it to determine where to account time.
*/
#define TIMER_INTERRUPT_ENTRY(N) \
[--sp] = SYSCFG; \
\
[--sp] = P0; /*orig_p0*/ \
[--sp] = R0; /*orig_r0*/ \
[--sp] = (R7:0,P5:0); \
@ -58,6 +76,74 @@
r1 = [p0]; \
R0 = (N); \
jump __common_int_entry;
#else /* CONFIG_EXACT_HWERR is defined */
/* if we want hardware error to be exact, we need to do a SSYNC (which forces
* read/writes to complete to the memory controllers), and check to see that
* caused a pending HW error condition. If so, we assume it was caused by user
* space, by setting the same interrupt that we are in (so it goes off again)
* and context restore, and a RTI (without servicing anything). This should
* cause the pending HWERR to fire, and when that is done, this interrupt will
* be re-serviced properly.
* As you can see by the code - we actually need to do two SSYNCS - one to
* make sure the read/writes complete, and another to make sure the hardware
* error is recognized by the core.
*/
#define INTERRUPT_ENTRY(N) \
SSYNC; \
SSYNC; \
[--sp] = SYSCFG; \
[--sp] = P0; /*orig_p0*/ \
[--sp] = R0; /*orig_r0*/ \
[--sp] = (R7:0,P5:0); \
R1 = ASTAT; \
P0.L = LO(ILAT); \
P0.H = HI(ILAT); \
R0 = [P0]; \
CC = BITTST(R0, EVT_IVHW_P); \
IF CC JUMP 1f; \
ASTAT = R1; \
p0.l = lo(IPEND); \
p0.h = hi(IPEND); \
r1 = [p0]; \
R0 = (N); \
LOAD_IPIPE_IPEND \
jump __common_int_entry; \
1: ASTAT = R1; \
RAISE N; \
(R7:0, P5:0) = [SP++]; \
SP += 0x8; \
SYSCFG = [SP++]; \
CSYNC; \
RTI;
#define TIMER_INTERRUPT_ENTRY(N) \
SSYNC; \
SSYNC; \
[--sp] = SYSCFG; \
[--sp] = P0; /*orig_p0*/ \
[--sp] = R0; /*orig_r0*/ \
[--sp] = (R7:0,P5:0); \
R1 = ASTAT; \
P0.L = LO(ILAT); \
P0.H = HI(ILAT); \
R0 = [P0]; \
CC = BITTST(R0, EVT_IVHW_P); \
IF CC JUMP 1f; \
ASTAT = R1; \
p0.l = lo(IPEND); \
p0.h = hi(IPEND); \
r1 = [p0]; \
R0 = (N); \
jump __common_int_entry; \
1: ASTAT = R1; \
RAISE N; \
(R7:0, P5:0) = [SP++]; \
SP += 0x8; \
SYSCFG = [SP++]; \
CSYNC; \
RTI;
#endif /* CONFIG_EXACT_HWERR */
/* This one pushes RETI without using CLI. Interrupts are enabled. */
#define SAVE_CONTEXT_SYSCALL save_context_syscall

43
arch/blackfin/include/asm/gptimers.h
View File

@ -30,6 +30,7 @@
# else
# define MAX_BLACKFIN_GPTIMERS 11
# define TIMER8_GROUP_REG TIMER_ENABLE1
# define TIMER_GROUP2 1
# endif
# define TIMER0_GROUP_REG TIMER_ENABLE0
#endif
@ -40,10 +41,12 @@
# define MAX_BLACKFIN_GPTIMERS 12
# define TIMER0_GROUP_REG TMRS8_ENABLE
# define TIMER8_GROUP_REG TMRS4_ENABLE
# define TIMER_GROUP2 1
#endif
/*
* All others: 3 timers:
*/
#define TIMER_GROUP1 0
#if !defined(MAX_BLACKFIN_GPTIMERS)
# define MAX_BLACKFIN_GPTIMERS 3
# define TIMER0_GROUP_REG TIMER_ENABLE
@ -109,8 +112,8 @@
#define TIMER_ERR_PROG_PER 0x8000
#define TIMER_ERR_PROG_PW 0xC000
#define TIMER_EMU_RUN 0x0200
#define TIMER_TOGGLE_HI 0x0100
#define TIMER_CLK_SEL 0x0080
#define TIMER_TOGGLE_HI 0x0100
#define TIMER_CLK_SEL 0x0080
#define TIMER_OUT_DIS 0x0040
#define TIMER_TIN_SEL 0x0020
#define TIMER_IRQ_ENA 0x0010
@ -169,23 +172,25 @@
/* The actual gptimer API */
void set_gptimer_pwidth (int timer_id, uint32_t width);
uint32_t get_gptimer_pwidth (int timer_id);
void set_gptimer_period (int timer_id, uint32_t period);
uint32_t get_gptimer_period (int timer_id);
uint32_t get_gptimer_count (int timer_id);
uint16_t get_gptimer_intr (int timer_id);
void clear_gptimer_intr (int timer_id);
uint16_t get_gptimer_over (int timer_id);
void clear_gptimer_over (int timer_id);
void set_gptimer_config (int timer_id, uint16_t config);
uint16_t get_gptimer_config (int timer_id);
void set_gptimer_pulse_hi (int timer_id);
void set_gptimer_pwidth(int timer_id, uint32_t width);
uint32_t get_gptimer_pwidth(int timer_id);
void set_gptimer_period(int timer_id, uint32_t period);
uint32_t get_gptimer_period(int timer_id);
uint32_t get_gptimer_count(int timer_id);
int get_gptimer_intr(int timer_id);
void clear_gptimer_intr(int timer_id);
int get_gptimer_over(int timer_id);
void clear_gptimer_over(int timer_id);
void set_gptimer_config(int timer_id, uint16_t config);
uint16_t get_gptimer_config(int timer_id);
int get_gptimer_run(int timer_id);
void set_gptimer_pulse_hi(int timer_id);
void clear_gptimer_pulse_hi(int timer_id);
void enable_gptimers (uint16_t mask);
void disable_gptimers (uint16_t mask);
uint16_t get_enabled_gptimers (void);
uint32_t get_gptimer_status (int group);
void set_gptimer_status (int group, uint32_t value);
void enable_gptimers(uint16_t mask);
void disable_gptimers(uint16_t mask);
void disable_gptimers_sync(uint16_t mask);
uint16_t get_enabled_gptimers(void);
uint32_t get_gptimer_status(int group);
void set_gptimer_status(int group, uint32_t value);
#endif

27
arch/blackfin/include/asm/io.h
View File

@ -80,19 +80,22 @@ static inline unsigned int readl(const volatile void __iomem *addr)
#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
#define inb(addr) readb(addr)
#define inw(addr) readw(addr)
#define inl(addr) readl(addr)
#define outb(x,addr) ((void) writeb(x,addr))
#define outw(x,addr) ((void) writew(x,addr))
#define outl(x,addr) ((void) writel(x,addr))
/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */
#define __io(port) ((void *)(unsigned long)(port))
#define inb_p(addr) inb(addr)
#define inw_p(addr) inw(addr)
#define inl_p(addr) inl(addr)
#define outb_p(x,addr) outb(x,addr)
#define outw_p(x,addr) outw(x,addr)
#define outl_p(x,addr) outl(x,addr)
#define inb(port) readb(__io(port))
#define inw(port) readw(__io(port))
#define inl(port) readl(__io(port))
#define outb(x,port) writeb(x,__io(port))
#define outw(x,port) writew(x,__io(port))
#define outl(x,port) writel(x,__io(port))
#define inb_p(port) inb(__io(port))
#define inw_p(port) inw(__io(port))
#define inl_p(port) inl(__io(port))
#define outb_p(x,port) outb(x,__io(port))
#define outw_p(x,port) outw(x,__io(port))
#define outl_p(x,port) outl(x,__io(port))
#define ioread8_rep(a,d,c) readsb(a,d,c)
#define ioread16_rep(a,d,c) readsw(a,d,c)

4
arch/blackfin/include/asm/ipipe.h
View File

@ -35,10 +35,10 @@
#include <asm/atomic.h>
#include <asm/traps.h>
#define IPIPE_ARCH_STRING "1.9-00"
#define IPIPE_ARCH_STRING "1.9-01"
#define IPIPE_MAJOR_NUMBER 1
#define IPIPE_MINOR_NUMBER 9
#define IPIPE_PATCH_NUMBER 0
#define IPIPE_PATCH_NUMBER 1
#ifdef CONFIG_SMP
#error "I-pipe/blackfin: SMP not implemented"

2
arch/blackfin/include/asm/pda.h
View File

@ -64,8 +64,6 @@ struct blackfin_pda { /* Per-processor Data Area */
extern struct blackfin_pda cpu_pda[];
void reserve_pda(void);
#endif /* __ASSEMBLY__ */
#endif /* _ASM_BLACKFIN_PDA_H */

4
arch/blackfin/include/asm/processor.h
View File

@ -131,8 +131,8 @@ unsigned long get_wchan(struct task_struct *p);
/* Get the Silicon Revision of the chip */
static inline uint32_t __pure bfin_revid(void)
{
/* stored in the upper 4 bits */
uint32_t revid = bfin_read_CHIPID() >> 28;
/* Always use CHIPID, to work around ANOMALY_05000234 */
uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28;
#ifdef CONFIG_BF52x
/* ANOMALY_05000357

1
arch/blackfin/include/asm/time.h
View File

@ -37,4 +37,5 @@ extern unsigned long long __bfin_cycles_off;
extern unsigned int __bfin_cycles_mod;
#endif
extern void __init setup_core_timer(void);
#endif

32
arch/blackfin/include/asm/uaccess.h
View File

@ -59,12 +59,8 @@ static inline int is_in_rom(unsigned long addr)
#ifndef CONFIG_ACCESS_CHECK
static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
#else
#ifdef CONFIG_ACCESS_OK_L1
extern int _access_ok(unsigned long addr, unsigned long size)__attribute__((l1_text));
#else
extern int _access_ok(unsigned long addr, unsigned long size);
#endif
#endif
/*
* The exception table consists of pairs of addresses: the first is the
@ -83,9 +79,6 @@ struct exception_table_entry {
unsigned long insn, fixup;
};
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
/*
* These are the main single-value transfer routines. They automatically
* use the right size if we just have the right pointer type.
@ -233,16 +226,29 @@ strncpy_from_user(char *dst, const char *src, long count)
}
/*
* Return the size of a string (including the ending 0)
* Get the size of a string in user space.
* src: The string to measure
* n: The maximum valid length
*
* Return 0 on exception, a value greater than N if too long
* Get the size of a NUL-terminated string in user space.
*
* Returns the size of the string INCLUDING the terminating NUL.
* On exception, returns 0.
* If the string is too long, returns a value greater than n.
*/
static inline long strnlen_user(const char *src, long n)
static inline long __must_check strnlen_user(const char *src, long n)
{
return (strlen(src) + 1);
if (!access_ok(VERIFY_READ, src, 1))
return 0;
return strnlen(src, n) + 1;
}
#define strlen_user(str) strnlen_user(str, 32767)
static inline long __must_check strlen_user(const char *src)
{
if (!access_ok(VERIFY_READ, src, 1))
return 0;
return strlen(src) + 1;
}
/*
* Zero Userspace
@ -251,6 +257,8 @@ static inline long strnlen_user(const char *src, long n)
static inline unsigned long __must_check
__clear_user(void *to, unsigned long n)
{
if (!access_ok(VERIFY_WRITE, to, n))
return n;
memset(to, 0, n);
return 0;
}

86
arch/blackfin/kernel/bfin_dma_5xx.c
View File

@ -20,6 +20,11 @@
#include <asm/dma.h>
#include <asm/uaccess.h>
/*
* To make sure we work around 05000119 - we always check DMA_DONE bit,
* never the DMA_RUN bit
*/
struct dma_channel dma_ch[MAX_DMA_CHANNELS];
EXPORT_SYMBOL(dma_ch);
@ -232,6 +237,87 @@ void blackfin_dma_resume(void)
void __init blackfin_dma_early_init(void)
{
bfin_write_MDMA_S0_CONFIG(0);
bfin_write_MDMA_S1_CONFIG(0);
}
void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
{
unsigned long dst = (unsigned long)pdst;
unsigned long src = (unsigned long)psrc;
struct dma_register *dst_ch, *src_ch;
/* We assume that everything is 4 byte aligned, so include
* a basic sanity check
*/
BUG_ON(dst % 4);
BUG_ON(src % 4);
BUG_ON(size % 4);
/* Force a sync in case a previous config reset on this channel
* occurred. This is needed so subsequent writes to DMA registers
* are not spuriously lost/corrupted.
*/
__builtin_bfin_ssync();
src_ch = 0;
/* Find an avalible memDMA channel */
while (1) {
if (!src_ch || src_ch == (struct dma_register *)MDMA_S1_NEXT_DESC_PTR) {
dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
} else {
dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
}
if (!bfin_read16(&src_ch->cfg)) {
break;
} else {
if (bfin_read16(&src_ch->irq_status) & DMA_DONE)
bfin_write16(&src_ch->cfg, 0);
}
}
/* Destination */
bfin_write32(&dst_ch->start_addr, dst);
bfin_write16(&dst_ch->x_count, size >> 2);
bfin_write16(&dst_ch->x_modify, 1 << 2);
bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
/* Source */
bfin_write32(&src_ch->start_addr, src);
bfin_write16(&src_ch->x_count, size >> 2);
bfin_write16(&src_ch->x_modify, 1 << 2);
bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR);
/* Enable */
bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32);
bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32);
/* Since we are atomic now, don't use the workaround ssync */
__builtin_bfin_ssync();
}
void __init early_dma_memcpy_done(void)
{
while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) ||
(bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE)))
continue;
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR);
/*
* Now that DMA is done, we would normally flush cache, but
* i/d cache isn't running this early, so we don't bother,
* and just clear out the DMA channel for next time
*/
bfin_write_MDMA_S0_CONFIG(0);
bfin_write_MDMA_S1_CONFIG(0);
bfin_write_MDMA_D0_CONFIG(0);
bfin_write_MDMA_D1_CONFIG(0);
__builtin_bfin_ssync();
}
/**

18
arch/blackfin/kernel/bfin_gpio.c
View File

@ -313,15 +313,6 @@ inline void portmux_setup(unsigned short per)
# define portmux_setup(...) do { } while (0)
#endif
static int __init bfin_gpio_init(void)
{
printk(KERN_INFO "Blackfin GPIO Controller\n");
return 0;
}
arch_initcall(bfin_gpio_init);
#ifndef CONFIG_BF54x
/***********************************************************
*
@ -1021,15 +1012,6 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
local_irq_save_hw(flags);
if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
if (system_state == SYSTEM_BOOTING)
dump_stack();
printk(KERN_ERR
"bfin-gpio: GPIO %d is already reserved as gpio-irq !\n",
gpio);
local_irq_restore_hw(flags);
return -EBUSY;
}
if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
if (system_state == SYSTEM_BOOTING)
dump_stack();

1
arch/blackfin/kernel/bfin_ksyms.c
View File

@ -16,7 +16,6 @@ EXPORT_SYMBOL(bfin_return_from_exception);
/* All the Blackfin cache functions: mach-common/cache.S */
EXPORT_SYMBOL(blackfin_dcache_invalidate_range);
EXPORT_SYMBOL(blackfin_icache_dcache_flush_range);
EXPORT_SYMBOL(blackfin_icache_flush_range);
EXPORT_SYMBOL(blackfin_dcache_flush_range);
EXPORT_SYMBOL(blackfin_dflush_page);

9
arch/blackfin/kernel/cplb-mpu/cacheinit.c
View File

@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
}
ctrl = bfin_read_DMEM_CONTROL();
ctrl |= DMEM_CNTR;
/*
* Anomaly notes:
* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
* register, so that the port preferences for DAG0 and DAG1 are set
* to port B
*/
ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
bfin_write_DMEM_CONTROL(ctrl);
SSYNC();
}

2
arch/blackfin/kernel/cplb-mpu/cplbinit.c
View File

@ -64,7 +64,7 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
icplb_tbl[cpu][i_i].addr = 0;
icplb_tbl[cpu][i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
/* Cover kernel memory with 4M pages. */
addr = 0;

9
arch/blackfin/kernel/cplb-nompu/cacheinit.c
View File

@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
}
ctrl = bfin_read_DMEM_CONTROL();
ctrl |= DMEM_CNTR;
/*
* Anomaly notes:
* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
* register, so that the port preferences for DAG0 and DAG1 are set
* to port B
*/
ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
bfin_write_DMEM_CONTROL(ctrl);
SSYNC();
}

16
arch/blackfin/kernel/early_printk.c
View File

@ -178,25 +178,15 @@ int __init setup_early_printk(char *buf)
asmlinkage void __init init_early_exception_vectors(void)
{
u32 evt;
SSYNC();
/* cannot program in software:
* evt0 - emulation (jtag)
* evt1 - reset
*/
bfin_write_EVT2(early_trap);
bfin_write_EVT3(early_trap);
bfin_write_EVT5(early_trap);
bfin_write_EVT6(early_trap);
bfin_write_EVT7(early_trap);
bfin_write_EVT8(early_trap);
bfin_write_EVT9(early_trap);
bfin_write_EVT10(early_trap);
bfin_write_EVT11(early_trap);
bfin_write_EVT12(early_trap);
bfin_write_EVT13(early_trap);
bfin_write_EVT14(early_trap);
bfin_write_EVT15(early_trap);
for (evt = EVT2; evt <= EVT15; evt += 4)
bfin_write32(evt, early_trap);
CSYNC();
/* Set all the return from interrupt, exception, NMI to a known place

30
arch/blackfin/kernel/gptimers.c
View File

@ -189,10 +189,10 @@ void set_gptimer_status(int group, uint32_t value)
}
EXPORT_SYMBOL(set_gptimer_status);
uint16_t get_gptimer_intr(int timer_id)
int get_gptimer_intr(int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return (group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]) ? 1 : 0;
return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_intr);
@ -203,10 +203,10 @@ void clear_gptimer_intr(int timer_id)
}
EXPORT_SYMBOL(clear_gptimer_intr);
uint16_t get_gptimer_over(int timer_id)
int get_gptimer_over(int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return (group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]) ? 1 : 0;
return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_over);
@ -217,6 +217,13 @@ void clear_gptimer_over(int timer_id)
}
EXPORT_SYMBOL(clear_gptimer_over);
int get_gptimer_run(int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_run);
void set_gptimer_config(int timer_id, uint16_t config)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
@ -244,7 +251,7 @@ void enable_gptimers(uint16_t mask)
}
EXPORT_SYMBOL(enable_gptimers);
void disable_gptimers(uint16_t mask)
static void _disable_gptimers(uint16_t mask)
{
int i;
uint16_t m = mask;
@ -253,6 +260,12 @@ void disable_gptimers(uint16_t mask)
group_regs[i]->disable = m & 0xFF;
m >>= 8;
}
}
void disable_gptimers(uint16_t mask)
{
int i;
_disable_gptimers(mask);
for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
if (mask & (1 << i))
group_regs[BFIN_TIMER_OCTET(i)]->status |= trun_mask[i];
@ -260,6 +273,13 @@ void disable_gptimers(uint16_t mask)
}
EXPORT_SYMBOL(disable_gptimers);
void disable_gptimers_sync(uint16_t mask)
{
_disable_gptimers(mask);
SSYNC();
}
EXPORT_SYMBOL(disable_gptimers_sync);
void set_gptimer_pulse_hi(int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);

9
arch/blackfin/kernel/ipipe.c
View File

@ -167,7 +167,7 @@ int __ipipe_check_root(void)
void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
{
struct irq_desc *desc = irq_to_desc(irq);
int prio = desc->ic_prio;
int prio = __ipipe_get_irq_priority(irq);
desc->depth = 0;
if (ipd != &ipipe_root &&
@ -178,8 +178,7 @@ EXPORT_SYMBOL(__ipipe_enable_irqdesc);
void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
{
struct irq_desc *desc = irq_to_desc(irq);
int prio = desc->ic_prio;
int prio = __ipipe_get_irq_priority(irq);
if (ipd != &ipipe_root &&
atomic_dec_and_test(&__ipipe_irq_lvdepth[prio]))
@ -310,12 +309,16 @@ int ipipe_trigger_irq(unsigned irq)
asmlinkage void __ipipe_sync_root(void)
{
void (*irq_tail_hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
unsigned long flags;
BUG_ON(irqs_disabled());
local_irq_save_hw(flags);
if (irq_tail_hook)
irq_tail_hook();
clear_thread_flag(TIF_IRQ_SYNC);
if (ipipe_root_cpudom_var(irqpend_himask) != 0)

2
arch/blackfin/kernel/irqchip.c
View File

@ -59,12 +59,14 @@ static struct irq_chip bad_chip = {
.unmask = dummy_mask_unmask_irq,
};
static int bad_stats;
static struct irq_desc bad_irq_desc = {
.status = IRQ_DISABLED,
.chip = &bad_chip,
.handle_irq = handle_bad_irq,
.depth = 1,
.lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock),
.kstat_irqs = &bad_stats,
#ifdef CONFIG_SMP
.affinity = CPU_MASK_ALL
#endif

60
arch/blackfin/kernel/kgdb.c
View File

@ -466,7 +466,7 @@ static int validate_memory_access_address(unsigned long addr, int size)
int cpu = raw_smp_processor_id();
if (size < 0)
return EFAULT;
return -EFAULT;
if (addr >= 0x1000 && (addr + size) <= physical_mem_end)
return 0;
if (addr >= SYSMMR_BASE)
@ -498,7 +498,7 @@ static int validate_memory_access_address(unsigned long addr, int size)
if (IN_MEM(addr, size, L2_START, L2_LENGTH))
return 0;
return EFAULT;
return -EFAULT;
}
/*
@ -508,14 +508,15 @@ static int validate_memory_access_address(unsigned long addr, int size)
int kgdb_mem2hex(char *mem, char *buf, int count)
{
char *tmp;
int err = 0;
int err;
unsigned char *pch;
unsigned short mmr16;
unsigned long mmr32;
int cpu = raw_smp_processor_id();
if (validate_memory_access_address((unsigned long)mem, count))
return EFAULT;
err = validate_memory_access_address((unsigned long)mem, count);
if (err)
return err;
/*
* We use the upper half of buf as an intermediate buffer for the
@ -533,7 +534,7 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
*tmp++ = *pch++;
tmp -= 2;
} else
err = EFAULT;
err = -EFAULT;
break;
case 4:
if ((unsigned int)mem % 4 == 0) {
@ -545,10 +546,10 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
*tmp++ = *pch++;
tmp -= 4;
} else
err = EFAULT;
err = -EFAULT;
break;
default:
err = EFAULT;
err = -EFAULT;
}
} else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
#ifdef CONFIG_SMP
@ -557,7 +558,7 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
) {
/* access L1 instruction SRAM*/
if (dma_memcpy(tmp, mem, count) == NULL)
err = EFAULT;
err = -EFAULT;
} else
err = probe_kernel_read(tmp, mem, count);
@ -585,24 +586,24 @@ int kgdb_ebin2mem(char *buf, char *mem, int count)
char *tmp_new;
unsigned short *mmr16;
unsigned long *mmr32;
int err = 0;
int size = 0;
int err;
int size;
int cpu = raw_smp_processor_id();
tmp_old = tmp_new = buf;
while (count-- > 0) {
for (size = 0; size < count; ++size) {
if (*tmp_old == 0x7d)
*tmp_new = *(++tmp_old) ^ 0x20;
else
*tmp_new = *tmp_old;
tmp_new++;
tmp_old++;
size++;
}
if (validate_memory_access_address((unsigned long)mem, size))
return EFAULT;
err = validate_memory_access_address((unsigned long)mem, size);
if (err)
return err;
if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
switch (size) {
@ -611,17 +612,17 @@ int kgdb_ebin2mem(char *buf, char *mem, int count)
mmr16 = (unsigned short *)buf;
*(unsigned short *)mem = *mmr16;
} else
return EFAULT;
err = -EFAULT;
break;
case 4:
if ((unsigned int)mem % 4 == 0) {
mmr32 = (unsigned long *)buf;
*(unsigned long *)mem = *mmr32;
} else
return EFAULT;
err = -EFAULT;
break;
default:
return EFAULT;
err = -EFAULT;
}
} else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
#ifdef CONFIG_SMP
@ -630,7 +631,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count)
) {
/* access L1 instruction SRAM */
if (dma_memcpy(mem, buf, size) == NULL)
err = EFAULT;
err = -EFAULT;
} else
err = probe_kernel_write(mem, buf, size);
@ -648,10 +649,12 @@ int kgdb_hex2mem(char *buf, char *mem, int count)
char *tmp_hex;
unsigned short *mmr16;
unsigned long *mmr32;
int err;
int cpu = raw_smp_processor_id();
if (validate_memory_access_address((unsigned long)mem, count))
return EFAULT;
err = validate_memory_access_address((unsigned long)mem, count);
if (err)
return err;
/*
* We use the upper half of buf as an intermediate buffer for the
@ -673,17 +676,17 @@ int kgdb_hex2mem(char *buf, char *mem, int count)
mmr16 = (unsigned short *)tmp_raw;
*(unsigned short *)mem = *mmr16;
} else
return EFAULT;
err = -EFAULT;
break;
case 4:
if ((unsigned int)mem % 4 == 0) {
mmr32 = (unsigned long *)tmp_raw;
*(unsigned long *)mem = *mmr32;
} else
return EFAULT;
err = -EFAULT;
break;
default:
return EFAULT;
err = -EFAULT;
}
} else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
#ifdef CONFIG_SMP
@ -692,10 +695,11 @@ int kgdb_hex2mem(char *buf, char *mem, int count)
) {
/* access L1 instruction SRAM */
if (dma_memcpy(mem, tmp_raw, count) == NULL)
return EFAULT;
err = -EFAULT;
} else
return probe_kernel_write(mem, tmp_raw, count);
return 0;
err = probe_kernel_write(mem, tmp_raw, count);
return err;
}
int kgdb_validate_break_address(unsigned long addr)
@ -715,7 +719,7 @@ int kgdb_validate_break_address(unsigned long addr)
if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
return 0;
return EFAULT;
return -EFAULT;
}
int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)

22
arch/blackfin/kernel/module.c
View File

@ -201,8 +201,8 @@ apply_relocate(Elf_Shdr * sechdrs, const char *strtab,
/* Arithmetic relocations are handled. */
/* We do not expect LSETUP to be split and hence is not */
/* handled. */
/* R_byte and R_byte2 are also not handled as the gas */
/* does not generate it. */
/* R_BFIN_BYTE and R_BFIN_BYTE2 are also not handled as the */
/* gas does not generate it. */
/*************************************************************************/
int
apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
@ -243,8 +243,8 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
#endif
switch (ELF32_R_TYPE(rel[i].r_info)) {
case R_pcrel24:
case R_pcrel24_jump_l:
case R_BFIN_PCREL24:
case R_BFIN_PCREL24_JUMP_L:
/* Add the value, subtract its postition */
location16 =
(uint16_t *) (sechdrs[sechdrs[relsec].sh_info].
@ -266,18 +266,18 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
(*location16 & 0xff00) | (value >> 16 & 0x00ff);
*(location16 + 1) = value & 0xffff;
break;
case R_pcrel12_jump:
case R_pcrel12_jump_s:
case R_BFIN_PCREL12_JUMP:
case R_BFIN_PCREL12_JUMP_S:
value -= (uint32_t) location32;
value >>= 1;
*location16 = (value & 0xfff);
break;
case R_pcrel10:
case R_BFIN_PCREL10:
value -= (uint32_t) location32;
value >>= 1;
*location16 = (value & 0x3ff);
break;
case R_luimm16:
case R_BFIN_LUIMM16:
pr_debug("before %x after %x\n", *location16,
(value & 0xffff));
tmp = (value & 0xffff);
@ -286,7 +286,7 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
} else
*location16 = tmp;
break;
case R_huimm16:
case R_BFIN_HUIMM16:
pr_debug("before %x after %x\n", *location16,
((value >> 16) & 0xffff));
tmp = ((value >> 16) & 0xffff);
@ -295,10 +295,10 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
} else
*location16 = tmp;
break;
case R_rimm16:
case R_BFIN_RIMM16:
*location16 = (value & 0xffff);
break;
case R_byte4_data:
case R_BFIN_BYTE4_DATA:
pr_debug("before %x after %x\n", *location32, value);
*location32 = value;
break;

3
arch/blackfin/kernel/process.c
View File

@ -322,6 +322,9 @@ void finish_atomic_sections (struct pt_regs *regs)
}
#if defined(CONFIG_ACCESS_CHECK)
#ifdef CONFIG_ACCESS_OK_L1
__attribute__((l1_text))
#endif
/* Return 1 if access to memory range is OK, 0 otherwise */
int _access_ok(unsigned long addr, unsigned long size)
{

81
arch/blackfin/kernel/setup.c
View File

@ -18,9 +18,12 @@
#include <linux/tty.h>
#include <linux/pfn.h>
#ifdef CONFIG_MTD_UCLINUX
#include <linux/mtd/map.h>
#include <linux/ext2_fs.h>
#include <linux/cramfs_fs.h>
#include <linux/romfs_fs.h>
#endif
#include <asm/cplb.h>
#include <asm/cacheflush.h>
@ -45,6 +48,7 @@ EXPORT_SYMBOL(_ramend);
EXPORT_SYMBOL(reserved_mem_dcache_on);
#ifdef CONFIG_MTD_UCLINUX
extern struct map_info uclinux_ram_map;
unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
unsigned long _ebss;
EXPORT_SYMBOL(memory_mtd_end);
@ -150,40 +154,45 @@ void __init bfin_relocate_l1_mem(void)
unsigned long l1_data_b_length;
unsigned long l2_length;
blackfin_dma_early_init();
l1_code_length = _etext_l1 - _stext_l1;
if (l1_code_length > L1_CODE_LENGTH)
panic("L1 Instruction SRAM Overflow\n");
/* cannot complain as printk is not available as yet.
* But we can continue booting and complain later!
/*
* due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
* we know that everything about l1 text/data is nice and aligned,
* so copy by 4 byte chunks, and don't worry about overlapping
* src/dest.
*
* We can't use the dma_memcpy functions, since they can call
* scheduler functions which might be in L1 :( and core writes
* into L1 instruction cause bad access errors, so we are stuck,
* we are required to use DMA, but can't use the common dma
* functions. We can't use memcpy either - since that might be
* going to be in the relocated L1
*/
/* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
blackfin_dma_early_init();
/* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
l1_code_length = _etext_l1 - _stext_l1;
if (l1_code_length)
early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
/* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */
l1_data_a_length = _sbss_l1 - _sdata_l1;
if (l1_data_a_length > L1_DATA_A_LENGTH)
panic("L1 Data SRAM Bank A Overflow\n");
/* Copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */
dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
if (l1_data_a_length)
early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
/* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */
l1_data_b_length = _sbss_b_l1 - _sdata_b_l1;
if (l1_data_b_length > L1_DATA_B_LENGTH)
panic("L1 Data SRAM Bank B Overflow\n");
/* Copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */
dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
if (l1_data_b_length)
early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
l1_data_a_length, l1_data_b_length);
early_dma_memcpy_done();
/* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */
if (L2_LENGTH != 0) {
l2_length = _sbss_l2 - _stext_l2;
if (l2_length > L2_LENGTH)
panic("L2 SRAM Overflow\n");
/* Copy _stext_l2 to _edata_l2 to L2 SRAM */
dma_memcpy(_stext_l2, _l2_lma_start, l2_length);
if (l2_length)
memcpy(_stext_l2, _l2_lma_start, l2_length);
}
}
@ -472,7 +481,7 @@ static __init void memory_setup(void)
if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
console_init();
panic("DMA region exceeds memory limit: %lu.\n",
panic("DMA region exceeds memory limit: %lu.",
_ramend - _ramstart);
}
memory_end = _ramend - DMA_UNCACHED_REGION;
@ -526,14 +535,13 @@ static __init void memory_setup(void)
if (mtd_size == 0) {
console_init();
panic("Don't boot kernel without rootfs attached.\n");
panic("Don't boot kernel without rootfs attached.");
}
/* Relocate MTD image to the top of memory after the uncached memory area */
dma_memcpy((char *)memory_end, _end, mtd_size);
memory_mtd_start = memory_end;
_ebss = memory_mtd_start; /* define _ebss for compatible */
uclinux_ram_map.phys = memory_mtd_start = memory_end;
uclinux_ram_map.size = mtd_size;
dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
#endif /* CONFIG_MTD_UCLINUX */
#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
@ -796,10 +804,8 @@ void __init setup_arch(char **cmdline_p)
cclk = get_cclk();
sclk = get_sclk();
#if !defined(CONFIG_BFIN_KERNEL_CLOCK)
if (ANOMALY_05000273 && cclk == sclk)
panic("ANOMALY 05000273, SCLK can not be same as CCLK");
#endif
if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
#ifdef BF561_FAMILY
if (ANOMALY_05000266) {
@ -881,7 +887,7 @@ void __init setup_arch(char **cmdline_p)
printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
bfin_compiled_revid(), bfin_revid());
if (bfin_compiled_revid() > bfin_revid())
panic("Error: you are missing anomaly workarounds for this rev\n");
panic("Error: you are missing anomaly workarounds for this rev");
}
}
if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
@ -891,16 +897,13 @@ void __init setup_arch(char **cmdline_p)
/* We can't run on BF548-0.1 due to ANOMALY 05000448 */
if (bfin_cpuid() == 0x27de && bfin_revid() == 1)
panic("You can't run on this processor due to 05000448\n");
panic("You can't run on this processor due to 05000448");
printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
cclk / 1000000, sclk / 1000000);
if (ANOMALY_05000273 && (cclk >> 1) <= sclk)
printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
setup_bootmem_allocator();
paging_init();

5
arch/blackfin/kernel/sys_bfin.c
View File

@ -78,11 +78,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
return do_mmap2(addr, len, prot, flags, fd, pgoff);
}
asmlinkage int sys_getpagesize(void)
{
return PAGE_SIZE;
}
asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags)
{
return sram_alloc_with_lsl(size, flags);

230
arch/blackfin/kernel/time-ts.c
View File

@ -20,8 +20,9 @@
#include <asm/blackfin.h>
#include <asm/time.h>
#include <asm/gptimers.h>
#ifdef CONFIG_CYCLES_CLOCKSOURCE
#if defined(CONFIG_CYCLES_CLOCKSOURCE)
/* Accelerators for sched_clock()
* convert from cycles(64bits) => nanoseconds (64bits)
@ -58,15 +59,15 @@ static inline unsigned long long cycles_2_ns(cycle_t cyc)
return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
}
static cycle_t read_cycles(struct clocksource *cs)
static cycle_t bfin_read_cycles(struct clocksource *cs)
{
return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
}
static struct clocksource clocksource_bfin = {
.name = "bfin_cycles",
static struct clocksource bfin_cs_cycles = {
.name = "bfin_cs_cycles",
.rating = 350,
.read = read_cycles,
.read = bfin_read_cycles,
.mask = CLOCKSOURCE_MASK(64),
.shift = 22,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
@ -74,53 +75,198 @@ static struct clocksource clocksource_bfin = {
unsigned long long sched_clock(void)
{
return cycles_2_ns(read_cycles(&clocksource_bfin));
return cycles_2_ns(bfin_read_cycles(&bfin_cs_cycles));
}
static int __init bfin_clocksource_init(void)
static int __init bfin_cs_cycles_init(void)
{
set_cyc2ns_scale(get_cclk() / 1000);
clocksource_bfin.mult = clocksource_hz2mult(get_cclk(), clocksource_bfin.shift);
bfin_cs_cycles.mult = \
clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);
if (clocksource_register(&clocksource_bfin))
if (clocksource_register(&bfin_cs_cycles))
panic("failed to register clocksource");
return 0;
}
#else
# define bfin_clocksource_init()
# define bfin_cs_cycles_init()
#endif
#ifdef CONFIG_GPTMR0_CLOCKSOURCE
void __init setup_gptimer0(void)
{
disable_gptimers(TIMER0bit);
set_gptimer_config(TIMER0_id, \
TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
set_gptimer_period(TIMER0_id, -1);
set_gptimer_pwidth(TIMER0_id, -2);
SSYNC();
enable_gptimers(TIMER0bit);
}
static cycle_t bfin_read_gptimer0(void)
{
return bfin_read_TIMER0_COUNTER();
}
static struct clocksource bfin_cs_gptimer0 = {
.name = "bfin_cs_gptimer0",
.rating = 400,
.read = bfin_read_gptimer0,
.mask = CLOCKSOURCE_MASK(32),
.shift = 22,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static int __init bfin_cs_gptimer0_init(void)
{
setup_gptimer0();
bfin_cs_gptimer0.mult = \
clocksource_hz2mult(get_sclk(), bfin_cs_gptimer0.shift);
if (clocksource_register(&bfin_cs_gptimer0))
panic("failed to register clocksource");
return 0;
}
#else
# define bfin_cs_gptimer0_init()
#endif
#ifdef CONFIG_CORE_TIMER_IRQ_L1
__attribute__((l1_text))
#endif
irqreturn_t timer_interrupt(int irq, void *dev_id);
static int bfin_timer_set_next_event(unsigned long, \
struct clock_event_device *);
static void bfin_timer_set_mode(enum clock_event_mode, \
struct clock_event_device *);
static struct clock_event_device clockevent_bfin = {
#if defined(CONFIG_TICKSOURCE_GPTMR0)
.name = "bfin_gptimer0",
.rating = 300,
.irq = IRQ_TIMER0,
#else
.name = "bfin_core_timer",
.rating = 350,
.irq = IRQ_CORETMR,
#endif
.shift = 32,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = bfin_timer_set_next_event,
.set_mode = bfin_timer_set_mode,
};
static struct irqaction bfin_timer_irq = {
#if defined(CONFIG_TICKSOURCE_GPTMR0)
.name = "Blackfin GPTimer0",
#else
.name = "Blackfin CoreTimer",
#endif
.flags = IRQF_DISABLED | IRQF_TIMER | \
IRQF_IRQPOLL | IRQF_PERCPU,
.handler = timer_interrupt,
.dev_id = &clockevent_bfin,
};
#if defined(CONFIG_TICKSOURCE_GPTMR0)
static int bfin_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
bfin_write_TCOUNT(cycles);
CSYNC();
disable_gptimers(TIMER0bit);
/* it starts counting three SCLK cycles after the TIMENx bit is set */
set_gptimer_pwidth(TIMER0_id, cycles - 3);
enable_gptimers(TIMER0bit);
return 0;
}
static void bfin_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
struct clock_event_device *evt)
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC: {
set_gptimer_config(TIMER0_id, \
TIMER_OUT_DIS | TIMER_IRQ_ENA | \
TIMER_PERIOD_CNT | TIMER_MODE_PWM);
set_gptimer_period(TIMER0_id, get_sclk() / HZ);
set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
enable_gptimers(TIMER0bit);
break;
}
case CLOCK_EVT_MODE_ONESHOT:
disable_gptimers(TIMER0bit);
set_gptimer_config(TIMER0_id, \
TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
set_gptimer_period(TIMER0_id, 0);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
disable_gptimers(TIMER0bit);
break;
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static void bfin_timer_ack(void)
{
set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0);
}
static void __init bfin_timer_init(void)
{
disable_gptimers(TIMER0bit);
}
static unsigned long __init bfin_clockevent_check(void)
{
setup_irq(IRQ_TIMER0, &bfin_timer_irq);
return get_sclk();
}
#else /* CONFIG_TICKSOURCE_CORETMR */
static int bfin_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
bfin_write_TCNTL(TMPWR);
CSYNC();
bfin_write_TCOUNT(cycles);
CSYNC();
bfin_write_TCNTL(TMPWR | TMREN);
return 0;
}
static void bfin_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC: {
unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
bfin_write_TCNTL(TMPWR);
bfin_write_TSCALE(TIME_SCALE - 1);
CSYNC();
bfin_write_TSCALE(TIME_SCALE - 1);
bfin_write_TPERIOD(tcount);
bfin_write_TCOUNT(tcount);
bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
CSYNC();
bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
break;
}
case CLOCK_EVT_MODE_ONESHOT:
bfin_write_TSCALE(TIME_SCALE - 1);
bfin_write_TCOUNT(0);
bfin_write_TCNTL(TMPWR | TMREN);
bfin_write_TCNTL(TMPWR);
CSYNC();
bfin_write_TSCALE(TIME_SCALE - 1);
bfin_write_TPERIOD(0);
bfin_write_TCOUNT(0);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
@ -132,6 +278,10 @@ static void bfin_timer_set_mode(enum clock_event_mode mode,
}
}
static void bfin_timer_ack(void)
{
}
static void __init bfin_timer_init(void)
{
/* power up the timer, but don't enable it just yet */
@ -145,38 +295,32 @@ static void __init bfin_timer_init(void)
bfin_write_TPERIOD(0);
bfin_write_TCOUNT(0);
/* now enable the timer */
CSYNC();
}
static unsigned long __init bfin_clockevent_check(void)
{
setup_irq(IRQ_CORETMR, &bfin_timer_irq);
return get_cclk() / TIME_SCALE;
}
void __init setup_core_timer(void)
{
bfin_timer_init();
bfin_timer_set_mode(CLOCK_EVT_MODE_PERIODIC, NULL);
}
#endif /* CONFIG_TICKSOURCE_GPTMR0 */
/*
* timer_interrupt() needs to keep up the real-time clock,
* as well as call the "do_timer()" routine every clocktick
*/
#ifdef CONFIG_CORE_TIMER_IRQ_L1
__attribute__((l1_text))
#endif
irqreturn_t timer_interrupt(int irq, void *dev_id);
static struct clock_event_device clockevent_bfin = {
.name = "bfin_core_timer",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.set_next_event = bfin_timer_set_next_event,
.set_mode = bfin_timer_set_mode,
};
static struct irqaction bfin_timer_irq = {
.name = "Blackfin Core Timer",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = timer_interrupt,
.dev_id = &clockevent_bfin,
};
irqreturn_t timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
smp_mb();
evt->event_handler(evt);
bfin_timer_ack();
return IRQ_HANDLED;
}
@ -184,9 +328,8 @@ static int __init bfin_clockevent_init(void)
{
unsigned long timer_clk;
timer_clk = get_cclk() / TIME_SCALE;
timer_clk = bfin_clockevent_check();
setup_irq(IRQ_CORETMR, &bfin_timer_irq);
bfin_timer_init();
clockevent_bfin.mult = div_sc(timer_clk, NSEC_PER_SEC, clockevent_bfin.shift);
@ -218,6 +361,7 @@ void __init time_init(void)
xtime.tv_nsec = 0;
set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
bfin_clocksource_init();
bfin_cs_cycles_init();
bfin_cs_gptimer0_init();
bfin_clockevent_init();
}

55
arch/blackfin/kernel/time.c
View File

@ -24,14 +24,10 @@
static struct irqaction bfin_timer_irq = {
.name = "Blackfin Timer Tick",
#ifdef CONFIG_IRQ_PER_CPU
.flags = IRQF_DISABLED | IRQF_PERCPU,
#else
.flags = IRQF_DISABLED
#endif
};
#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
#if defined(CONFIG_IPIPE)
void __init setup_system_timer0(void)
{
/* Power down the core timer, just to play safe. */
@ -74,7 +70,7 @@ void __init setup_core_timer(void)
static void __init
time_sched_init(irqreturn_t(*timer_routine) (int, void *))
{
#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
#if defined(CONFIG_IPIPE)
setup_system_timer0();
bfin_timer_irq.handler = timer_routine;
setup_irq(IRQ_TIMER0, &bfin_timer_irq);
@ -94,7 +90,7 @@ static unsigned long gettimeoffset(void)
unsigned long offset;
unsigned long clocks_per_jiffy;
#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
#if defined(CONFIG_IPIPE)
clocks_per_jiffy = bfin_read_TIMER0_PERIOD();
offset = bfin_read_TIMER0_COUNTER() / \
(((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
@ -133,36 +129,25 @@ irqreturn_t timer_interrupt(int irq, void *dummy)
static long last_rtc_update;
write_seqlock(&xtime_lock);
#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE)
/*
* TIMIL0 is latched in __ipipe_grab_irq() when the I-Pipe is
* enabled.
*/
if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) {
#endif
do_timer(1);
do_timer(1);
/*
* If we have an externally synchronized Linux clock, then update
* CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
* called as close as possible to 500 ms before the new second starts.
*/
if (ntp_synced() &&
xtime.tv_sec > last_rtc_update + 660 &&
(xtime.tv_nsec / NSEC_PER_USEC) >=
500000 - ((unsigned)TICK_SIZE) / 2
&& (xtime.tv_nsec / NSEC_PER_USEC) <=
500000 + ((unsigned)TICK_SIZE) / 2) {
if (set_rtc_mmss(xtime.tv_sec) == 0)
last_rtc_update = xtime.tv_sec;
else
/* Do it again in 60s. */
last_rtc_update = xtime.tv_sec - 600;
}
#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE)
set_gptimer_status(0, TIMER_STATUS_TIMIL0);
/*
* If we have an externally synchronized Linux clock, then update
* CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
* called as close as possible to 500 ms before the new second starts.
*/
if (ntp_synced() &&
xtime.tv_sec > last_rtc_update + 660 &&
(xtime.tv_nsec / NSEC_PER_USEC) >=
500000 - ((unsigned)TICK_SIZE) / 2
&& (xtime.tv_nsec / NSEC_PER_USEC) <=
500000 + ((unsigned)TICK_SIZE) / 2) {
if (set_rtc_mmss(xtime.tv_sec) == 0)
last_rtc_update = xtime.tv_sec;
else
/* Do it again in 60s. */
last_rtc_update = xtime.tv_sec - 600;
}
#endif
write_sequnlock(&xtime_lock);
#ifdef CONFIG_IPIPE

52
arch/blackfin/kernel/traps.c
View File

@ -68,6 +68,13 @@
({ if (0) printk(fmt, ##arg); 0; })
#endif
#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE)
u32 last_seqstat;
#ifdef CONFIG_DEBUG_MMRS_MODULE
EXPORT_SYMBOL(last_seqstat);
#endif
#endif
/* Initiate the event table handler */
void __init trap_init(void)
{
@ -79,7 +86,6 @@ void __init trap_init(void)
static void decode_address(char *buf, unsigned long address)
{
#ifdef CONFIG_DEBUG_VERBOSE
struct vm_list_struct *vml;
struct task_struct *p;
struct mm_struct *mm;
unsigned long flags, offset;
@ -196,6 +202,11 @@ done:
asmlinkage void double_fault_c(struct pt_regs *fp)
{
#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
int j;
trace_buffer_save(j);
#endif
console_verbose();
oops_in_progress = 1;
#ifdef CONFIG_DEBUG_VERBOSE
@ -220,9 +231,10 @@ asmlinkage void double_fault_c(struct pt_regs *fp)
dump_bfin_process(fp);
dump_bfin_mem(fp);
show_regs(fp);
dump_bfin_trace_buffer();
}
#endif
panic("Double Fault - unrecoverable event\n");
panic("Double Fault - unrecoverable event");
}
@ -239,6 +251,9 @@ asmlinkage void trap_c(struct pt_regs *fp)
unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE;
trace_buffer_save(j);
#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE)
last_seqstat = (u32)fp->seqstat;
#endif
/* Important - be very careful dereferncing pointers - will lead to
* double faults if the stack has become corrupt
@ -588,6 +603,9 @@ asmlinkage void trap_c(struct pt_regs *fp)
force_sig_info(sig, &info, current);
}
if (ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8))
fp->pc = SAFE_USER_INSTRUCTION;
trace_buffer_restore(j);
return;
}
@ -832,6 +850,11 @@ void show_stack(struct task_struct *task, unsigned long *stack)
decode_address(buf, (unsigned int)stack);
printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) {
printk(KERN_NOTICE "Invalid stack pointer\n");
return;
}
/* First thing is to look for a frame pointer */
for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) {
if (*addr & 0x1)
@ -1066,6 +1089,29 @@ void show_regs(struct pt_regs *fp)
unsigned int cpu = smp_processor_id();
unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
verbose_printk(KERN_NOTICE "\n");
if (CPUID != bfin_cpuid())
verbose_printk(KERN_NOTICE "Compiled for cpu family 0x%04x (Rev %d), "
"but running on:0x%04x (Rev %d)\n",
CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
verbose_printk(KERN_NOTICE "ADSP-%s-0.%d",
CPU, bfin_compiled_revid());
if (bfin_compiled_revid() != bfin_revid())
verbose_printk("(Detected 0.%d)", bfin_revid());
verbose_printk(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
get_cclk()/1000000, get_sclk()/1000000,
#ifdef CONFIG_MPU
"mpu on"
#else
"mpu off"
#endif
);
verbose_printk(KERN_NOTICE "%s", linux_banner);
verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted());
verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
(long)fp->seqstat, fp->ipend, fp->syscfg);
@ -1246,5 +1292,5 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
dump_bfin_mem(fp);
show_regs(fp);
dump_stack();
panic("Unrecoverable event\n");
panic("Unrecoverable event");
}

5
arch/blackfin/kernel/vmlinux.lds.S
View File

@ -50,7 +50,9 @@ SECTIONS
_text = .;
__stext = .;
TEXT_TEXT
#ifndef CONFIG_SCHEDULE_L1
SCHED_TEXT
#endif
LOCK_TEXT
KPROBES_TEXT
*(.text.*)
@ -180,6 +182,9 @@ SECTIONS
. = ALIGN(4);
__stext_l1 = .;
*(.l1.text)
#ifdef CONFIG_SCHEDULE_L1
SCHED_TEXT
#endif
. = ALIGN(4);
__etext_l1 = .;
}

1
arch/blackfin/mach-bf518/Kconfig
View File

@ -156,6 +156,7 @@ config IRQ_PORTH_INTB
default 11
config IRQ_TIMER0
int "IRQ_TIMER0"
default 7 if TICKSOURCE_GPTMR0
default 8
config IRQ_TIMER1
int "IRQ_TIMER1"

19
arch/blackfin/mach-bf518/boards/ezbrd.c
View File

@ -82,7 +82,11 @@ static struct physmap_flash_data ezbrd_flash_data = {
static struct resource ezbrd_flash_resource = {
.start = 0x20000000,
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
.end = 0x202fffff,
#else
.end = 0x203fffff,
#endif
.flags = IORESOURCE_MEM,
};
@ -162,8 +166,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -249,8 +253,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
@ -514,7 +518,7 @@ static struct platform_device i2c_bfin_twi_device = {
#endif
static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
},
@ -678,6 +682,11 @@ static int __init ezbrd_init(void)
ARRAY_SIZE(bfin_i2c_board_info));
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
/* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
peripheral_request(P_AMS2, "ParaFlash");
#if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)
peripheral_request(P_AMS3, "ParaFlash");
#endif
return 0;
}

35
arch/blackfin/mach-bf518/include/mach/anomaly.h
View File

@ -6,14 +6,19 @@
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
/* This file should be up to date with:
* - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
*/
/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
#if __SILICON_REVISION__ < 0
# error will not work on BF518 silicon version
#endif
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
@ -47,7 +52,7 @@
#define ANOMALY_05000435 (1)
/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
#define ANOMALY_05000438 (1)
/* Preboot Cannot be Used to Program the PLL_DIV Register */
/* Preboot Cannot be Used to Alter the PLL_DIV Register */
#define ANOMALY_05000439 (1)
/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
#define ANOMALY_05000440 (1)
@ -61,32 +66,56 @@
#define ANOMALY_05000453 (1)
/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
#define ANOMALY_05000455 (1)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000119 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
#define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#endif

6
arch/blackfin/mach-bf518/include/mach/portmux.h
View File

@ -185,6 +185,10 @@
#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1))
/* AMS */
#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1))
#endif /* _MACH_PORTMUX_H_ */

1
arch/blackfin/mach-bf527/Kconfig
View File

@ -170,6 +170,7 @@ config IRQ_PORTH_INTB
default 11
config IRQ_TIMER0
int "IRQ_TIMER0"
default 7 if TICKSOURCE_GPTMR0
default 8
config IRQ_TIMER1
int "IRQ_TIMER1"

10
arch/blackfin/mach-bf527/boards/cm_bf527.c
View File

@ -463,8 +463,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -554,8 +554,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
@ -789,7 +789,7 @@ static struct platform_device i2c_bfin_twi_device = {
#endif
static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
.type = "pcf8574_lcd",

10
arch/blackfin/mach-bf527/boards/ezbrd.c
View File

@ -247,8 +247,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -354,8 +354,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
@ -586,7 +586,7 @@ static struct platform_device i2c_bfin_twi_device = {
#endif
static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
},

28
arch/blackfin/mach-bf527/boards/ezkit.c
View File

@ -485,8 +485,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -509,6 +509,13 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
};
#endif
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
#if defined(CONFIG_PBX)
static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
.ctl_reg = 0x4, /* send zero */
@ -593,8 +600,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
@ -624,6 +631,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &ad9960_spi_chip_info,
},
#endif
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
{
.modalias = "mmc_spi",
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 3,
.controller_data = &mmc_spi_chip_info,
.mode = SPI_MODE_0,
},
#endif
#if defined(CONFIG_PBX)
{
.modalias = "fxs-spi",
@ -836,7 +854,7 @@ static struct platform_device i2c_bfin_twi_device = {
#endif
static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
},

168
arch/blackfin/mach-bf527/include/mach/anomaly.h
View File

@ -6,14 +6,19 @@
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
* - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
* - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List
/* This file should be up to date with:
* - Revision C, 03/13/2009; ADSP-BF526 Blackfin Processor Anomaly List
* - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* We do not support old silicon - sorry */
#if __SILICON_REVISION__ < 0
# error will not work on BF526/BF527 silicon version
#endif
#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
# define ANOMALY_BF526 1
#else
@ -25,158 +30,203 @@
# define ANOMALY_BF527 0
#endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
#define ANOMALY_05000254 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
/* Host DMA Boot Modes Are Not Functional */
#define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
/* USB Calibration Value Is Not Initialized */
#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
/* USB Calibration Value to use */
#define ANOMALY_05000346_value 0xE510
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
/* Security Features Are Not Functional */
#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
#define ANOMALY_05000353 (ANOMALY_BF526)
#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
/* Incorrect Revision Number in DSPID Register */
#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Incorrect Default CSEL Value in PLL_DIV */
#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
/* Authentication Fails To Initiate */
#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
/* Data Read From L3 Memory by USB DMA May be Corrupted */
#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
/* 8-Bit NAND Flash Boot Mode Not Functional */
#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
/* Host Must Not Read Back During Host DMA Boot */
#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Boot from OTP Memory Not Functional */
#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
/* bfrom_SysControl() Firmware Routine Not Functional */
#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
/* Programmable Preboot Settings Not Functional */
#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
/* CRC32 Checksum Support Not Functional */
#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Reset Vector Must Not Be in SDRAM Memory Space */
#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
/* Log Buffer Not Functional */
#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
/* Hook Routine Not Functional */
#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
/* Header Indirect Bit Not Functional */
#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Lockbox SESR Disallows Certain User Interrupts */
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
#define ANOMALY_05000405 (1)
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
#define ANOMALY_05000408 (1)
/* Lockbox firmware leaves MDMA0 channel enabled */
#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Incorrect Default Internal Voltage Regulator Setting */
#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2))
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
/* DEB2_URGENT Bit Not Functional */
#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
#define ANOMALY_05000421 (1)
/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Internal Voltage Regulator Not Trimmed */
#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (1)
/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
#define ANOMALY_05000432 (ANOMALY_BF526)
#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* Preboot Cannot be Used to Alter the PLL_DIV Register */
#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* OTP Write Accesses Not Supported */
#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* The WURESET Bit in the SYSCR Register is not Functional */
#define ANOMALY_05000445 (1)
/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
#define ANOMALY_05000451 (1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
#define ANOMALY_05000456 (1)
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
#define ANOMALY_05000457 (1)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
#define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000450 (0)
#endif

1
arch/blackfin/mach-bf533/Kconfig
View File

@ -59,6 +59,7 @@ config DMA7_UARTTX
default 10
config TIMER0
int "TIMER0"
default 7 if TICKSOURCE_GPTMR0
default 8
config TIMER1
int "TIMER1"

4
arch/blackfin/mach-bf533/boards/H8606.c
View File

@ -173,7 +173,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.ctl_reg = 0x1000,
@ -216,7 +216,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 4, /* actual baudrate is SCLK/(2xspeed_hz) */

4
arch/blackfin/mach-bf533/boards/cm_bf533.c
View File

@ -82,7 +82,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
#endif
/* SPI ADC chip */
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
.bits_per_word = 16,
@ -117,7 +117,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */

4
arch/blackfin/mach-bf533/boards/ezkit.c
View File

@ -118,7 +118,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -154,7 +154,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */

6
arch/blackfin/mach-bf533/boards/stamp.c
View File

@ -192,7 +192,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -237,7 +237,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
@ -448,7 +448,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
.irq = 39,
},
#endif
#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
},

88
arch/blackfin/mach-bf533/include/mach/anomaly.h
View File

@ -6,7 +6,7 @@
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
/* This file should be up to date with:
* - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
*/
@ -34,12 +34,12 @@
# define ANOMALY_BF533 0
#endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1)
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
#define ANOMALY_05000105 (1)
#define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
@ -48,7 +48,7 @@
#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1)
/* Turning Serial Ports on with External Frame Syncs */
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
#define ANOMALY_05000167 (1)
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
@ -67,9 +67,9 @@
/* Current DMA Address Shows Wrong Value During Carry Fix */
#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
#define ANOMALY_05000201 (__SILICON_REVISION__ < 4)
#define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
/* Possible Infinite Stall with Specific Dual-DAG Situation */
#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
@ -104,7 +104,7 @@
#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Data CPLBs Should Prevent Spurious Hardware Errors */
#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
@ -137,7 +137,7 @@
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
/* Spontaneous Reset of Internal Voltage Regulator */
#define ANOMALY_05000271 (__SILICON_REVISION__ < 4)
#define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* Writes to Synchronous SDRAM Memory May Be Lost */
@ -165,14 +165,14 @@
/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (1)
#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
/* PPI Is Level-Sensitive on First Transfer */
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
@ -200,17 +200,63 @@
#define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
*/
/* Internal voltage regulator can't be modified via register writes */
#define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
/* Watchpoints (Hardware Breakpoints) are not supported */
#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
/* Writing FIO_DIR can corrupt a programmable flag's data */
#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
/* Timer Auto-Baud Mode requires the UART clock to be enabled */
#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
/* Internal Clocking Modes on SPORT0 not supported */
#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
/* Internal voltage regulator does not wake up from an RTC wakeup */
#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
/* The IFLUSH instruction must be preceded by a CSYNC instruction */
#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */
#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */
#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
/* 32-bit SPORT DMA will be word reversed */
#define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
/* Incorrect status in the UART_IIR register */
#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
/* Incorrect value written to the cycle counters */
#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
/* Stores to L1 Data memory incorrect when a specific sequence is followed */
#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
/* Programmable Flag (PF3) functionality not supported in all PPI modes */
#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
/* Data store can be lost when targeting a cache line fill */
#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
/* Reserved bits in SYSCFG register not set at power on */
#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
/* Infinite Core Stall */
#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
/* PPI_FSx may glitch when generated by the on chip Timers */
#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */
#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
@ -222,7 +268,9 @@
/* DMEM_CONTROL is not set on Reset */
#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
/* SPI boot will not complete if there is a zero fill block in the loader file */
#define ANOMALY_05000138 (__SILICON_REVISION__ < 3)
#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */
#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
/* Allowing the SPORT RX FIFO to fill will cause an overflow */
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
@ -237,17 +285,17 @@
#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
/* MDMA may lose the first few words of a descriptor chain */
#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
/* The source MDMA descriptor may stop with a DMA Error */
/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
/* Frame Delay in SPORT Multichannel Mode */
#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */
/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */
/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
/* SPORT transmit data is not gated by external frame sync in certain conditions */
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
@ -275,15 +323,27 @@
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000120 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#endif

1
arch/blackfin/mach-bf537/Kconfig
View File

@ -66,6 +66,7 @@ config IRQ_MAC_TX
default 11
config IRQ_TIMER0
int "IRQ_TIMER0"
default 7 if TICKSOURCE_GPTMR0
default 8
config IRQ_TIMER1
int "IRQ_TIMER1"

4
arch/blackfin/mach-bf537/boards/cm_bf537.c
View File

@ -86,7 +86,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -129,7 +129,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */

8
arch/blackfin/mach-bf537/boards/pnav10.c
View File

@ -265,8 +265,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -333,8 +333,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */

69
arch/blackfin/mach-bf537/boards/stamp.c
View File

@ -508,8 +508,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -607,6 +607,43 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
};
#endif
#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
#include <linux/input.h>
#include <linux/spi/adxl34x.h>
static const struct adxl34x_platform_data adxl34x_info = {
.x_axis_offset = 0,
.y_axis_offset = 0,
.z_axis_offset = 0,
.tap_threshold = 0x31,
.tap_duration = 0x10,
.tap_latency = 0x60,
.tap_window = 0xF0,
.tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
.act_axis_control = 0xFF,
.activity_threshold = 5,
.inactivity_threshold = 3,
.inactivity_time = 4,
.free_fall_threshold = 0x7,
.free_fall_time = 0x20,
.data_rate = 0x8,
.data_range = ADXL_FULL_RES,
.ev_type = EV_ABS,
.ev_code_x = ABS_X, /* EV_REL */
.ev_code_y = ABS_Y, /* EV_REL */
.ev_code_z = ABS_Z, /* EV_REL */
.ev_code_tap_x = BTN_TOUCH, /* EV_KEY */
.ev_code_tap_y = BTN_TOUCH, /* EV_KEY */
.ev_code_tap_z = BTN_TOUCH, /* EV_KEY */
/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
.power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
.fifo_mode = ADXL_FIFO_STREAM,
};
#endif
#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
.enable_dma = 0,
@ -695,8 +732,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) \
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
@ -1280,7 +1317,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
.irq = IRQ_PF5,
},
#endif
#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
},
@ -1312,6 +1349,13 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
.platform_data = (void *)&adp5520_pdev_data,
},
#endif
#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
{
I2C_BOARD_INFO("adxl34x", 0x53),
.irq = IRQ_PG3,
.platform_data = (void *)&adxl34x_info,
},
#endif
};
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@ -1358,16 +1402,18 @@ static struct resource bfin_pata_resources[] = {
static struct pata_platform_info bfin_pata_platform_data = {
.ioport_shift = 0,
};
/* CompactFlash Storage Card Memory Mapped Adressing
* /REG = A11 = 1
*/
static struct resource bfin_pata_resources[] = {
{
.start = 0x20211820,
.end = 0x2021183F,
.start = 0x20211800,
.end = 0x20211807,
.flags = IORESOURCE_MEM,
},
{
.start = 0x2021181C,
.end = 0x2021181F,
.start = 0x2021180E, /* Device Ctl */
.end = 0x2021180E,
.flags = IORESOURCE_MEM,
},
};
@ -1527,7 +1573,8 @@ static int __init stamp_init(void)
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
#if (defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)) \
&& defined(PATA_INT)
irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
#endif

4
arch/blackfin/mach-bf537/boards/tcm_bf537.c
View File

@ -86,7 +86,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -129,7 +129,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */

84
arch/blackfin/mach-bf537/include/mach/anomaly.h
View File

@ -6,7 +6,7 @@
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
/* This file should be up to date with:
* - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
*/
@ -36,77 +36,75 @@
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H cannot be used to access 16-bit System MMR registers */
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
#define ANOMALY_05000167 (1)
/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000180 (1)
/* Instruction Cache Is Not Functional */
#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* Spurious Hardware Error from an access in the shadow of a conditional branch */
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
#define ANOMALY_05000247 (1)
/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
/* EMAC Tx DMA error after an early frame abort */
#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
/* Maximum external clock speed for Timers */
/* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
/* EMAC MDIO input latched on wrong MDC edge */
#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
/* ICPLB_STATUS MMR register may be corrupted */
/* ICPLB_STATUS MMR Register May Be Corrupted */
#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
/* DCPLB_FAULT_ADDR MMR register may be corrupted */
/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
/* Stores to data cache may be lost */
/* Stores To Data Cache May Be Lost */
#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
/* Hardware loop corrupted when taking an ICPLB exception */
/* Hardware Loop Corrupted When Taking an ICPLB Exception */
#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
/* Certain data cache write through modes fail for VDDint <=0.9V */
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* Writes to Synchronous SDRAM memory may be lost */
/* Writes to Synchronous SDRAM Memory May Be Lost */
#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA running may cause DMA system instability */
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
/* SPI Master boot mode does not work well with Atmel Data flash devices */
#define ANOMALY_05000280 (1)
/* False Hardware Error Exception when ISR context is not restored */
/* False Hardware Error Exception When ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
/* Memory DMA corruption with 32-bit data and traffic control */
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
/* SPORTs may receive bad data if FIFOs fill up */
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
/* Memory to memory DMA source/destination descriptors must be in same memory space */
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
#define ANOMALY_05000301 (1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
@ -116,11 +114,11 @@
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
/* False hardware errors caused by fetches at the boundary of reserved memory */
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* PPI is level sensitive on first transfer */
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (1)
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
@ -156,24 +154,46 @@
#define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#endif

1
arch/blackfin/mach-bf538/Kconfig
View File

@ -57,6 +57,7 @@ config IRQ_UART0_TX
default 10
config IRQ_TIMER0
int "IRQ_TIMER0"
default 7 if TICKSOURCE_GPTMR0
default 8
config IRQ_TIMER1
int "IRQ_TIMER1"

60
arch/blackfin/mach-bf538/include/mach/anomaly.h
View File

@ -6,7 +6,7 @@
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
/* This file should be up to date with:
* - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List
* - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List
*/
@ -14,17 +14,29 @@
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* We do not support old silicon - sorry */
#if __SILICON_REVISION__ < 4
# error will not work on BF538 silicon version 0.0, 0.1, 0.2, or 0.3
# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
#endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#if defined(__ADSPBF538__)
# define ANOMALY_BF538 1
#else
# define ANOMALY_BF538 0
#endif
#if defined(__ADSPBF539__)
# define ANOMALY_BF539 1
#else
# define ANOMALY_BF539 0
#endif
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1)
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
#define ANOMALY_05000179 (1)
@ -40,13 +52,13 @@
#define ANOMALY_05000229 (1)
/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
#define ANOMALY_05000233 (1)
/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (1)
/* DCPLB_FAULT_ADDR MMR register may be corrupted */
/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
@ -58,11 +70,11 @@
#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
/* False Hardware Error Exception when ISR Context Is Not Restored */
/* False Hardware Error Exception When ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
@ -80,14 +92,14 @@
#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
/* PPI Is Level-Sensitive on First Transfer */
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
#define ANOMALY_05000318 (__SILICON_REVISION__ < 4)
#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
@ -114,23 +126,45 @@
#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000254 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#endif

19
arch/blackfin/mach-bf538/include/mach/blackfin.h
View File

@ -68,25 +68,6 @@
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */
#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_D0_IRQ_STATUS
#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_D0_START_ADDR
#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_S0_START_ADDR
#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_D0_X_COUNT
#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_S0_X_COUNT
#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_D0_Y_COUNT
#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_S0_Y_COUNT
#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_D0_X_MODIFY
#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_S0_X_MODIFY
#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_D0_Y_MODIFY
#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_S0_Y_MODIFY
#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_S0_CONFIG
#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_D0_CONFIG
#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_S0_CONFIG
#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_D0_IRQ_STATUS
#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_S0_IRQ_STATUS
/* DPMC*/
#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)

65
arch/blackfin/mach-bf538/include/mach/cdefBF538.h
View File

@ -67,14 +67,14 @@
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
#define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
#define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
@ -1247,6 +1247,65 @@
#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA0_S0_CONFIG()
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA0_S0_CONFIG(val)
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA0_S0_IRQ_STATUS()
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA0_S0_IRQ_STATUS(val)
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA0_S0_X_MODIFY()
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA0_S0_X_MODIFY(val)
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA0_S0_Y_MODIFY()
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA0_S0_Y_MODIFY(val)
#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA0_S0_X_COUNT()
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA0_S0_X_COUNT(val)
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA0_S0_Y_COUNT()
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA0_S0_Y_COUNT(val)
#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA0_S0_START_ADDR()
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA0_S0_START_ADDR(val)
#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA0_D0_CONFIG()
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA0_D0_CONFIG(val)
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA0_D0_IRQ_STATUS()
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA0_D0_IRQ_STATUS(val)
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA0_D0_X_MODIFY()
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA0_D0_X_MODIFY(val)
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA0_D0_Y_MODIFY()
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA0_D0_Y_MODIFY(val)
#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA0_D0_X_COUNT()
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA0_D0_X_COUNT(val)
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA0_D0_Y_COUNT()
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA0_D0_Y_COUNT(val)
#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA0_D0_START_ADDR()
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA0_D0_START_ADDR(val)
#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA0_S1_CONFIG()
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA0_S1_CONFIG(val)
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA0_S1_IRQ_STATUS()
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA0_S1_IRQ_STATUS(val)
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA0_S1_X_MODIFY()
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA0_S1_X_MODIFY(val)
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA0_S1_Y_MODIFY()
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA0_S1_Y_MODIFY(val)
#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA0_S1_X_COUNT()
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA0_S1_X_COUNT(val)
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA0_S1_Y_COUNT()
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA0_S1_Y_COUNT(val)
#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA0_S1_START_ADDR()
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA0_S1_START_ADDR(val)
#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA0_D1_CONFIG()
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA0_D1_CONFIG(val)
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA0_D1_IRQ_STATUS()
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA0_D1_IRQ_STATUS(val)
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA0_D1_X_MODIFY()
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA0_D1_X_MODIFY(val)
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA0_D1_Y_MODIFY()
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA0_D1_Y_MODIFY(val)
#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA0_D1_X_COUNT()
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA0_D1_X_COUNT(val)
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA0_D1_Y_COUNT()
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA0_D1_Y_COUNT(val)
#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA0_D1_START_ADDR()
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA0_D1_START_ADDR(val)
#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)

56
arch/blackfin/mach-bf538/include/mach/defBF539.h
View File

@ -412,6 +412,62 @@
#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
#define MDMA_D0_NEXT_DESC_PTR MDMA0_D0_NEXT_DESC_PTR
#define MDMA_D0_START_ADDR MDMA0_D0_START_ADDR
#define MDMA_D0_CONFIG MDMA0_D0_CONFIG
#define MDMA_D0_X_COUNT MDMA0_D0_X_COUNT
#define MDMA_D0_X_MODIFY MDMA0_D0_X_MODIFY
#define MDMA_D0_Y_COUNT MDMA0_D0_Y_COUNT
#define MDMA_D0_Y_MODIFY MDMA0_D0_Y_MODIFY
#define MDMA_D0_CURR_DESC_PTR MDMA0_D0_CURR_DESC_PTR
#define MDMA_D0_CURR_ADDR MDMA0_D0_CURR_ADDR
#define MDMA_D0_IRQ_STATUS MDMA0_D0_IRQ_STATUS
#define MDMA_D0_PERIPHERAL_MAP MDMA0_D0_PERIPHERAL_MAP
#define MDMA_D0_CURR_X_COUNT MDMA0_D0_CURR_X_COUNT
#define MDMA_D0_CURR_Y_COUNT MDMA0_D0_CURR_Y_COUNT
#define MDMA_S0_NEXT_DESC_PTR MDMA0_S0_NEXT_DESC_PTR
#define MDMA_S0_START_ADDR MDMA0_S0_START_ADDR
#define MDMA_S0_CONFIG MDMA0_S0_CONFIG
#define MDMA_S0_X_COUNT MDMA0_S0_X_COUNT
#define MDMA_S0_X_MODIFY MDMA0_S0_X_MODIFY
#define MDMA_S0_Y_COUNT MDMA0_S0_Y_COUNT
#define MDMA_S0_Y_MODIFY MDMA0_S0_Y_MODIFY
#define MDMA_S0_CURR_DESC_PTR MDMA0_S0_CURR_DESC_PTR
#define MDMA_S0_CURR_ADDR MDMA0_S0_CURR_ADDR
#define MDMA_S0_IRQ_STATUS MDMA0_S0_IRQ_STATUS
#define MDMA_S0_PERIPHERAL_MAP MDMA0_S0_PERIPHERAL_MAP
#define MDMA_S0_CURR_X_COUNT MDMA0_S0_CURR_X_COUNT
#define MDMA_S0_CURR_Y_COUNT MDMA0_S0_CURR_Y_COUNT
#define MDMA_D1_NEXT_DESC_PTR MDMA0_D1_NEXT_DESC_PTR
#define MDMA_D1_START_ADDR MDMA0_D1_START_ADDR
#define MDMA_D1_CONFIG MDMA0_D1_CONFIG
#define MDMA_D1_X_COUNT MDMA0_D1_X_COUNT
#define MDMA_D1_X_MODIFY MDMA0_D1_X_MODIFY
#define MDMA_D1_Y_COUNT MDMA0_D1_Y_COUNT
#define MDMA_D1_Y_MODIFY MDMA0_D1_Y_MODIFY
#define MDMA_D1_CURR_DESC_PTR MDMA0_D1_CURR_DESC_PTR
#define MDMA_D1_CURR_ADDR MDMA0_D1_CURR_ADDR
#define MDMA_D1_IRQ_STATUS MDMA0_D1_IRQ_STATUS
#define MDMA_D1_PERIPHERAL_MAP MDMA0_D1_PERIPHERAL_MAP
#define MDMA_D1_CURR_X_COUNT MDMA0_D1_CURR_X_COUNT
#define MDMA_D1_CURR_Y_COUNT MDMA0_D1_CURR_Y_COUNT
#define MDMA_S1_NEXT_DESC_PTR MDMA0_S1_NEXT_DESC_PTR
#define MDMA_S1_START_ADDR MDMA0_S1_START_ADDR
#define MDMA_S1_CONFIG MDMA0_S1_CONFIG
#define MDMA_S1_X_COUNT MDMA0_S1_X_COUNT
#define MDMA_S1_X_MODIFY MDMA0_S1_X_MODIFY
#define MDMA_S1_Y_COUNT MDMA0_S1_Y_COUNT
#define MDMA_S1_Y_MODIFY MDMA0_S1_Y_MODIFY
#define MDMA_S1_CURR_DESC_PTR MDMA0_S1_CURR_DESC_PTR
#define MDMA_S1_CURR_ADDR MDMA0_S1_CURR_ADDR
#define MDMA_S1_IRQ_STATUS MDMA0_S1_IRQ_STATUS
#define MDMA_S1_PERIPHERAL_MAP MDMA0_S1_PERIPHERAL_MAP
#define MDMA_S1_CURR_X_COUNT MDMA0_S1_CURR_X_COUNT
#define MDMA_S1_CURR_Y_COUNT MDMA0_S1_CURR_Y_COUNT
/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */

8
arch/blackfin/mach-bf548/Kconfig
View File

@ -11,6 +11,13 @@ config DEB_DMA_URGENT
help
Treat any DEB1, DEB2 and DEB3 request as Urgent
config BF548_ATAPI_ALTERNATIVE_PORT
bool "BF548 ATAPI alternative port via GPIO"
help
BF548 ATAPI data and address PINs can be routed through
async address or GPIO port F and G. Select y to route it
to GPIO.
comment "Interrupt Priority Assignment"
menu "Priority"
@ -250,6 +257,7 @@ config IRQ_OTPSEC
default 11
config IRQ_TIMER0
int "IRQ_TIMER0"
default 7 if TICKSOURCE_GPTMR0
default 8
config IRQ_TIMER1
int "IRQ_TIMER1"

85
arch/blackfin/mach-bf548/boards/ezkit.c
View File

@ -208,6 +208,43 @@ static struct platform_device bfin_rotary_device = {
};
#endif
#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
#include <linux/input.h>
#include <linux/spi/adxl34x.h>
static const struct adxl34x_platform_data adxl34x_info = {
.x_axis_offset = 0,
.y_axis_offset = 0,
.z_axis_offset = 0,
.tap_threshold = 0x31,
.tap_duration = 0x10,
.tap_latency = 0x60,
.tap_window = 0xF0,
.tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
.act_axis_control = 0xFF,
.activity_threshold = 5,
.inactivity_threshold = 3,
.inactivity_time = 4,
.free_fall_threshold = 0x7,
.free_fall_time = 0x20,
.data_rate = 0x8,
.data_range = ADXL_FULL_RES,
.ev_type = EV_ABS,
.ev_code_x = ABS_X, /* EV_REL */
.ev_code_y = ABS_Y, /* EV_REL */
.ev_code_z = ABS_Z, /* EV_REL */
.ev_code_tap_x = BTN_TOUCH, /* EV_KEY */
.ev_code_tap_y = BTN_TOUCH, /* EV_KEY */
.ev_code_tap_z = BTN_TOUCH, /* EV_KEY */
/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
.power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
.fifo_mode = ADXL_FIFO_STREAM,
};
#endif
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
static struct platform_device rtc_device = {
.name = "rtc-bfin",
@ -628,6 +665,14 @@ static struct bfin5xx_spi_chip spidev_chip_info = {
};
#endif
#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
.enable_dma = 0, /* use dma transfer with this chip*/
.bits_per_word = 8,
.cs_change_per_word = 0,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
@ -653,15 +698,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
{
.modalias = "ad7877",
.platform_data = &bfin_ad7877_ts_info,
.irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 2,
.controller_data = &spi_ad7877_chip_info,
},
{
.modalias = "ad7877",
.platform_data = &bfin_ad7877_ts_info,
.irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 2,
.controller_data = &spi_ad7877_chip_info,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
@ -672,8 +717,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &spidev_chip_info,
},
#endif
#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
{
.modalias = "adxl34x",
.platform_data = &adxl34x_info,
.irq = IRQ_PC5,
.max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 1,
.chip_select = 2,
.controller_data = &spi_adxl34x_chip_info,
.mode = SPI_MODE_3,
},
#endif
};
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
@ -786,7 +842,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
},
@ -797,6 +853,13 @@ static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
.irq = 212,
},
#endif
#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
{
I2C_BOARD_INFO("adxl34x", 0x53),
.irq = IRQ_PC5,
.platform_data = (void *)&adxl34x_info,
},
#endif
};
#endif

44
arch/blackfin/mach-bf548/include/mach/anomaly.h
View File

@ -6,26 +6,31 @@
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
/* This file should be up to date with:
* - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
/* We do not support 0.0 or 0.1 silicon - sorry */
#if __SILICON_REVISION__ < 2
# error will not work on BF548 silicon version 0.0, or 0.1
#endif
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* False Hardware Error Exception when ISR context is not restored */
/* False Hardware Error Exception When ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
@ -59,7 +64,7 @@
#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Intialized */
/* USB Calibration Value Is Not Initialized */
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
/* USB Calibration Value to use */
#define ANOMALY_05000346_value 0x5411
@ -147,11 +152,11 @@
#define ANOMALY_05000416 (1)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
#define ANOMALY_05000425 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
/* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
@ -170,26 +175,49 @@
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
/* USB DMA Mode 1 Short Packet Data Corruption */
#define ANOMALY_05000450 (1
#define ANOMALY_05000450 (1)
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
#define ANOMALY_05000456 (__SILICON_REVISION__ < 3)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000254 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)

64
arch/blackfin/mach-bf548/include/mach/portmux.h
View File

@ -167,22 +167,42 @@
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
#define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
#define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
#define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
#define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
#define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
#define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
#define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
#define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
#define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
#define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
#define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
#define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
#define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
#define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
#define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
#define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
#else
# define P_ATAPI_D0A (P_DONTCARE)
# define P_ATAPI_D1A (P_DONTCARE)
# define P_ATAPI_D2A (P_DONTCARE)
# define P_ATAPI_D3A (P_DONTCARE)
# define P_ATAPI_D4A (P_DONTCARE)
# define P_ATAPI_D5A (P_DONTCARE)
# define P_ATAPI_D6A (P_DONTCARE)
# define P_ATAPI_D7A (P_DONTCARE)
# define P_ATAPI_D8A (P_DONTCARE)
# define P_ATAPI_D9A (P_DONTCARE)
# define P_ATAPI_D10A (P_DONTCARE)
# define P_ATAPI_D11A (P_DONTCARE)
# define P_ATAPI_D12A (P_DONTCARE)
# define P_ATAPI_D13A (P_DONTCARE)
# define P_ATAPI_D14A (P_DONTCARE)
# define P_ATAPI_D15A (P_DONTCARE)
#endif
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
@ -200,9 +220,15 @@
#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
#define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
#define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
#define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
#else
# define P_ATAPI_A0A (P_DONTCARE)
# define P_ATAPI_A1A (P_DONTCARE)
# define P_ATAPI_A2A (P_DONTCARE)
#endif
#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))

16
arch/blackfin/mach-bf561/Kconfig
View File

@ -9,22 +9,9 @@ if (!SMP)
comment "Core B Support"
config BF561_COREB
bool "Enable Core B support"
bool "Enable Core B loader"
default y
config BF561_COREB_RESET
bool "Enable Core B reset support"
default n
help
This requires code in the application that is loaded
into Core B. In order to reset, the application needs
to install an interrupt handler for Supplemental
Interrupt 0, that sets RETI to 0xff600000 and writes
bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
This causes Core B to stall when Supplemental Interrupt
0 is set, and will reset PC to 0xff600000 when
COREB_SRAM_INIT is cleared.
endif
comment "Interrupt Priority Assignment"
@ -138,6 +125,7 @@ config IRQ_DMA2_11
default 9
config IRQ_TIMER0
int "TIMER 0 Interrupt"
default 7 if TICKSOURCE_GPTMR0
default 8
config IRQ_TIMER1
int "TIMER 1 Interrupt"

4
arch/blackfin/mach-bf561/boards/cm_bf561.c
View File

@ -83,7 +83,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
@ -126,7 +126,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */

418
arch/blackfin/mach-bf561/coreb.c
View File

@ -1,406 +1,74 @@
/*
* File: arch/blackfin/mach-bf561/coreb.c
* Based on:
* Author:
/* Load firmware into Core B on a BF561
*
* Created:
* Description: Handle CoreB on a BF561
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* Copyright 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* The Core B reset func requires code in the application that is loaded into
* Core B. In order to reset, the application needs to install an interrupt
* handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and
* writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core
* B to stall when Supplemental Interrupt 0 is set, and will reset PC to
* 0xff600000 when COREB_SRAM_INIT is cleared.
*/
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/device.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/uaccess.h>
#include <linux/fs.h>
#include <asm/dma.h>
#include <asm/cacheflush.h>
#include <linux/kernel.h>
#include <linux/miscdevice.h>
#include <linux/module.h>
#define MODULE_VER "v0.1"
static spinlock_t coreb_lock;
static wait_queue_head_t coreb_dma_wait;
#define COREB_IS_OPEN 0x00000001
#define COREB_IS_RUNNING 0x00000010
#define CMD_COREB_INDEX 1
#define CMD_COREB_START 2
#define CMD_COREB_STOP 3
#define CMD_COREB_RESET 4
#define COREB_MINOR 229
static unsigned long coreb_status = 0;
static unsigned long coreb_base = 0xff600000;
static unsigned long coreb_size = 0x4000;
int coreb_dma_done;
static loff_t coreb_lseek(struct file *file, loff_t offset, int origin);
static ssize_t coreb_read(struct file *file, char *buf, size_t count,
loff_t * ppos);
static ssize_t coreb_write(struct file *file, const char *buf, size_t count,
loff_t * ppos);
static int coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
unsigned long arg);
static int coreb_open(struct inode *inode, struct file *file);
static int coreb_release(struct inode *inode, struct file *file);
static irqreturn_t coreb_dma_interrupt(int irq, void *dev_id)
static int
coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
{
clear_dma_irqstat(CH_MEM_STREAM2_DEST);
coreb_dma_done = 1;
wake_up_interruptible(&coreb_dma_wait);
return IRQ_HANDLED;
}
int ret = 0;
static ssize_t coreb_write(struct file *file, const char *buf, size_t count,
loff_t * ppos)
{
unsigned long p = *ppos;
ssize_t wrote = 0;
if (p + count > coreb_size)
return -EFAULT;
while (count > 0) {
int len = count;
if (len > PAGE_SIZE)
len = PAGE_SIZE;
coreb_dma_done = 0;
flush_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
/* Source Channel */
set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf);
set_dma_x_count(CH_MEM_STREAM2_SRC, len);
set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
set_dma_config(CH_MEM_STREAM2_SRC, 0);
/* Destination Channel */
set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p);
set_dma_x_count(CH_MEM_STREAM2_DEST, len);
set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char));
set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN);
enable_dma(CH_MEM_STREAM2_SRC);
enable_dma(CH_MEM_STREAM2_DEST);
wait_event_interruptible(coreb_dma_wait, coreb_dma_done);
disable_dma(CH_MEM_STREAM2_SRC);
disable_dma(CH_MEM_STREAM2_DEST);
count -= len;
wrote += len;
buf += len;
p += len;
}
*ppos = p;
return wrote;
}
static ssize_t coreb_read(struct file *file, char *buf, size_t count,
loff_t * ppos)
{
unsigned long p = *ppos;
ssize_t read = 0;
if ((p + count) > coreb_size)
return -EFAULT;
while (count > 0) {
int len = count;
if (len > PAGE_SIZE)
len = PAGE_SIZE;
coreb_dma_done = 0;
invalidate_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
/* Source Channel */
set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p);
set_dma_x_count(CH_MEM_STREAM2_SRC, len);
set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
set_dma_config(CH_MEM_STREAM2_SRC, 0);
/* Destination Channel */
set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf);
set_dma_x_count(CH_MEM_STREAM2_DEST, len);
set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char));
set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN);
enable_dma(CH_MEM_STREAM2_SRC);
enable_dma(CH_MEM_STREAM2_DEST);
wait_event_interruptible(coreb_dma_wait, coreb_dma_done);
disable_dma(CH_MEM_STREAM2_SRC);
disable_dma(CH_MEM_STREAM2_DEST);
count -= len;
read += len;
buf += len;
p += len;
}
return read;
}
static loff_t coreb_lseek(struct file *file, loff_t offset, int origin)
{
loff_t ret;
mutex_lock(&file->f_dentry->d_inode->i_mutex);
switch (origin) {
case 0 /* SEEK_SET */ :
if (offset < coreb_size) {
file->f_pos = offset;
ret = file->f_pos;
} else
ret = -EINVAL;
switch (cmd) {
case CMD_COREB_START:
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
break;
case CMD_COREB_STOP:
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
break;
case CMD_COREB_RESET:
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
break;
case 1 /* SEEK_CUR */ :
if ((offset + file->f_pos) < coreb_size) {
file->f_pos += offset;
ret = file->f_pos;
} else
ret = -EINVAL;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&file->f_dentry->d_inode->i_mutex);
CSYNC();
return ret;
}
/* No BKL needed here */
static int coreb_open(struct inode *inode, struct file *file)
{
spin_lock_irq(&coreb_lock);
if (coreb_status & COREB_IS_OPEN)
goto out_busy;
coreb_status |= COREB_IS_OPEN;
spin_unlock_irq(&coreb_lock);
return 0;
out_busy:
spin_unlock_irq(&coreb_lock);
return -EBUSY;
}
static int coreb_release(struct inode *inode, struct file *file)
{
spin_lock_irq(&coreb_lock);
coreb_status &= ~COREB_IS_OPEN;
spin_unlock_irq(&coreb_lock);
return 0;
}
static int coreb_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg)
{
int retval = 0;
int coreb_index = 0;
switch (cmd) {
case CMD_COREB_INDEX:
if (copy_from_user(&coreb_index, (int *)arg, sizeof(int))) {
retval = -EFAULT;
break;
}
spin_lock_irq(&coreb_lock);
switch (coreb_index) {
case 0:
coreb_base = 0xff600000;
coreb_size = 0x4000;
break;
case 1:
coreb_base = 0xff610000;
coreb_size = 0x4000;
break;
case 2:
coreb_base = 0xff500000;
coreb_size = 0x8000;
break;
case 3:
coreb_base = 0xff400000;
coreb_size = 0x8000;
break;
default:
retval = -EINVAL;
break;
}
spin_unlock_irq(&coreb_lock);
mutex_lock(&file->f_dentry->d_inode->i_mutex);
file->f_pos = 0;
mutex_unlock(&file->f_dentry->d_inode->i_mutex);
break;
case CMD_COREB_START:
spin_lock_irq(&coreb_lock);
if (coreb_status & COREB_IS_RUNNING) {
retval = -EBUSY;
break;
}
printk(KERN_INFO "Starting Core B\n");
coreb_status |= COREB_IS_RUNNING;
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
SSYNC();
spin_unlock_irq(&coreb_lock);
break;
#if defined(CONFIG_BF561_COREB_RESET)
case CMD_COREB_STOP:
spin_lock_irq(&coreb_lock);
printk(KERN_INFO "Stopping Core B\n");
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
coreb_status &= ~COREB_IS_RUNNING;
spin_unlock_irq(&coreb_lock);
break;
case CMD_COREB_RESET:
printk(KERN_INFO "Resetting Core B\n");
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
break;
#endif
}
return retval;
}
static struct file_operations coreb_fops = {
.owner = THIS_MODULE,
.llseek = coreb_lseek,
.read = coreb_read,
.write = coreb_write,
.ioctl = coreb_ioctl,
.open = coreb_open,
.release = coreb_release
.owner = THIS_MODULE,
.ioctl = coreb_ioctl,
};
static struct miscdevice coreb_dev = {
COREB_MINOR,
"coreb",
&coreb_fops
.minor = MISC_DYNAMIC_MINOR,
.name = "coreb",
.fops = &coreb_fops,
};
static ssize_t coreb_show_status(struct device *dev, struct device_attribute *attr, char *buf)
static int __init bf561_coreb_init(void)
{
return sprintf(buf,
"Base Address:\t0x%08lx\n"
"Core B is %s\n"
"SICA_SYSCR:\t%04x\n"
"SICB_SYSCR:\t%04x\n"
"\n"
"IRQ Status:\tCore A\t\tCore B\n"
"ISR0:\t\t%08x\t\t%08x\n"
"ISR1:\t\t%08x\t\t%08x\n"
"IMASK0:\t\t%08x\t\t%08x\n"
"IMASK1:\t\t%08x\t\t%08x\n",
coreb_base,
coreb_status & COREB_IS_RUNNING ? "running" : "stalled",
bfin_read_SICA_SYSCR(), bfin_read_SICB_SYSCR(),
bfin_read_SICA_ISR0(), bfin_read_SICB_ISR0(),
bfin_read_SICA_ISR1(), bfin_read_SICB_ISR0(),
bfin_read_SICA_IMASK0(), bfin_read_SICB_IMASK0(),
bfin_read_SICA_IMASK1(), bfin_read_SICB_IMASK1());
return misc_register(&coreb_dev);
}
static DEVICE_ATTR(coreb_status, S_IRUGO, coreb_show_status, NULL);
int __init bf561_coreb_init(void)
{
init_waitqueue_head(&coreb_dma_wait);
spin_lock_init(&coreb_lock);
/* Request the core memory regions for Core B */
if (request_mem_region(0xff600000, 0x4000,
"Core B - Instruction SRAM") == NULL)
goto exit;
if (request_mem_region(0xFF610000, 0x4000,
"Core B - Instruction SRAM") == NULL)
goto release_instruction_a_sram;
if (request_mem_region(0xFF500000, 0x8000,
"Core B - Data Bank B SRAM") == NULL)
goto release_instruction_b_sram;
if (request_mem_region(0xff400000, 0x8000,
"Core B - Data Bank A SRAM") == NULL)
goto release_data_b_sram;
if (request_dma(CH_MEM_STREAM2_DEST, "Core B - DMA Destination") < 0)
goto release_data_a_sram;
if (request_dma(CH_MEM_STREAM2_SRC, "Core B - DMA Source") < 0)
goto release_dma_dest;
set_dma_callback(CH_MEM_STREAM2_DEST, coreb_dma_interrupt, NULL);
misc_register(&coreb_dev);
if (device_create_file(coreb_dev.this_device, &dev_attr_coreb_status))
goto release_dma_src;
printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER);
return 0;
release_dma_src:
free_dma(CH_MEM_STREAM2_SRC);
release_dma_dest:
free_dma(CH_MEM_STREAM2_DEST);
release_data_a_sram:
release_mem_region(0xff400000, 0x8000);
release_data_b_sram:
release_mem_region(0xff500000, 0x8000);
release_instruction_b_sram:
release_mem_region(0xff610000, 0x4000);
release_instruction_a_sram:
release_mem_region(0xff600000, 0x4000);
exit:
return -ENOMEM;
}
void __exit bf561_coreb_exit(void)
{
device_remove_file(coreb_dev.this_device, &dev_attr_coreb_status);
misc_deregister(&coreb_dev);
release_mem_region(0xff610000, 0x4000);
release_mem_region(0xff600000, 0x4000);
release_mem_region(0xff500000, 0x8000);
release_mem_region(0xff400000, 0x8000);
free_dma(CH_MEM_STREAM2_DEST);
free_dma(CH_MEM_STREAM2_SRC);
}
module_init(bf561_coreb_init);
static void __exit bf561_coreb_exit(void)
{
misc_deregister(&coreb_dev);
}
module_exit(bf561_coreb_exit);
MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>");

25
arch/blackfin/mach-bf561/include/mach/anomaly.h
View File

@ -6,7 +6,7 @@
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
/* This file should be up to date with:
* - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
*/
@ -18,11 +18,11 @@
# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
#endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1)
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
/* Testset instructions restricted to 32-bit aligned memory locations */
#define ANOMALY_05000120 (1)
@ -40,7 +40,7 @@
#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
/* Allowing the SPORT RX FIFO to fill will cause an overflow */
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
@ -80,7 +80,7 @@
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1)
/* Turning Serial Ports on with External Frame Syncs */
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
#define ANOMALY_05000167 (1)
/* SDRAM auto-refresh and subsequent Power Ups */
#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
@ -164,7 +164,7 @@
#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
/* TESTSET operation forces stall on the other core */
#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
@ -208,7 +208,7 @@
#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
@ -232,7 +232,7 @@
#define ANOMALY_05000310 (1)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* PPI Is Level-Sensitive on First Transfer */
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (1)
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
#define ANOMALY_05000315 (1)
@ -276,18 +276,27 @@
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000119 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#endif

29
arch/blackfin/mach-bf561/include/mach/cdefBF561.h
View File

@ -1526,6 +1526,35 @@
#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA1_S1_CONFIG()
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val)
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA1_S1_IRQ_STATUS()
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val)
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA1_S1_X_MODIFY()
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val)
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA1_S1_Y_MODIFY()
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val)
#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA1_S1_X_COUNT()
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val)
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA1_S1_Y_COUNT()
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val)
#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA1_S1_START_ADDR()
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val)
#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA1_D1_CONFIG()
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val)
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA1_D1_IRQ_STATUS()
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val)
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA1_D1_X_MODIFY()
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val)
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA1_D1_Y_MODIFY()
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val)
#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA1_D1_X_COUNT()
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val)
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA1_D1_Y_COUNT()
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val)
#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA1_D1_START_ADDR()
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val)
/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>

56
arch/blackfin/mach-bf561/include/mach/defBF561.h
View File

@ -796,6 +796,62 @@
#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR
#define MDMA_D0_CONFIG MDMA1_D0_CONFIG
#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT
#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY
#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT
#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY
#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR
#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR
#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS
#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP
#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT
#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT
#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR
#define MDMA_S0_CONFIG MDMA1_S0_CONFIG
#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT
#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY
#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT
#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY
#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR
#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR
#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS
#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP
#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT
#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT
#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR
#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR
#define MDMA_D1_CONFIG MDMA1_D1_CONFIG
#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT
#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY
#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT
#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY
#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR
#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR
#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS
#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP
#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT
#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT
#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR
#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR
#define MDMA_S1_CONFIG MDMA1_S1_CONFIG
#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT
#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY
#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT
#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY
#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR
#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR
#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS
#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP
#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT
#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT
/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */

4
arch/blackfin/mach-bf561/smp.c
View File

@ -133,9 +133,9 @@ void __init platform_request_ipi(irq_handler_t handler)
int ret;
ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
"SMP interrupt", handler);
"Supplemental Interrupt0", handler);
if (ret)
panic("Cannot request supplemental interrupt 0 for IPI service\n");
panic("Cannot request supplemental interrupt 0 for IPI service");
}
void platform_send_ipi(cpumask_t callmap)

7
arch/blackfin/mach-common/arch_checks.c
View File

@ -71,3 +71,10 @@
#if ANOMALY_05000448
# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
#endif
/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
#if ANOMALY_05000220 && \
((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \
(!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB)))
# error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB.
#endif

46
arch/blackfin/mach-common/cache.S
View File

@ -15,6 +15,13 @@
.text
/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
#if ANOMALY_05000443
# define BROK_FLUSH_INST "IFLUSH"
#else
# define BROK_FLUSH_INST "no anomaly! yeah!"
#endif
/* Since all L1 caches work the same way, we use the same method for flushing
* them. Only the actual flush instruction differs. We write this in asm as
* GCC can be hard to coax into writing nice hardware loops.
@ -23,7 +30,7 @@
* R0 = start address
* R1 = end address
*/
.macro do_flush flushins:req optflushins optnopins label
.macro do_flush flushins:req label
R2 = -L1_CACHE_BYTES;
@ -44,22 +51,15 @@
\label :
.endif
P0 = R0;
LSETUP (1f, 2f) LC1 = P1;
1:
.ifnb \optflushins
\optflushins [P0];
.endif
#if ANOMALY_05000443
.ifb \optnopins
2:
.endif
.ifeqs "\flushins", BROK_FLUSH_INST
\flushins [P0++];
.ifnb \optnopins
2: \optnopins;
.endif
#else
2: nop;
.else
2: \flushins [P0++];
#endif
.endif
RTS;
.endm
@ -77,25 +77,9 @@ ENTRY(_blackfin_icache_flush_range)
*/
P0 = R0;
IFLUSH[P0];
do_flush IFLUSH, , nop
do_flush IFLUSH
ENDPROC(_blackfin_icache_flush_range)
/* Flush all cache lines assocoiated with this area of memory. */
ENTRY(_blackfin_icache_dcache_flush_range)
/*
* Walkaround to avoid loading wrong instruction after invalidating icache
* and following sequence is met.
*
* 1) One instruction address is cached in the instruction cache.
* 2) This instruction in SDRAM is changed.
* 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
* 4) This instruction is executed again, but the old one is loaded.
*/
P0 = R0;
IFLUSH[P0];
do_flush FLUSH, IFLUSH
ENDPROC(_blackfin_icache_dcache_flush_range)
/* Throw away all D-cached data in specified region without any obligation to
* write them back. Since the Blackfin ISA does not have an "invalidate"
* instruction, we use flush/invalidate. Perhaps as a speed optimization we
@ -107,7 +91,7 @@ ENDPROC(_blackfin_dcache_invalidate_range)
/* Flush all data cache lines assocoiated with this memory area */
ENTRY(_blackfin_dcache_flush_range)
do_flush FLUSH, , , .Ldfr
do_flush FLUSH, .Ldfr
ENDPROC(_blackfin_dcache_flush_range)
/* Our headers convert the page structure to an address, so just need to flush

1
arch/blackfin/mach-common/clocks-init.c
View File

@ -72,6 +72,7 @@ void init_clocks(void)
#endif
bfin_write_PLL_LOCKCNT(0x300);
do_sync();
/* We always write PLL_CTL thus avoiding Anomaly 05000242 */
bfin_write16(PLL_CTL, PLL_CTL_VAL);
__asm__ __volatile__("IDLE;");
bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);

3
arch/blackfin/mach-common/cpufreq.c
View File

@ -140,7 +140,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
cclk = get_cclk() / 1000;
sclk = get_sclk() / 1000;
#if ANOMALY_05000273 || (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE))
#if ANOMALY_05000273 || ANOMALY_05000274 || \
(!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE))
min_cclk = sclk * 2;
#else
min_cclk = sclk;

76
arch/blackfin/mach-common/entry.S
View File

@ -36,7 +36,6 @@
#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/unistd.h>
#include <linux/threads.h>
#include <asm/blackfin.h>
#include <asm/errno.h>
#include <asm/fixed_code.h>
@ -201,7 +200,18 @@ ENTRY(_ex_single_step)
cc = r7 == 0;
if !cc jump 1f;
#endif
#ifdef CONFIG_EXACT_HWERR
/* Read the ILAT, and to check to see if the process we are
* single stepping caused a previous hardware error
* If so, do not single step, (which lowers to IRQ5, and makes
* us miss the error).
*/
p5.l = lo(ILAT);
p5.h = hi(ILAT);
r7 = [p5];
cc = bittst(r7, EVT_IVHW_P);
if cc jump 1f;
#endif
/* Single stepping only a single instruction, so clear the trace
* bit here. */
r7 = syscfg;
@ -263,15 +273,6 @@ ENTRY(_bfin_return_from_exception)
r6 = 0x25;
CC = R7 == R6;
if CC JUMP _double_fault;
/* Did we cause a HW error? */
p5.l = lo(ILAT);
p5.h = hi(ILAT);
r6 = [p5];
r7 = 0x20; /* Did I just cause anther HW error? */
r6 = r7 & r6;
CC = R7 == R6;
if CC JUMP _double_fault;
#endif
(R7:6,P5:4) = [sp++];
@ -473,6 +474,16 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
[--sp] = ASTAT;
[--sp] = (R7:6,P5:4);
#ifdef CONFIG_EXACT_HWERR
/* Make sure all pending read/writes complete. This will ensure any
* accesses which could cause hardware errors completes, and signal
* the the hardware before we do something silly, like crash the
* kernel. We don't need to work around anomaly 05000312, since
* we are already atomic
*/
ssync;
#endif
#if ANOMALY_05000283 || ANOMALY_05000315
cc = r7 == r7;
p5.h = HI(CHIPID);
@ -855,7 +866,7 @@ ENTRY(_ret_from_exception)
p1.h = _schedule_and_signal;
[p0] = p1;
csync;
raise 15; /* raise evt14 to do signal or reschedule */
raise 15; /* raise evt15 to do signal or reschedule */
4:
r0 = syscfg;
bitclr(r0, 0);
@ -916,7 +927,7 @@ ENTRY(_return_from_int)
p1.h = _schedule_and_signal_from_int;
[p0] = p1;
csync;
#if ANOMALY_05000281
#if ANOMALY_05000281 || ANOMALY_05000461
r0.l = lo(SAFE_USER_INSTRUCTION);
r0.h = hi(SAFE_USER_INSTRUCTION);
reti = r0;
@ -930,18 +941,27 @@ ENTRY(_return_from_int)
ENDPROC(_return_from_int)
ENTRY(_lower_to_irq14)
#if ANOMALY_05000281
#if ANOMALY_05000281 || ANOMALY_05000461
r0.l = lo(SAFE_USER_INSTRUCTION);
r0.h = hi(SAFE_USER_INSTRUCTION);
reti = r0;
#endif
r0 = 0x401f;
#ifdef CONFIG_DEBUG_HWERR
/* enable irq14 & hwerr interrupt, until we transition to _evt14_softirq */
r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
#else
/* Only enable irq14 interrupt, until we transition to _evt14_softirq */
r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
#endif
sti r0;
raise 14;
rti;
ENDPROC(_lower_to_irq14)
ENTRY(_evt14_softirq)
#ifdef CONFIG_DEBUG_HWERR
r0 = 0x3f;
r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
sti r0;
#else
cli r0;
@ -949,8 +969,9 @@ ENTRY(_evt14_softirq)
[--sp] = RETI;
SP += 4;
rts;
ENDPROC(_evt14_softirq)
_schedule_and_signal_from_int:
ENTRY(_schedule_and_signal_from_int)
/* To end up here, vector 15 was changed - so we have to change it
* back.
*/
@ -983,8 +1004,9 @@ _schedule_and_signal_from_int:
call _finish_atomic_sections;
sp += 12;
jump.s .Lresume_userspace;
ENDPROC(_schedule_and_signal_from_int)
_schedule_and_signal:
ENTRY(_schedule_and_signal)
SAVE_CONTEXT_SYSCALL
/* To end up here, vector 15 was changed - so we have to change it
* back.
@ -1002,7 +1024,7 @@ _schedule_and_signal:
1:
RESTORE_CONTEXT
rti;
ENDPROC(_lower_to_irq14)
ENDPROC(_schedule_and_signal)
/* We handle this 100% in exception space - to reduce overhead
* Only potiential problem is if the software buffer gets swapped out of the
@ -1588,19 +1610,3 @@ ENTRY(_sys_call_table)
.long _sys_ni_syscall
.endr
END(_sys_call_table)
#ifdef CONFIG_EXCEPTION_L1_SCRATCH
/* .section .l1.bss.scratch */
.set _exception_stack_top, L1_SCRATCH_START + L1_SCRATCH_LENGTH
#else
#ifdef CONFIG_SYSCALL_TAB_L1
.section .l1.bss
#else
.bss
#endif
ENTRY(_exception_stack)
.rept 1024 * NR_CPUS
.long 0
.endr
_exception_stack_top:
#endif

34
arch/blackfin/mach-common/head.S
View File

@ -30,8 +30,6 @@ ENTRY(__init_clear_bss)
rts;
ENDPROC(__init_clear_bss)
#define INITIAL_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
ENTRY(__start)
/* R0: argument of command line string, passed from uboot, save it */
R7 = R0;
@ -126,30 +124,30 @@ ENTRY(__start)
* below
*/
GET_PDA(p0, r0);
r7 = [p0 + PDA_RETX];
r6 = [p0 + PDA_RETX];
p1.l = _init_saved_retx;
p1.h = _init_saved_retx;
[p1] = r7;
[p1] = r6;
r7 = [p0 + PDA_DCPLB];
r6 = [p0 + PDA_DCPLB];
p1.l = _init_saved_dcplb_fault_addr;
p1.h = _init_saved_dcplb_fault_addr;
[p1] = r7;
[p1] = r6;
r7 = [p0 + PDA_ICPLB];
r6 = [p0 + PDA_ICPLB];
p1.l = _init_saved_icplb_fault_addr;
p1.h = _init_saved_icplb_fault_addr;
[p1] = r7;
[p1] = r6;
r7 = [p0 + PDA_SEQSTAT];
r6 = [p0 + PDA_SEQSTAT];
p1.l = _init_saved_seqstat;
p1.h = _init_saved_seqstat;
[p1] = r7;
[p1] = r6;
#endif
/* Initialize stack pointer */
sp.l = lo(INITIAL_STACK);
sp.h = hi(INITIAL_STACK);
sp.l = _init_thread_union;
sp.h = _init_thread_union;
fp = sp;
usp = sp;
@ -189,7 +187,15 @@ ENTRY(__start)
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
call _bfin_relocate_l1_mem;
#ifdef CONFIG_BFIN_KERNEL_CLOCK
/* Only use on-chip scratch space for stack when absolutely required
* to avoid Anomaly 05000227 ... we know the init_clocks() func only
* uses L1 text and stack space and no other memory region.
*/
# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
sp.l = lo(KERNEL_CLOCK_STACK);
sp.h = hi(KERNEL_CLOCK_STACK);
call _init_clocks;
sp = usp; /* usp hasnt been touched, so restore from there */
#endif
/* This section keeps the processor in supervisor mode
@ -243,9 +249,7 @@ ENTRY(_real_start)
call _cmdline_init;
/* Load the current thread pointer and stack */
sp.l = _init_thread_union;
sp.h = _init_thread_union;
p1 = THREAD_SIZE (z);
p1 = THREAD_SIZE + 4 (z); /* +4 is for reti loading */
sp = sp + p1;
usp = sp;
fp = sp;

27
arch/blackfin/mach-common/interrupt.S
View File

@ -145,6 +145,14 @@ __common_int_entry:
/* interrupt routine for ivhw - 5 */
ENTRY(_evt_ivhw)
/* In case a single action kicks off multiple memory transactions, (like
* a cache line fetch, - this can cause multiple hardware errors, let's
* catch them all. First - make sure all the actions are complete, and
* the core sees the hardware errors.
*/
SSYNC;
SSYNC;
SAVE_ALL_SYS
#ifdef CONFIG_FRAME_POINTER
fp = 0;
@ -159,6 +167,25 @@ ENTRY(_evt_ivhw)
1:
#endif
/* Handle all stacked hardware errors
* To make sure we don't hang forever, only do it 10 times
*/
R0 = 0;
R2 = 10;
1:
P0.L = LO(ILAT);
P0.H = HI(ILAT);
R1 = [P0];
CC = BITTST(R1, EVT_IVHW_P);
IF ! CC JUMP 2f;
/* OK a hardware error is pending - clear it */
R1 = EVT_IVHW_P;
[P0] = R1;
R0 += 1;
CC = R1 == R2;
if CC JUMP 2f;
JUMP 1b;
2:
# We are going to dump something out, so make sure we print IPEND properly
p2.l = lo(IPEND);
p2.h = hi(IPEND);

50
arch/blackfin/mach-common/ints-priority.c
View File

@ -1052,7 +1052,7 @@ int __init init_arch_irq(void)
set_irq_chained_handler(irq, bfin_demux_error_irq);
break;
#endif
#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
#if defined(CONFIG_TICKSOURCE_GPTMR0)
case IRQ_TIMER0:
set_irq_handler(irq, handle_percpu_irq);
break;
@ -1116,6 +1116,9 @@ int __init init_arch_irq(void)
IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
/* This implicitly covers ANOMALY_05000171
* Boot-ROM code modifies SICA_IWRx wakeup registers
*/
#ifdef SIC_IWR0
bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
# ifdef SIC_IWR1
@ -1136,13 +1139,6 @@ int __init init_arch_irq(void)
bfin_write_SIC_IWR(IWR_DISABLE_ALL);
#endif
#ifdef CONFIG_IPIPE
for (irq = 0; irq < NR_IRQS; irq++) {
struct irq_desc *desc = irq_to_desc(irq);
desc->ic_prio = __ipipe_get_irq_priority(irq);
}
#endif /* CONFIG_IPIPE */
return 0;
}
@ -1156,23 +1152,22 @@ void do_irq(int vec, struct pt_regs *fp)
} else {
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
|| defined(BF538_FAMILY) || defined(CONFIG_BF51x)
#if defined(SIC_ISR0) || defined(SICA_ISR0)
unsigned long sic_status[3];
if (smp_processor_id()) {
#ifdef CONFIG_SMP
# ifdef SICB_ISR0
/* This will be optimized out in UP mode. */
sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
#endif
# endif
} else {
sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
}
#ifdef CONFIG_BF54x
# ifdef SIC_ISR2
sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
#endif
# endif
for (;; ivg++) {
if (ivg >= ivg_stop) {
atomic_inc(&num_spurious);
@ -1236,20 +1231,16 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
if (likely(vec == EVT_IVTMR_P)) {
irq = IRQ_CORETMR;
goto core_tick;
}
SSYNC();
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
{
} else {
#if defined(SIC_ISR0) || defined(SICA_ISR0)
unsigned long sic_status[3];
sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
#ifdef CONFIG_BF54x
# ifdef SIC_ISR2
sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
#endif
# endif
for (;; ivg++) {
if (ivg >= ivg_stop) {
atomic_inc(&num_spurious);
@ -1258,9 +1249,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
break;
}
}
#else
{
unsigned long sic_status;
sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
@ -1272,15 +1261,13 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
} else if (sic_status & ivg->isrflag)
break;
}
}
#endif
irq = ivg->irqno;
irq = ivg->irqno;
}
if (irq == IRQ_SYSTMR) {
#ifdef CONFIG_GENERIC_CLOCKEVENTS
core_tick:
#else
#ifndef CONFIG_GENERIC_CLOCKEVENTS
bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
#endif
/* This is basically what we need from the register frame. */
@ -1292,9 +1279,6 @@ core_tick:
__raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
}
#ifndef CONFIG_GENERIC_CLOCKEVENTS
core_tick:
#endif
if (this_domain == ipipe_root_domain) {
s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
barrier();
@ -1312,7 +1296,7 @@ core_tick:
}
}
return 0;
return 0;
}
#endif /* CONFIG_IPIPE */

12
arch/blackfin/mach-common/smp.c
View File

@ -43,8 +43,13 @@
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/cpu.h>
#include <asm/time.h>
#include <linux/err.h>
/*
* Anomaly notes:
* 05000120 - we always define corelock as 32-bit integer in L2
*/
struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
@ -352,7 +357,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
static void __cpuinit setup_secondary(unsigned int cpu)
{
#if !(defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE))
#if !defined(CONFIG_TICKSOURCE_GPTMR0)
struct irq_desc *timer_desc;
#endif
unsigned long ilat;
@ -364,16 +369,13 @@ static void __cpuinit setup_secondary(unsigned int cpu)
bfin_write_ILAT(ilat);
CSYNC();
/* Reserve the PDA space for the secondary CPU. */
reserve_pda();
/* Enable interrupt levels IVG7-15. IARs have been already
* programmed by the boot CPU. */
bfin_irq_flags |= IMASK_IVG15 |
IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
#if defined(CONFIG_TICKSOURCE_GPTMR0)
/* Power down the core timer, just to play safe. */
bfin_write_TCNTL(0);

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