net/mlx5e: Choose best nearest LRO timeout
Instead of predicting the index of the wanted LRO timeout value from
hardware capabilities, look for the nearest LRO timeout value.
Fixes: 5c50368f38
('net/mlx5e: Light-weight netdev open/stop')
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Mohamad Haj Yahia <mohamad@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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@ -85,6 +85,9 @@
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#define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
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#define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
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#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
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#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
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#define MLX5E_DEFAULT_LRO_TIMEOUT 32
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#define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
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@ -221,6 +224,7 @@ struct mlx5e_params {
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struct ieee_ets ets;
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struct ieee_ets ets;
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#endif
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#endif
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bool rx_am_enabled;
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bool rx_am_enabled;
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u32 lro_timeout;
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};
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};
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struct mlx5e_tstamp {
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struct mlx5e_tstamp {
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@ -888,5 +892,6 @@ int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
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void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
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void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
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struct rtnl_link_stats64 *
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struct rtnl_link_stats64 *
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mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
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mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
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u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
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#endif /* __MLX5_EN_H__ */
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#endif /* __MLX5_EN_H__ */
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@ -1971,9 +1971,7 @@ static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
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MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
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MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
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(priv->params.lro_wqe_sz -
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(priv->params.lro_wqe_sz -
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ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
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ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
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MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
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MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
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MLX5_CAP_ETH(priv->mdev,
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lro_timer_supported_periods[2]));
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}
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}
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void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
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void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
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@ -3401,6 +3399,18 @@ static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
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}
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}
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}
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}
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u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
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{
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int i;
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/* The supported periods are organized in ascending order */
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for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
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if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
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break;
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return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
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}
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static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
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static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
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struct net_device *netdev,
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struct net_device *netdev,
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const struct mlx5e_profile *profile,
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const struct mlx5e_profile *profile,
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@ -3419,6 +3429,9 @@ static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
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priv->profile = profile;
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priv->profile = profile;
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priv->ppriv = ppriv;
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priv->ppriv = ppriv;
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priv->params.lro_timeout =
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mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
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priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
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priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
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/* set CQE compression */
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/* set CQE compression */
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