x64, x2apic/intr-remap: Interrupt remapping infrastructure
Interrupt remapping (part of Intel Virtualization Tech for directed I/O) infrastructure. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
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fe962e90cb
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2ae2101069
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@ -145,6 +145,8 @@ struct device_domain_info {
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extern int init_dmars(void);
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extern void free_dmar_iommu(struct intel_iommu *iommu);
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extern int dmar_disabled;
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#ifndef CONFIG_DMAR_GFX_WA
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static inline void iommu_prepare_gfx_mapping(void)
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{
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@ -449,6 +449,22 @@ int __init early_dmar_detect(void)
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return (ACPI_SUCCESS(status) ? 1 : 0);
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}
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void __init detect_intel_iommu(void)
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{
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int ret;
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ret = early_dmar_detect();
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#ifdef CONFIG_DMAR
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{
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if (ret && !no_iommu && !iommu_detected && !swiotlb &&
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!dmar_disabled)
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iommu_detected = 1;
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}
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#endif
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}
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int alloc_iommu(struct dmar_drhd_unit *drhd)
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{
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struct intel_iommu *iommu;
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@ -76,7 +76,7 @@ static long list_size;
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static void domain_remove_dev_info(struct dmar_domain *domain);
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static int dmar_disabled;
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int dmar_disabled;
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static int __initdata dmar_map_gfx = 1;
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static int dmar_forcedac;
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static int intel_iommu_strict;
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@ -2238,15 +2238,6 @@ static void __init iommu_exit_mempool(void)
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}
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void __init detect_intel_iommu(void)
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{
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if (swiotlb || no_iommu || iommu_detected || dmar_disabled)
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return;
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if (early_dmar_detect()) {
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iommu_detected = 1;
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}
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}
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static void __init init_no_remapping_devices(void)
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{
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struct dmar_drhd_unit *drhd;
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@ -2293,15 +2284,19 @@ int __init intel_iommu_init(void)
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{
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int ret = 0;
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if (no_iommu || swiotlb || dmar_disabled)
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return -ENODEV;
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if (dmar_table_init())
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return -ENODEV;
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if (dmar_dev_scope_init())
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return -ENODEV;
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/*
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* Check the need for DMA-remapping initialization now.
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* Above initialization will also be used by Interrupt-remapping.
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*/
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if (no_iommu || swiotlb || dmar_disabled)
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return -ENODEV;
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iommu_init_mempool();
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dmar_init_reserved_ranges();
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@ -56,6 +56,7 @@
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#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
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#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
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#define DMAR_ICS_REG 0x98 /* Invalidation complete status register */
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#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
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#define OFFSET_STRIDE (9)
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/*
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@ -157,16 +158,20 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
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#define DMA_GCMD_SRTP (((u32)1) << 30)
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#define DMA_GCMD_SFL (((u32)1) << 29)
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#define DMA_GCMD_EAFL (((u32)1) << 28)
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#define DMA_GCMD_QIE (((u32)1) << 26)
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#define DMA_GCMD_WBF (((u32)1) << 27)
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#define DMA_GCMD_QIE (((u32)1) << 26)
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#define DMA_GCMD_SIRTP (((u32)1) << 24)
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#define DMA_GCMD_IRE (((u32) 1) << 25)
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/* GSTS_REG */
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#define DMA_GSTS_TES (((u32)1) << 31)
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#define DMA_GSTS_RTPS (((u32)1) << 30)
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#define DMA_GSTS_FLS (((u32)1) << 29)
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#define DMA_GSTS_AFLS (((u32)1) << 28)
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#define DMA_GSTS_QIES (((u32)1) << 26)
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#define DMA_GSTS_WBFS (((u32)1) << 27)
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#define DMA_GSTS_QIES (((u32)1) << 26)
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#define DMA_GSTS_IRTPS (((u32)1) << 24)
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#define DMA_GSTS_IRES (((u32)1) << 25)
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/* CCMD_REG */
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#define DMA_CCMD_ICC (((u64)1) << 63)
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@ -245,6 +250,16 @@ struct q_inval {
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int free_cnt;
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};
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#ifdef CONFIG_INTR_REMAP
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/* 1MB - maximum possible interrupt remapping table size */
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#define INTR_REMAP_PAGE_ORDER 8
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#define INTR_REMAP_TABLE_REG_SIZE 0xf
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struct ir_table {
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struct irte *base;
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};
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#endif
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struct intel_iommu {
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void __iomem *reg; /* Pointer to hardware regs, virtual addr */
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u64 cap;
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@ -266,6 +281,9 @@ struct intel_iommu {
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struct sys_device sysdev;
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#endif
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struct q_inval *qi; /* Queued invalidation info */
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#ifdef CONFIG_INTR_REMAP
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struct ir_table *ir_table; /* Interrupt remapping info */
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#endif
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};
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static inline void __iommu_flush_cache(
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@ -279,5 +297,7 @@ extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
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extern int alloc_iommu(struct dmar_drhd_unit *drhd);
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extern void free_iommu(struct intel_iommu *iommu);
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extern int dmar_enable_qi(struct intel_iommu *iommu);
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extern void qi_global_iec(struct intel_iommu *iommu);
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#endif
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@ -1,10 +1,147 @@
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#include <linux/dmar.h>
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#include <linux/spinlock.h>
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#include <linux/jiffies.h>
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#include <linux/pci.h>
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#include <asm/io_apic.h>
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#include "intel-iommu.h"
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#include "intr_remapping.h"
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static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
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static int ir_ioapic_num;
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int intr_remapping_enabled;
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static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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{
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u64 addr;
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u32 cmd, sts;
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unsigned long flags;
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addr = virt_to_phys((void *)iommu->ir_table->base);
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spin_lock_irqsave(&iommu->register_lock, flags);
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dmar_writeq(iommu->reg + DMAR_IRTA_REG,
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(addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
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/* Set interrupt-remapping table pointer */
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cmd = iommu->gcmd | DMA_GCMD_SIRTP;
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writel(cmd, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_IRTPS), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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/*
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* global invalidation of interrupt entry cache before enabling
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* interrupt-remapping.
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*/
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qi_global_iec(iommu);
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spin_lock_irqsave(&iommu->register_lock, flags);
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/* Enable interrupt-remapping */
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cmd = iommu->gcmd | DMA_GCMD_IRE;
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iommu->gcmd |= DMA_GCMD_IRE;
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writel(cmd, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_IRES), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
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{
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struct ir_table *ir_table;
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struct page *pages;
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ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
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GFP_KERNEL);
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if (!iommu->ir_table)
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return -ENOMEM;
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pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
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if (!pages) {
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printk(KERN_ERR "failed to allocate pages of order %d\n",
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INTR_REMAP_PAGE_ORDER);
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kfree(iommu->ir_table);
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return -ENOMEM;
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}
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ir_table->base = page_address(pages);
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iommu_set_intr_remapping(iommu, mode);
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return 0;
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}
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int __init enable_intr_remapping(int eim)
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{
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struct dmar_drhd_unit *drhd;
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int setup = 0;
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/*
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* check for the Interrupt-remapping support
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*/
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for_each_drhd_unit(drhd) {
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struct intel_iommu *iommu = drhd->iommu;
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if (!ecap_ir_support(iommu->ecap))
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continue;
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if (eim && !ecap_eim_support(iommu->ecap)) {
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printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
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" ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
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return -1;
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}
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}
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/*
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* Enable queued invalidation for all the DRHD's.
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*/
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for_each_drhd_unit(drhd) {
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int ret;
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struct intel_iommu *iommu = drhd->iommu;
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ret = dmar_enable_qi(iommu);
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if (ret) {
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printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
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" invalidation, ecap %Lx, ret %d\n",
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drhd->reg_base_addr, iommu->ecap, ret);
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return -1;
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}
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}
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/*
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* Setup Interrupt-remapping for all the DRHD's now.
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*/
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for_each_drhd_unit(drhd) {
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struct intel_iommu *iommu = drhd->iommu;
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if (!ecap_ir_support(iommu->ecap))
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continue;
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if (setup_intr_remapping(iommu, eim))
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goto error;
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setup = 1;
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}
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if (!setup)
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goto error;
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intr_remapping_enabled = 1;
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return 0;
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error:
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/*
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* handle error condition gracefully here!
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*/
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return -1;
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}
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static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
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struct intel_iommu *iommu)
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@ -4,3 +4,5 @@ struct ioapic_scope {
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struct intel_iommu *iommu;
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unsigned int id;
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};
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#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
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@ -25,33 +25,9 @@
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#include <linux/types.h>
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#include <linux/msi.h>
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#ifdef CONFIG_DMAR
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#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
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struct intel_iommu;
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extern const char *dmar_get_fault_reason(u8 fault_reason);
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/* Can't use the common MSI interrupt functions
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* since DMAR is not a pci device
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*/
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extern void dmar_msi_unmask(unsigned int irq);
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extern void dmar_msi_mask(unsigned int irq);
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extern void dmar_msi_read(int irq, struct msi_msg *msg);
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extern void dmar_msi_write(int irq, struct msi_msg *msg);
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extern int dmar_set_interrupt(struct intel_iommu *iommu);
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extern int arch_setup_dmar_msi(unsigned int irq);
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/* Intel IOMMU detection and initialization functions */
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extern void detect_intel_iommu(void);
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extern int intel_iommu_init(void);
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extern int dmar_table_init(void);
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extern int early_dmar_detect(void);
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extern int dmar_dev_scope_init(void);
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extern int parse_ioapics_under_ir(void);
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extern struct list_head dmar_drhd_units;
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extern struct list_head dmar_rmrr_units;
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struct dmar_drhd_unit {
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struct list_head list; /* list of drhd units */
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struct acpi_dmar_header *hdr; /* ACPI header */
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@ -63,6 +39,85 @@ struct dmar_drhd_unit {
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struct intel_iommu *iommu;
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};
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extern struct list_head dmar_drhd_units;
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#define for_each_drhd_unit(drhd) \
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list_for_each_entry(drhd, &dmar_drhd_units, list)
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extern int dmar_table_init(void);
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extern int early_dmar_detect(void);
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extern int dmar_dev_scope_init(void);
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/* Intel IOMMU detection */
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extern void detect_intel_iommu(void);
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extern int parse_ioapics_under_ir(void);
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extern int alloc_iommu(struct dmar_drhd_unit *);
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#else
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static inline void detect_intel_iommu(void)
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{
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return;
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}
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static inline int dmar_table_init(void)
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{
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return -ENODEV;
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}
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#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
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#ifdef CONFIG_INTR_REMAP
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extern int intr_remapping_enabled;
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extern int enable_intr_remapping(int);
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struct irte {
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union {
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struct {
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__u64 present : 1,
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fpd : 1,
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dst_mode : 1,
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redir_hint : 1,
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trigger_mode : 1,
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dlvry_mode : 3,
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avail : 4,
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__reserved_1 : 4,
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vector : 8,
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__reserved_2 : 8,
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dest_id : 32;
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};
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__u64 low;
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};
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union {
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struct {
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__u64 sid : 16,
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sq : 2,
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svt : 2,
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__reserved_3 : 44;
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};
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__u64 high;
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};
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};
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#else
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#define enable_intr_remapping(mode) (-1)
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#define intr_remapping_enabled (0)
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#endif
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#ifdef CONFIG_DMAR
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extern const char *dmar_get_fault_reason(u8 fault_reason);
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/* Can't use the common MSI interrupt functions
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* since DMAR is not a pci device
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*/
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extern void dmar_msi_unmask(unsigned int irq);
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extern void dmar_msi_mask(unsigned int irq);
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extern void dmar_msi_read(int irq, struct msi_msg *msg);
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extern void dmar_msi_write(int irq, struct msi_msg *msg);
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extern int dmar_set_interrupt(struct intel_iommu *iommu);
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extern int arch_setup_dmar_msi(unsigned int irq);
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extern int iommu_detected, no_iommu;
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extern struct list_head dmar_rmrr_units;
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struct dmar_rmrr_unit {
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struct list_head list; /* list of rmrr units */
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struct acpi_dmar_header *hdr; /* ACPI header */
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@ -72,24 +127,19 @@ struct dmar_rmrr_unit {
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int devices_cnt; /* target device count */
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};
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#define for_each_drhd_unit(drhd) \
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list_for_each_entry(drhd, &dmar_drhd_units, list)
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#define for_each_rmrr_units(rmrr) \
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list_for_each_entry(rmrr, &dmar_rmrr_units, list)
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extern int alloc_iommu(struct dmar_drhd_unit *);
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/* Intel DMAR initialization functions */
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extern int intel_iommu_init(void);
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extern int dmar_disabled;
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#else
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static inline void detect_intel_iommu(void)
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{
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return;
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}
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static inline int intel_iommu_init(void)
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{
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#ifdef CONFIG_INTR_REMAP
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return dmar_dev_scope_init();
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#else
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return -ENODEV;
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}
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static inline int dmar_table_init(void)
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{
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return -ENODEV;
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#endif
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}
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#endif /* !CONFIG_DMAR */
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#endif /* __DMAR_H__ */
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