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dmaengine: qcom: bam_dma: use correct pipe FIFO size 

The pipe fifo size register must instruct the bam hw
how many hw descriptors can be pushed to fifo. Currently
we instruct the hw with 32KBytes but wrap the tail in
bam_start_dma in BAM_P_EVNT_REG on 4095 i.e. 32760. This
leads to stalled transactions when the tail wraps.

Fix this by use the correct fifo size in BAM_P_FIFO_SIZES
register i.e. 32K - 8.

Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Stanimir Varbanov 2016-04-11 11:38:42 +03:00 committed by Vinod Koul
parent 5172c9eb89
commit 2a663ed9fe
1 changed files with 1 additions and 1 deletions
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2
drivers/dma/qcom/bam_dma.c
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@ -459,7 +459,7 @@ static void bam_chan_init_hw(struct bam_chan *bchan,
*/ */
writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)), writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR)); bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
writel_relaxed(BAM_DESC_FIFO_SIZE, writel_relaxed(BAM_MAX_DATA_SIZE,
bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES)); bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
/* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */ /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */