x86: add X86_FEATURE_XMM4_2 definitions
Added Intel processor SSE4.2 feature flag. No in-tree user at the moment, but makes the tree-merging life easier for the crypto tree. Signed-off-by: Austin Zhang <austin.zhang@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -91,6 +91,7 @@
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#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
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#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
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#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
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#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
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#define X86_FEATURE_XMM4_2 (4*32+20) /* Streaming SIMD Extensions-4.2 */
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/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
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/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
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#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
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#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
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@ -189,6 +190,7 @@ extern const char * const x86_power_flags[32];
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#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
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#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
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#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
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#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
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#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
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#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
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#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
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#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
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#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
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# define cpu_has_invlpg 1
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# define cpu_has_invlpg 1
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