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linux-sg2042
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Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm 

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] pxa: spitz wants PXA27x UDC definitions
  [ARM] pxa: fix pxafb build when cpufreq is enabled
  [ARM] fix parenthesis in include/asm-arm/arch-omap/control.h
  [ARM] colibri: fix support for DM9000 ethernet device
  [ARM] arm/kernel/arthur.c: add MODULE_LICENSE
  [ARM] 5037/1: Orion: fix DNS323/Kurobox Pro PCI initialisation
  [ARM] 5034/1: fix arm{925,926,940,946} dma_flush_range() in WT mode
  [ARM] export copy_page
  [ARM] 5026/1: locomo: add .settype for gpio and several small fixes
  ARM: OMAP: Fixed comments on global PRM register usage
  ARM: OMAP: Add PARENT_CONTROLS_CLOCK flag to dpll5_m2_ck
  ARM: OMAP: PRCM fixes to ssi clock handling
  ARM: OMAP: Add fuctional clock enabler for iva2
  ARM: OMAP: Fix 34xx to use correct shift values for gpio2-6 fclks
  ARM: OMAP: Keymap fix for palmte and palmz71
  ARM: OMAP: Fix Unbalanced enable for IRQ in omap mailbox
  ARM: OMAP: DMA: Fix incorrect channel linking
  ARM: OMAP: Warn on disabling clocks with no users
  ARM: OMAP: Add calls to omap2_set_globals_*()
  ARM: OMAP: Update MMC header to fix compile
This commit is contained in:
Linus Torvalds 2008-05-17 15:17:10 -07:00
parent 08c18964a2 dfb0ae0914
commit 29e92f4836
31 changed files with 142 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
arch/arm/common/locomo.c
View File

@ -321,11 +321,42 @@ static void locomo_gpio_unmask_irq(unsigned int irq)
locomo_writel(r, mapbase + LOCOMO_GIE);
}
static int GPIO_IRQ_rising_edge;
static int GPIO_IRQ_falling_edge;
static int locomo_gpio_type(unsigned int irq, unsigned int type)
{
unsigned int mask;
void __iomem *mapbase = get_irq_chip_data(irq);
mask = 1 << (irq - LOCOMO_IRQ_GPIO_START);
if (type == IRQT_PROBE) {
if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
return 0;
type = __IRQT_RISEDGE | __IRQT_FALEDGE;
}
if (type & __IRQT_RISEDGE)
GPIO_IRQ_rising_edge |= mask;
else
GPIO_IRQ_rising_edge &= ~mask;
if (type & __IRQT_FALEDGE)
GPIO_IRQ_falling_edge |= mask;
else
GPIO_IRQ_falling_edge &= ~mask;
locomo_writel(GPIO_IRQ_rising_edge, mapbase + LOCOMO_GRIE);
locomo_writel(GPIO_IRQ_falling_edge, mapbase + LOCOMO_GFIE);
return 0;
}
static struct irq_chip locomo_gpio_chip = {
.name = "LOCOMO-gpio",
.ack = locomo_gpio_ack_irq,
.mask = locomo_gpio_mask_irq,
.unmask = locomo_gpio_unmask_irq,
.name = "LOCOMO-gpio",
.ack = locomo_gpio_ack_irq,
.mask = locomo_gpio_mask_irq,
.unmask = locomo_gpio_unmask_irq,
.set_type = locomo_gpio_type,
};
static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc)
@ -450,22 +481,18 @@ static void locomo_setup_irq(struct locomo *lchip)
set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip);
set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase);
set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler);
set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE);
set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip);
set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase);
set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler);
set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE);
set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip);
set_irq_chip_data(IRQ_LOCOMO_LT_BASE, irqbase);
set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler);
set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE);
set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip);
set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase);
set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler);
set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE);
/* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */
set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip);
@ -488,7 +515,7 @@ static void locomo_setup_irq(struct locomo *lchip)
set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE);
/* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */
for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) {
for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 4; irq++) {
set_irq_chip(irq, &locomo_spi_chip);
set_irq_chip_data(irq, irqbase);
set_irq_handler(irq, handle_edge_irq);
@ -574,20 +601,20 @@ static int locomo_suspend(struct platform_device *dev, pm_message_t state)
save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */
locomo_writel(0x00, lchip->base + LOCOMO_GPO);
save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPICT); /* SPI */
save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPICT); /* SPI */
locomo_writel(0x40, lchip->base + LOCOMO_SPICT);
save->LCM_GPE = locomo_readl(lchip->base + LOCOMO_GPE); /* GPIO */
locomo_writel(0x00, lchip->base + LOCOMO_GPE);
save->LCM_ASD = locomo_readl(lchip->base + LOCOMO_ASD); /* ADSTART */
locomo_writel(0x00, lchip->base + LOCOMO_ASD);
save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPIMD); /* SPI */
locomo_writel(0x3C14, lchip->base + LOCOMO_SPIMD);
save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); /* SPI */
locomo_writel(0x3C14, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);
locomo_writel(0x00, lchip->base + LOCOMO_PAIF);
locomo_writel(0x00, lchip->base + LOCOMO_DAC);
locomo_writel(0x00, lchip->base + LOCOMO_BACKLIGHT + LOCOMO_TC);
if ( (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88) )
if ((locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88))
locomo_writel(0x00, lchip->base + LOCOMO_C32K); /* CLK32 off */
else
/* 18MHz already enabled, so no wait */
@ -616,10 +643,10 @@ static int locomo_resume(struct platform_device *dev)
spin_lock_irqsave(&lchip->lock, flags);
locomo_writel(save->LCM_GPO, lchip->base + LOCOMO_GPO);
locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPICT);
locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPI + LOCOMO_SPICT);
locomo_writel(save->LCM_GPE, lchip->base + LOCOMO_GPE);
locomo_writel(save->LCM_ASD, lchip->base + LOCOMO_ASD);
locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPIMD);
locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);
locomo_writel(0x00, lchip->base + LOCOMO_C32K);
locomo_writel(0x90, lchip->base + LOCOMO_TADC);
@ -688,9 +715,9 @@ __locomo_probe(struct device *me, struct resource *mem, int irq)
/* GPIO */
locomo_writel(0, lchip->base + LOCOMO_GPO);
locomo_writel( (LOCOMO_GPIO(2) | LOCOMO_GPIO(3) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14))
locomo_writel((LOCOMO_GPIO(1) | LOCOMO_GPIO(2) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14))
, lchip->base + LOCOMO_GPE);
locomo_writel( (LOCOMO_GPIO(2) | LOCOMO_GPIO(3) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14))
locomo_writel((LOCOMO_GPIO(1) | LOCOMO_GPIO(2) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14))
, lchip->base + LOCOMO_GPD);
locomo_writel(0, lchip->base + LOCOMO_GIE);
@ -833,7 +860,10 @@ void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir
spin_lock_irqsave(&lchip->lock, flags);
r = locomo_readl(lchip->base + LOCOMO_GPD);
r &= ~bits;
if (dir)
r |= bits;
else
r &= ~bits;
locomo_writel(r, lchip->base + LOCOMO_GPD);
r = locomo_readl(lchip->base + LOCOMO_GPE);

2
arch/arm/kernel/armksyms.c
View File

@ -179,3 +179,5 @@ EXPORT_SYMBOL(_find_next_zero_bit_be);
EXPORT_SYMBOL(_find_first_bit_be);
EXPORT_SYMBOL(_find_next_bit_be);
#endif
EXPORT_SYMBOL(copy_page);

2
arch/arm/kernel/arthur.c
View File

@ -90,3 +90,5 @@ static void __exit arthur_exit(void)
module_init(arthur_init);
module_exit(arthur_exit);
MODULE_LICENSE("GPL");

2
arch/arm/mach-omap1/board-palmte.c
View File

@ -63,7 +63,7 @@ static const int palmte_keymap[] = {
KEY(1, 1, KEY_DOWN),
KEY(1, 2, KEY_UP),
KEY(1, 3, KEY_RIGHT),
KEY(1, 4, KEY_CENTER),
KEY(1, 4, KEY_ENTER),
0,
};

2
arch/arm/mach-omap1/board-palmz71.c
View File

@ -65,7 +65,7 @@ static int palmz71_keymap[] = {
KEY(1, 1, KEY_DOWN),
KEY(1, 2, KEY_UP),
KEY(1, 3, KEY_RIGHT),
KEY(1, 4, KEY_CENTER),
KEY(1, 4, KEY_ENTER),
KEY(2, 0, KEY_CAMERA),
0,
};

1
arch/arm/mach-omap2/board-2430sdp.c
View File

@ -208,6 +208,7 @@ static void __init omap_2430sdp_init(void)
static void __init omap_2430sdp_map_io(void)
{
omap2_set_globals_243x();
omap2_map_common_io();
}

1
arch/arm/mach-omap2/board-apollon.c
View File

@ -394,6 +394,7 @@ static void __init omap_apollon_init(void)
static void __init omap_apollon_map_io(void)
{
omap2_set_globals_242x();
omap2_map_common_io();
}

1
arch/arm/mach-omap2/board-generic.c
View File

@ -65,6 +65,7 @@ static void __init omap_generic_init(void)
static void __init omap_generic_map_io(void)
{
omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */
omap2_map_common_io();
}

1
arch/arm/mach-omap2/board-h4.c
View File

@ -420,6 +420,7 @@ static void __init omap_h4_init(void)
static void __init omap_h4_map_io(void)
{
omap2_set_globals_242x();
omap2_map_common_io();
}

4
arch/arm/mach-omap2/clock.c
View File

@ -205,7 +205,9 @@ static void omap2_clk_wait_ready(struct clk *clk)
/* REVISIT: What are the appropriate exclusions for 34XX? */
/* OMAP3: ignore DSS-mod clocks */
if (cpu_is_omap34xx() &&
(((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0)))
(((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) &&
clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
return;
/* Check if both functional and interface clocks

21
arch/arm/mach-omap2/clock34xx.h
View File

@ -836,7 +836,8 @@ static struct clk dpll5_m2_ck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
.clksel_mask = OMAP3430ES2_DIV_120M_MASK,
.clksel = div16_dpll5_clksel,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.recalc = &omap2_clksel_recalc,
};
@ -1046,12 +1047,13 @@ static struct clk iva2_ck = {
.name = "iva2_ck",
.parent = &dpll2_m2_ck,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
OMAP3430_CM_IDLEST_PLL),
.clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
.clksel = iva2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@ -1836,7 +1838,8 @@ static struct clk omapctrl_ick = {
static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.recalc = &followparent_recalc,
};
@ -2344,7 +2347,7 @@ static struct clk gpio6_fck = {
.name = "gpio6_fck",
.parent = &per_32k_alwon_fck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.recalc = &followparent_recalc,
};
@ -2353,7 +2356,7 @@ static struct clk gpio5_fck = {
.name = "gpio5_fck",
.parent = &per_32k_alwon_fck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.recalc = &followparent_recalc,
};
@ -2362,7 +2365,7 @@ static struct clk gpio4_fck = {
.name = "gpio4_fck",
.parent = &per_32k_alwon_fck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.recalc = &followparent_recalc,
};
@ -2371,7 +2374,7 @@ static struct clk gpio3_fck = {
.name = "gpio3_fck",
.parent = &per_32k_alwon_fck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.recalc = &followparent_recalc,
};
@ -2380,7 +2383,7 @@ static struct clk gpio2_fck = {
.name = "gpio2_fck",
.parent = &per_32k_alwon_fck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
.recalc = &followparent_recalc,
};

1
arch/arm/mach-omap2/cm-regbits-34xx.h
View File

@ -56,6 +56,7 @@
/* CM_FCLKEN_IVA2 */
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0)
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
/* CM_CLKEN_PLL_IVA2 */
#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8

25
arch/arm/mach-omap2/mailbox.c
View File

@ -70,6 +70,9 @@ struct omap_mbox2_priv {
static struct clk *mbox_ick_handle;
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
static inline unsigned int mbox_read_reg(unsigned int reg)
{
return __raw_readl(mbox_base + reg);
@ -81,7 +84,7 @@ static inline void mbox_write_reg(unsigned int val, unsigned int reg)
}
/* Mailbox H/W preparations */
static inline int omap2_mbox_startup(struct omap_mbox *mbox)
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
unsigned int l;
@ -97,38 +100,40 @@ static inline int omap2_mbox_startup(struct omap_mbox *mbox)
l |= 0x00000011;
mbox_write_reg(l, MAILBOX_SYSCONFIG);
omap2_mbox_enable_irq(mbox, IRQ_RX);
return 0;
}
static inline void omap2_mbox_shutdown(struct omap_mbox *mbox)
static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
clk_disable(mbox_ick_handle);
clk_put(mbox_ick_handle);
}
/* Mailbox FIFO handle functions */
static inline mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
{
struct omap_mbox2_fifo *fifo =
&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
return (mbox_msg_t) mbox_read_reg(fifo->msg);
}
static inline void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
{
struct omap_mbox2_fifo *fifo =
&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
mbox_write_reg(msg, fifo->msg);
}
static inline int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
{
struct omap_mbox2_fifo *fifo =
&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
return (mbox_read_reg(fifo->msg_stat) == 0);
}
static inline int omap2_mbox_fifo_full(struct omap_mbox *mbox)
static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
{
struct omap_mbox2_fifo *fifo =
&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
@ -136,7 +141,7 @@ static inline int omap2_mbox_fifo_full(struct omap_mbox *mbox)
}
/* Mailbox IRQ handle functions */
static inline void omap2_mbox_enable_irq(struct omap_mbox *mbox,
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
{
struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
@ -147,7 +152,7 @@ static inline void omap2_mbox_enable_irq(struct omap_mbox *mbox,
mbox_write_reg(l, p->irqenable);
}
static inline void omap2_mbox_disable_irq(struct omap_mbox *mbox,
static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
{
struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
@ -158,7 +163,7 @@ static inline void omap2_mbox_disable_irq(struct omap_mbox *mbox,
mbox_write_reg(l, p->irqenable);
}
static inline void omap2_mbox_ack_irq(struct omap_mbox *mbox,
static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
{
struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
@ -167,7 +172,7 @@ static inline void omap2_mbox_ack_irq(struct omap_mbox *mbox,
mbox_write_reg(bit, p->irqstatus);
}
static inline int omap2_mbox_is_irq(struct omap_mbox *mbox,
static int omap2_mbox_is_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
{
struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;

2
arch/arm/mach-omap2/prm.h
View File

@ -30,7 +30,7 @@
/*
* Architecture-specific global PRM registers
* Use prm_{read,write}_reg() with these registers.
* Use __raw_{read,write}l() with these registers.
*
* With a few exceptions, these are the register names beginning with
* PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the

2
arch/arm/mach-orion5x/dns323-setup.c
View File

@ -58,7 +58,7 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci dns323_pci __initdata = {
.nr_controllers = 1,
.nr_controllers = 2,
.swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,

2
arch/arm/mach-orion5x/kurobox_pro-setup.c
View File

@ -138,7 +138,7 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci kurobox_pro_pci __initdata = {
.nr_controllers = 1,
.nr_controllers = 2,
.swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,

3
arch/arm/mach-pxa/colibri.c
View File

@ -98,7 +98,7 @@ static struct resource dm9000_resources[] = {
[2] = {
.start = COLIBRI_ETH_IRQ,
.end = COLIBRI_ETH_IRQ,
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
},
};
@ -119,7 +119,6 @@ static void __init colibri_init(void)
/* DM9000 LAN */
pxa_gpio_mode(GPIO78_nCS_2_MD);
pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
set_irq_type(COLIBRI_ETH_IRQ, IRQT_FALLING);
platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices));
}

1
arch/arm/mach-pxa/spitz.c
View File

@ -38,6 +38,7 @@
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/pxa27x-udc.h>
#include <asm/arch/irda.h>
#include <asm/arch/mmc.h>
#include <asm/arch/ohci.h>

2
arch/arm/mm/proc-arm925.S
View File

@ -332,7 +332,7 @@ ENTRY(arm925_dma_flush_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
#else
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
#endif
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1

2
arch/arm/mm/proc-arm926.S
View File

@ -295,7 +295,7 @@ ENTRY(arm926_dma_flush_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
#else
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
#endif
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1

2
arch/arm/mm/proc-arm940.S
View File

@ -222,7 +222,7 @@ ENTRY(arm940_dma_flush_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
#else
mcr p15, 0, r3, c7, c10, 2 @ clean D entry
mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
#endif
subs r3, r3, #1 << 26
bcs 2b @ entries 63 to 0

2
arch/arm/mm/proc-arm946.S
View File

@ -265,7 +265,7 @@ ENTRY(arm946_dma_flush_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
#else
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
#endif
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1

10
arch/arm/plat-omap/clock.c
View File

@ -134,9 +134,17 @@ void clk_disable(struct clk *clk)
return;
spin_lock_irqsave(&clockfw_lock, flags);
BUG_ON(clk->usecount == 0);
if (clk->usecount == 0) {
printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
clk->name);
WARN_ON(1);
goto out;
}
if (arch_clock->clk_disable)
arch_clock->clk_disable(clk);
out:
spin_unlock_irqrestore(&clockfw_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

2
arch/arm/plat-omap/dma.c
View File

@ -604,6 +604,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
chan->data = data;
#ifndef CONFIG_ARCH_OMAP1
chan->chain_id = -1;
chan->next_linked_ch = -1;
#endif
chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
@ -1087,7 +1088,6 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
printk(KERN_ERR "omap_dma: Request failed %d\n", err);
return err;
}
dma_chan[channels[i]].next_linked_ch = -1;
dma_chan[channels[i]].prev_linked_ch = -1;
dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;

1
arch/arm/plat-omap/mailbox.c
View File

@ -355,7 +355,6 @@ static int omap_mbox_init(struct omap_mbox *mbox)
"failed to register mailbox interrupt:%d\n", ret);
goto fail_request_irq;
}
enable_mbox_irq(mbox, IRQ_RX);
mq = mbox_queue_alloc(mbox, mbox_txq_fn, mbox_tx_work);
if (!mq) {

5
drivers/video/pxafb.c
View File

@ -355,9 +355,8 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
}
#ifdef CONFIG_CPU_FREQ
pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
pxafb_display_dma_period(var),
get_clk_frequency_khz(0));
pr_debug("pxafb: dma period = %d ps\n",
pxafb_display_dma_period(var));
#endif
return 0;

4
include/asm-arm/arch-omap/common.h
View File

@ -47,4 +47,8 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
}
#endif
void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void);
void omap2_set_globals_343x(void);
#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */

2
include/asm-arm/arch-omap/control.h
View File

@ -80,7 +80,7 @@
#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074
#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)

24
include/asm-arm/arch-omap/mmc.h
View File

@ -15,21 +15,16 @@
#include <linux/device.h>
#include <linux/mmc/host.h>
#include <asm/arch/board.h>
#define OMAP_MMC_MAX_SLOTS 2
struct omap_mmc_platform_data {
struct omap_mmc_conf conf;
unsigned enabled:1;
/* number of slots on board */
unsigned nr_slots:2;
/* nomux means "standard" muxing is wrong on this board, and that
* board-specific code handled it before common init logic.
*/
unsigned nomux:1;
/* 4 wire signaling is optional, and is only used for SD/SDIO and
* MMCv4 */
unsigned wire4:1;
/* set if your board has components or wiring that limits the
* maximum frequency on the MMC bus */
unsigned int max_freq;
@ -40,6 +35,11 @@ struct omap_mmc_platform_data {
* not supported */
int (* init)(struct device *dev);
void (* cleanup)(struct device *dev);
void (* shutdown)(struct device *dev);
/* To handle board related suspend/resume functionality for MMC */
int (*suspend)(struct device *dev, int slot);
int (*resume)(struct device *dev, int slot);
struct omap_mmc_slot_data {
int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
@ -56,13 +56,19 @@ struct omap_mmc_platform_data {
const char *name;
u32 ocr_mask;
/* Card detection IRQs */
int card_detect_irq;
int (* card_detect)(int irq);
unsigned int ban_openended:1;
} slots[OMAP_MMC_MAX_SLOTS];
};
extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info);
/* called from board-specific card detection service routine */
extern void omap_mmc_notify_card_detect(struct device *dev, int slot, int detected);
extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
#endif

2
include/asm-arm/arch-sa1100/irqs.h
View File

@ -141,7 +141,7 @@
#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17)
#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18)
#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19)
#define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20)
#define IRQ_LOCOMO_SPI_REND (IRQ_BOARD_END + 20)
#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21)
/*

19
include/asm-arm/hardware/locomo.h
View File

@ -58,6 +58,11 @@
#define LOCOMO_SPIMD 0x00 /* SPI mode setting */
#define LOCOMO_SPICT 0x04 /* SPI mode control */
#define LOCOMO_SPIST 0x08 /* SPI status */
#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
#define LOCOMO_SPI_REND (1 << 2) /* Receive end bit */
#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
#define LOCOMO_SPI_RFR (1) /* read buffer bit */
#define LOCOMO_SPIIS 0x10 /* SPI interrupt status */
#define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */
#define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */
@ -66,16 +71,12 @@
#define LOCOMO_SPIRD 0x24 /* SPI receive data read */
#define LOCOMO_SPITS 0x28 /* SPI transfer data shift */
#define LOCOMO_SPIRS 0x2C /* SPI receive data shift */
#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
#define LOCOMO_SPI_OVRN (1 << 2) /* Over Run bit */
#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
#define LOCOMO_SPI_RFR (1) /* read buffer bit */
/* GPIO */
#define LOCOMO_GPD 0x90 /* GPIO direction */
#define LOCOMO_GPE 0x94 /* GPIO input enable */
#define LOCOMO_GPL 0x98 /* GPIO level */
#define LOCOMO_GPO 0x9c /* GPIO out data setteing */
#define LOCOMO_GPO 0x9c /* GPIO out data setting */
#define LOCOMO_GRIE 0xa0 /* GPIO rise detection */
#define LOCOMO_GFIE 0xa4 /* GPIO fall detection */
#define LOCOMO_GIS 0xa8 /* GPIO edge detection status */
@ -96,6 +97,9 @@
#define LOCOMO_GPIO_DAC_SDATA LOCOMO_GPIO(10)
#define LOCOMO_GPIO_DAC_SCK LOCOMO_GPIO(11)
#define LOCOMO_GPIO_DAC_SLOAD LOCOMO_GPIO(12)
#define LOCOMO_GPIO_CARD_DETECT LOCOMO_GPIO(13)
#define LOCOMO_GPIO_WRITE_PROT LOCOMO_GPIO(14)
#define LOCOMO_GPIO_CARD_POWER LOCOMO_GPIO(15)
/* Start the definitions of the devices. Each device has an initial
* base address and a series of offsets from that base address. */
@ -122,7 +126,7 @@
/* Audio controller */
#define LOCOMO_AUDIO 0x54
#define LOCOMO_ACC 0x00 /* Audio clock */
#define LOCOMO_PAIF 0x7C /* PCM audio interface */
#define LOCOMO_PAIF 0xD0 /* PCM audio interface */
/* Audio clock */
#define LOCOMO_ACC_XON 0x80
#define LOCOMO_ACC_XEN 0x40
@ -162,7 +166,7 @@ extern struct bus_type locomo_bus_type;
#define LOCOMO_DEVID_AUDIO 3
#define LOCOMO_DEVID_LED 4
#define LOCOMO_DEVID_UART 5
#define LOCOMO_DEVID_SPI 6
#define LOCOMO_DEVID_SPI 6
struct locomo_dev {
struct device dev;
@ -204,7 +208,6 @@ int locomo_gpio_read_level(struct device *dev, unsigned int bits);
int locomo_gpio_read_output(struct device *dev, unsigned int bits);
void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set);
/* M62332 control function */
void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);