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plat-mxc/ehci.c: fix compile breakage 

commits 2eb42d5c28 and
9e1dde3387 renamed some defines
but didn't fix all the places where these defines are used
leading to a compile failure for USB on i.MX31, 35 and 27.

Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Eric Bénard 2010-11-27 09:15:38 +01:00 committed by Sascha Hauer
parent 4e5cf41eeb
commit 29bb6afcb0
2 changed files with 8 additions and 8 deletions
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12
arch/arm/plat-mxc/ehci.c
View File

@ -115,7 +115,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
#endif /* if defined(CONFIG_SOC_IMX25) */ #endif /* if defined(CONFIG_SOC_IMX25) */
#if defined(CONFIG_ARCH_MX3) #if defined(CONFIG_ARCH_MX3)
if (cpu_is_mx31()) { if (cpu_is_mx31()) {
v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET)); USBCTRL_OTGBASE_OFFSET));
switch (port) { switch (port) {
@ -153,13 +153,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
return -EINVAL; return -EINVAL;
} }
writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET)); USBCTRL_OTGBASE_OFFSET));
return 0; return 0;
} }
if (cpu_is_mx35()) { if (cpu_is_mx35()) {
v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET)); USBCTRL_OTGBASE_OFFSET));
switch (port) { switch (port) {
@ -196,7 +196,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
return -EINVAL; return -EINVAL;
} }
writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET)); USBCTRL_OTGBASE_OFFSET));
return 0; return 0;
} }
@ -206,7 +206,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
/* On i.MX27 we can use the i.MX31 USBCTRL bits, they /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
* are identical * are identical
*/ */
v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET)); USBCTRL_OTGBASE_OFFSET));
switch (port) { switch (port) {
case 0: /* OTG port */ case 0: /* OTG port */
@ -241,7 +241,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
default: default:
return -EINVAL; return -EINVAL;
} }
writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET)); USBCTRL_OTGBASE_OFFSET));
return 0; return 0;
} }

4
drivers/usb/gadget/fsl_mxc_udc.c
View File

@ -93,9 +93,9 @@ void fsl_udc_clk_finalize(struct platform_device *pdev)
/* workaround ENGcm09152 for i.MX35 */ /* workaround ENGcm09152 for i.MX35 */
if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) { if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
USBPHYCTRL_OTGBASE_OFFSET)); USBPHYCTRL_OTGBASE_OFFSET));
writel(v | USBPHYCTRL_EVDO, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + writel(v | USBPHYCTRL_EVDO, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
USBPHYCTRL_OTGBASE_OFFSET)); USBPHYCTRL_OTGBASE_OFFSET));
} }
#endif #endif