sata_mv: use new sata phy register settings for new devices
Marvell's new SoC (65 nano) needs different settings for its SATA PHY registers. Tested-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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@ -293,6 +293,10 @@ enum {
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FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
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FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
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PHY_MODE9_GEN2 = 0x398,
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PHY_MODE9_GEN1 = 0x39c,
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PHYCFG_OFS = 0x3a0, /* only in 65n devices */
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MV5_PHY_MODE = 0x74,
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MV5_LTMODE = 0x30,
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MV5_PHY_CTL = 0x0C,
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@ -609,6 +613,8 @@ static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
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static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
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void __iomem *mmio);
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static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
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static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
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void __iomem *mmio, unsigned int port);
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static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
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static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
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unsigned int port_no);
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@ -807,6 +813,14 @@ static const struct mv_hw_ops mv_soc_ops = {
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.reset_bus = mv_soc_reset_bus,
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};
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static const struct mv_hw_ops mv_soc_65n_ops = {
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.phy_errata = mv_soc_65n_phy_errata,
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.enable_leds = mv_soc_enable_leds,
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.reset_hc = mv_soc_reset_hc,
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.reset_flash = mv_soc_reset_flash,
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.reset_bus = mv_soc_reset_bus,
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};
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/*
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* Functions
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*/
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@ -3397,6 +3411,53 @@ static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
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return;
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}
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static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
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void __iomem *mmio, unsigned int port)
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{
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void __iomem *port_mmio = mv_port_base(mmio, port);
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u32 reg;
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reg = readl(port_mmio + PHY_MODE3);
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reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
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reg |= (0x1 << 27);
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reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
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reg |= (0x1 << 29);
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writel(reg, port_mmio + PHY_MODE3);
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reg = readl(port_mmio + PHY_MODE4);
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reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
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reg |= (0x1 << 16);
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writel(reg, port_mmio + PHY_MODE4);
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reg = readl(port_mmio + PHY_MODE9_GEN2);
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reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
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reg |= 0x8;
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reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
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writel(reg, port_mmio + PHY_MODE9_GEN2);
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reg = readl(port_mmio + PHY_MODE9_GEN1);
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reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
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reg |= 0x8;
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reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
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writel(reg, port_mmio + PHY_MODE9_GEN1);
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}
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/**
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* soc_is_65 - check if the soc is 65 nano device
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*
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* Detect the type of the SoC, this is done by reading the PHYCFG_OFS
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* register, this register should contain non-zero value and it exists only
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* in the 65 nano devices, when reading it from older devices we get 0.
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*/
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static bool soc_is_65n(struct mv_host_priv *hpriv)
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{
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void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
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if (readl(port0_mmio + PHYCFG_OFS))
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return true;
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return false;
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}
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static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
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{
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u32 ifcfg = readl(port_mmio + SATA_IFCFG);
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@ -3737,7 +3798,10 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
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}
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break;
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case chip_soc:
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hpriv->ops = &mv_soc_ops;
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if (soc_is_65n(hpriv))
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hpriv->ops = &mv_soc_65n_ops;
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else
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hpriv->ops = &mv_soc_ops;
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hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
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MV_HP_ERRATA_60X1C0;
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break;
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@ -3800,7 +3864,8 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
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n_hc = mv_get_hc_count(host->ports[0]->flags);
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for (port = 0; port < host->n_ports; port++)
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hpriv->ops->read_preamp(hpriv, port, mmio);
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if (hpriv->ops->read_preamp)
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hpriv->ops->read_preamp(hpriv, port, mmio);
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rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
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if (rc)
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