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vme: tsi148: CR/CSR logic arround the wrong way 

The logic in the init routine for the TSI148 is inverted. It isn't switching
on the CR/CSR space when it should be and is reporting it's on when its not.

Correct the logic to do the right thing.

Reported-by: De Roo, Steven <steven.deroo@arcelormittal.com>
Signed-off-by: Martyn Welch <martyn.welch@ge.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Martyn Welch 2013-06-11 17:03:14 +01:00 committed by Greg Kroah-Hartman
parent e31c51e4a1
commit 2981795cc0
1 changed files with 4 additions and 3 deletions
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7
drivers/vme/bridges/vme_tsi148.c
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@ -2300,12 +2300,13 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
if (crat & TSI148_LCSR_CRAT_EN) {
if (crat & TSI148_LCSR_CRAT_EN)
dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
else {
dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
iowrite32be(crat | TSI148_LCSR_CRAT_EN,
bridge->base + TSI148_LCSR_CRAT);
} else
dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
}
/* If we want flushed, error-checked writes, set up a window
* over the CR/CSR registers. We read from here to safely flush