arm: dts: calxeda: Basic DT file fixes
The .dts files for the Calxeda machines are quite old, so carry some sloppy mistakes that the DT schema checker will complain about. Fix those issues, they should not have any effect on functionality. Link: https://lore.kernel.org/r/20200228135106.220620-2-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@ -13,7 +13,6 @@
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compatible = "calxeda,ecx-2000";
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#address-cells = <2>;
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#size-cells = <2>;
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clock-ranges;
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cpus {
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#address-cells = <1>;
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@ -83,8 +82,7 @@
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#size-cells = <0>;
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#address-cells = <1>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <1 9 0xf04>;
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reg = <0xfff11000 0x1000>,
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@ -13,7 +13,6 @@
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compatible = "calxeda,highbank";
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#address-cells = <1>;
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#size-cells = <1>;
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clock-ranges;
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cpus {
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#address-cells = <1>;
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@ -96,7 +95,7 @@
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};
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};
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memory {
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memory@0 {
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name = "memory";
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device_type = "memory";
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reg = <0x00000000 0xff900000>;
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@ -128,14 +127,12 @@
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#size-cells = <0>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xfff11000 0x1000>,
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<0xfff10100 0x100>;
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};
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L2: l2-cache {
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xfff12000 0x1000>;
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interrupts = <0 70 4>;
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