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riscv: dts: fix apb timer clock bug 

driver: clk: by default, the timer clock is turned off

Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
This commit is contained in:
haijiao.liu 2023-07-14 20:51:30 +08:00 committed by Xiaoguang Xing
parent d55addb9f3
commit 28afded752
3 changed files with 32 additions and 20 deletions
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4
arch/riscv/boot/dts/sophgo/mango.dtsi
View File

@ -519,7 +519,7 @@
interrupt-parent = <&intc>;
interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_LEVEL_HIGH>;
reg = <0x70 0x30003000 0x0 0x14>;
clocks = <&div_clk GATE_CLK_APB_TIMER>;
clocks = <&div_clk GATE_CLK_TIMER1>;
clock-names = "timer";
clk-drv-rating = <300>;
};
@ -529,7 +529,7 @@
interrupt-parent = <&intc>;
interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_LEVEL_HIGH>;
reg = <0x70 0x30003014 0x0 0x10>;
clocks = <&div_clk GATE_CLK_APB_TIMER>;
clocks = <&div_clk GATE_CLK_TIMER2>;
clock-names = "timer";
clk-drv-rating = <300>;
};

16
arch/riscv/include/asm/vdso/gettimeofday.h
View File

@ -77,11 +77,23 @@ static __always_inline const struct vdso_data *__arch_get_vdso_data(void)
}
#ifdef CONFIG_SOPHGO_MULTI_CHIP_CLOCK_SYNC
static inline bool arch_vdso_clocksource_ok(const struct vdso_data *vd)
static inline bool sophgo_vdso_hres_capable(void)
{
return false;
}
#define vdso_clocksource_ok arch_vdso_clocksource_ok
#define __arch_vdso_hres_capable sophgo_vdso_hres_capable
static inline bool sophgo_vdso_clocksource_ok(const struct vdso_data *vd)
{
return false;
}
#define vdso_clocksource_ok sophgo_vdso_clocksource_ok
static inline bool sophgo_vdso_cycles_ok(u64 cycles)
{
return false;
}
#define vdso_cycles_ok sophgo_vdso_cycles_ok
#endif
#ifdef CONFIG_TIME_NS

32
drivers/clk/sophgo/clk-mango.c
View File

@ -265,21 +265,21 @@ static const struct mango_gate_clock s0_gate_clks[] = {
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 5, 0 },
{ GATE_CLK_TIMER1, "clk_gate_timer1", "clk_div_timer1",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 12, 0 },
CLK_SET_RATE_PARENT, 0x2000, 12, 0 },
{ GATE_CLK_TIMER2, "clk_gate_timer2", "clk_div_timer2",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 13, 0 },
CLK_SET_RATE_PARENT, 0x2000, 13, 0 },
{ GATE_CLK_TIMER3, "clk_gate_timer3", "clk_div_timer3",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 14, 0 },
CLK_SET_RATE_PARENT, 0x2000, 14, 0 },
{ GATE_CLK_TIMER4, "clk_gate_timer4", "clk_div_timer4",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 15, 0 },
CLK_SET_RATE_PARENT, 0x2000, 15, 0 },
{ GATE_CLK_TIMER5, "clk_gate_timer5", "clk_div_timer5",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 16, 0 },
CLK_SET_RATE_PARENT, 0x2000, 16, 0 },
{ GATE_CLK_TIMER6, "clk_gate_timer6", "clk_div_timer6",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 17, 0 },
CLK_SET_RATE_PARENT, 0x2000, 17, 0 },
{ GATE_CLK_TIMER7, "clk_gate_timer7", "clk_div_timer7",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 18, 0 },
CLK_SET_RATE_PARENT, 0x2000, 18, 0 },
{ GATE_CLK_TIMER8, "clk_gate_timer8", "clk_div_timer8",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 19, 0 },
CLK_SET_RATE_PARENT, 0x2000, 19, 0 },
{ GATE_CLK_100K_EMMC, "clk_gate_100k_emmc", "clk_div_100k_emmc",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 4, 0 },
{ GATE_CLK_100K_SD, "clk_gate_100k_sd", "clk_div_100k_sd",
@ -583,21 +583,21 @@ static const struct mango_gate_clock s1_gate_clks[] = {
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 5, 0 },
{ GATE_CLK_TIMER1, "s1_clk_gate_timer1", "s1_clk_div_timer1",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 12, 0 },
CLK_SET_RATE_PARENT, 0x2000, 12, 0 },
{ GATE_CLK_TIMER2, "s1_clk_gate_timer2", "s1_clk_div_timer2",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 13, 0 },
CLK_SET_RATE_PARENT, 0x2000, 13, 0 },
{ GATE_CLK_TIMER3, "s1_clk_gate_timer3", "s1_clk_div_timer3",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 14, 0 },
CLK_SET_RATE_PARENT, 0x2000, 14, 0 },
{ GATE_CLK_TIMER4, "s1_clk_gate_timer4", "s1_clk_div_timer4",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 15, 0 },
CLK_SET_RATE_PARENT, 0x2000, 15, 0 },
{ GATE_CLK_TIMER5, "s1_clk_gate_timer5", "s1_clk_div_timer5",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 16, 0 },
CLK_SET_RATE_PARENT, 0x2000, 16, 0 },
{ GATE_CLK_TIMER6, "s1_clk_gate_timer6", "s1_clk_div_timer6",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 17, 0 },
CLK_SET_RATE_PARENT, 0x2000, 17, 0 },
{ GATE_CLK_TIMER7, "s1_clk_gate_timer7", "s1_clk_div_timer7",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 18, 0 },
CLK_SET_RATE_PARENT, 0x2000, 18, 0 },
{ GATE_CLK_TIMER8, "s1_clk_gate_timer8", "s1_clk_div_timer8",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 19, 0 },
CLK_SET_RATE_PARENT, 0x2000, 19, 0 },
{ GATE_CLK_100K_EMMC, "s1_clk_gate_100k_emmc", "s1_clk_div_100k_emmc",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 4, 0 },
{ GATE_CLK_100K_SD, "s1_clk_gate_100k_sd", "s1_clk_div_100k_sd",