usb: dwc2: add hibernation core parameter
dwc2 may not be able to exit from hibernation if the hardware does not provide a way to detect resume signalling in this state. Thus, add the possibility to disable hibernation feature. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -342,6 +342,9 @@ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->core_params->hibernation)
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return -ENOTSUPP;
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pcgcctl = readl(hsotg->regs + PCGCTL);
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pcgcctl &= ~PCGCTL_STOPPCLK;
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writel(pcgcctl, hsotg->regs + PCGCTL);
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@ -392,6 +395,9 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->core_params->hibernation)
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return -ENOTSUPP;
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/* Backup all registers */
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ret = dwc2_backup_global_registers(hsotg);
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if (ret) {
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@ -2998,6 +3004,23 @@ static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
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hsotg->core_params->external_id_pin_ctl = val;
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}
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static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
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int val)
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{
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if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
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if (val >= 0) {
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dev_err(hsotg->dev,
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"'%d' invalid for parameter hibernation\n",
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val);
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dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
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}
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val = 0;
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dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
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}
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hsotg->core_params->hibernation = val;
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}
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/*
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* This function is called during module intialization to pass module parameters
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* for the DWC_otg core.
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@ -3043,6 +3066,7 @@ void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
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dwc2_set_param_otg_ver(hsotg, params->otg_ver);
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dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
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dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
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dwc2_set_param_hibernation(hsotg, params->hibernation);
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}
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/**
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@ -336,6 +336,12 @@ enum dwc2_ep0_state {
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* case.
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* 0 - No (default)
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* 1 - Yes
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* @hibernation: Specifies whether the controller support hibernation.
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* If hibernation is enabled, the controller will enter
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* hibernation in both peripheral and host mode when
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* needed.
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* 0 - No (default)
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* 1 - Yes
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*
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* The following parameters may be specified when starting the module. These
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* parameters define how the DWC_otg controller should be configured. A
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@ -374,6 +380,7 @@ struct dwc2_core_params {
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int ahbcfg;
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int uframe_sched;
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int external_id_pin_ctl;
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int hibernation;
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};
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/**
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@ -347,7 +347,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
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dctl &= ~DCTL_RMTWKUPSIG;
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writel(dctl, hsotg->regs + DCTL);
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ret = dwc2_exit_hibernation(hsotg, true);
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if (ret)
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if (ret && (ret != -ENOTSUPP))
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dev_err(hsotg->dev, "exit hibernation failed\n");
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call_gadget(hsotg, resume);
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@ -428,6 +428,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
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ret = dwc2_enter_hibernation(hsotg);
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if (ret) {
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if (ret != -ENOTSUPP)
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dev_err(hsotg->dev,
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"enter hibernation failed\n");
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goto skip_power_saving;
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@ -78,6 +78,7 @@ static const struct dwc2_core_params params_bcm2835 = {
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.ahbcfg = 0x10,
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.uframe_sched = 0,
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.external_id_pin_ctl = -1,
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.hibernation = -1,
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};
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static const struct dwc2_core_params params_rk3066 = {
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@ -107,6 +108,7 @@ static const struct dwc2_core_params params_rk3066 = {
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.ahbcfg = 0x7, /* INCR16 */
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.uframe_sched = -1,
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.external_id_pin_ctl = -1,
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.hibernation = -1,
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};
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/**
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