nios2: Kernel booting and initialization
This patch adds the kernel booting and the initial setup code. Signed-off-by: Ley Foon Tan <lftan@altera.com>
This commit is contained in:
Ley Foon Tan
parent
39b505cb79
commit
27d22413e6
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/*
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* Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
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* Copyright (C) 2004 Microtronix Datacom Ltd.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef _ASM_NIOS2_ENTRY_H
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#define _ASM_NIOS2_ENTRY_H
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#ifdef __ASSEMBLY__
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#include <asm/processor.h>
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#include <asm/registers.h>
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#include <asm/asm-offsets.h>
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/*
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* Standard Nios2 interrupt entry and exit macros.
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* Must be called with interrupts disabled.
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*/
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.macro SAVE_ALL
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rdctl r24, estatus
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andi r24, r24, ESTATUS_EU
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beq r24, r0, 1f /* In supervisor mode, already on kernel stack */
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movia r24, _current_thread /* Switch to current kernel stack */
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ldw r24, 0(r24) /* using the thread_info */
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addi r24, r24, THREAD_SIZE-PT_REGS_SIZE
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stw sp, PT_SP(r24) /* Save user stack before changing */
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mov sp, r24
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br 2f
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1 : mov r24, sp
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addi sp, sp, -PT_REGS_SIZE /* Backup the kernel stack pointer */
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stw r24, PT_SP(sp)
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2 : stw r1, PT_R1(sp)
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stw r2, PT_R2(sp)
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stw r3, PT_R3(sp)
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stw r4, PT_R4(sp)
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stw r5, PT_R5(sp)
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stw r6, PT_R6(sp)
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stw r7, PT_R7(sp)
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stw r8, PT_R8(sp)
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stw r9, PT_R9(sp)
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stw r10, PT_R10(sp)
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stw r11, PT_R11(sp)
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stw r12, PT_R12(sp)
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stw r13, PT_R13(sp)
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stw r14, PT_R14(sp)
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stw r15, PT_R15(sp)
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stw r2, PT_ORIG_R2(sp)
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stw r7, PT_ORIG_R7(sp)
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stw ra, PT_RA(sp)
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stw fp, PT_FP(sp)
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stw gp, PT_GP(sp)
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rdctl r24, estatus
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stw r24, PT_ESTATUS(sp)
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stw ea, PT_EA(sp)
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.endm
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.macro RESTORE_ALL
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ldw r1, PT_R1(sp) /* Restore registers */
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ldw r2, PT_R2(sp)
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ldw r3, PT_R3(sp)
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ldw r4, PT_R4(sp)
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ldw r5, PT_R5(sp)
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ldw r6, PT_R6(sp)
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ldw r7, PT_R7(sp)
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ldw r8, PT_R8(sp)
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ldw r9, PT_R9(sp)
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ldw r10, PT_R10(sp)
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ldw r11, PT_R11(sp)
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ldw r12, PT_R12(sp)
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ldw r13, PT_R13(sp)
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ldw r14, PT_R14(sp)
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ldw r15, PT_R15(sp)
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ldw ra, PT_RA(sp)
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ldw fp, PT_FP(sp)
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ldw gp, PT_GP(sp)
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ldw r24, PT_ESTATUS(sp)
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wrctl estatus, r24
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ldw ea, PT_EA(sp)
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ldw sp, PT_SP(sp) /* Restore sp last */
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.endm
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.macro SAVE_SWITCH_STACK
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addi sp, sp, -SWITCH_STACK_SIZE
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stw r16, SW_R16(sp)
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stw r17, SW_R17(sp)
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stw r18, SW_R18(sp)
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stw r19, SW_R19(sp)
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stw r20, SW_R20(sp)
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stw r21, SW_R21(sp)
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stw r22, SW_R22(sp)
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stw r23, SW_R23(sp)
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stw fp, SW_FP(sp)
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stw gp, SW_GP(sp)
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stw ra, SW_RA(sp)
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.endm
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.macro RESTORE_SWITCH_STACK
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ldw r16, SW_R16(sp)
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ldw r17, SW_R17(sp)
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ldw r18, SW_R18(sp)
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ldw r19, SW_R19(sp)
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ldw r20, SW_R20(sp)
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ldw r21, SW_R21(sp)
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ldw r22, SW_R22(sp)
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ldw r23, SW_R23(sp)
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ldw fp, SW_FP(sp)
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ldw gp, SW_GP(sp)
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ldw ra, SW_RA(sp)
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addi sp, sp, SWITCH_STACK_SIZE
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_NIOS2_ENTRY_H */
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@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef _ASM_NIOS2_SETUP_H
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#define _ASM_NIOS2_SETUP_H
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#include <asm-generic/setup.h>
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#ifndef __ASSEMBLY__
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#ifdef __KERNEL__
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extern char exception_handler_hook[];
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extern char fast_handler[];
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extern char fast_handler_end[];
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extern void pagetable_init(void);
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extern void setup_early_printk(void);
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#endif/* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_NIOS2_SETUP_H */
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@ -0,0 +1,175 @@
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/*
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* Copyright (C) 2009 Wind River Systems Inc
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* Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
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* Copyright (C) 2004 Microtronix Datacom Ltd
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* Copyright (C) 2001 Vic Phillips, Microtronix Datacom Ltd.
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*
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* Based on head.S for Altera's Excalibur development board with nios processor
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*
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* Based on the following from the Excalibur sdk distribution:
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* NA_MemoryMap.s, NR_JumpToStart.s, NR_Setup.s, NR_CWPManager.s
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/page.h>
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#include <asm/asm-offsets.h>
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#include <asm/asm-macros.h>
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/*
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* ZERO_PAGE is a special page that is used for zero-initialized
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* data and COW.
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*/
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.data
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.global empty_zero_page
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.align 12
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empty_zero_page:
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.space PAGE_SIZE
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/*
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* This global variable is used as an extension to the nios'
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* STATUS register to emulate a user/supervisor mode.
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*/
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.data
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.align 2
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.set noat
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.global _current_thread
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_current_thread:
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.long 0
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/*
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* Input(s): passed from u-boot
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* r4 - Optional pointer to a board information structure.
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* r5 - Optional pointer to the physical starting address of the init RAM
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* disk.
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* r6 - Optional pointer to the physical ending address of the init RAM
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* disk.
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* r7 - Optional pointer to the physical starting address of any kernel
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* command-line parameters.
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*/
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/*
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* First executable code - detected and jumped to by the ROM bootstrap
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* if the code resides in flash (looks for "Nios" at offset 0x0c from
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* the potential executable image).
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*/
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__HEAD
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ENTRY(_start)
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wrctl status, r0 /* Disable interrupts */
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/* Initialize all cache lines within the instruction cache */
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movia r1, NIOS2_ICACHE_SIZE
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movui r2, NIOS2_ICACHE_LINE_SIZE
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icache_init:
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initi r1
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sub r1, r1, r2
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bgt r1, r0, icache_init
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br 1f
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/*
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* This is the default location for the exception handler. Code in jump
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* to our handler
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*/
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ENTRY(exception_handler_hook)
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movia r24, inthandler
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jmp r24
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ENTRY(fast_handler)
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nextpc et
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helper:
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stw r3, r3save - helper(et)
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rdctl r3 , pteaddr
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srli r3, r3, 12
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slli r3, r3, 2
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movia et, pgd_current
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ldw et, 0(et)
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add r3, et, r3
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ldw et, 0(r3)
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rdctl r3, pteaddr
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andi r3, r3, 0xfff
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add et, r3, et
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ldw et, 0(et)
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wrctl tlbacc, et
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nextpc et
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helper2:
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ldw r3, r3save - helper2(et)
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subi ea, ea, 4
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eret
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r3save:
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.word 0x0
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ENTRY(fast_handler_end)
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1:
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/*
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* After the instruction cache is initialized, the data cache must
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* also be initialized.
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*/
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movia r1, NIOS2_DCACHE_SIZE
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movui r2, NIOS2_DCACHE_LINE_SIZE
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dcache_init:
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initd 0(r1)
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sub r1, r1, r2
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bgt r1, r0, dcache_init
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nextpc r1 /* Find out where we are */
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chkadr:
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movia r2, chkadr
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beq r1, r2,finish_move /* We are running in RAM done */
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addi r1, r1,(_start - chkadr) /* Source */
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movia r2, _start /* Destination */
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movia r3, __bss_start /* End of copy */
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loop_move: /* r1: src, r2: dest, r3: last dest */
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ldw r8, 0(r1) /* load a word from [r1] */
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stw r8, 0(r2) /* store a word to dest [r2] */
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flushd 0(r2) /* Flush cache for safety */
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addi r1, r1, 4 /* inc the src addr */
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addi r2, r2, 4 /* inc the dest addr */
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blt r2, r3, loop_move
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movia r1, finish_move /* VMA(_start)->l1 */
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jmp r1 /* jmp to _start */
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finish_move:
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/* Mask off all possible interrupts */
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wrctl ienable, r0
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/* Clear .bss */
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movia r2, __bss_start
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movia r1, __bss_stop
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1:
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stb r0, 0(r2)
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addi r2, r2, 1
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bne r1, r2, 1b
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movia r1, init_thread_union /* set stack at top of the task union */
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addi sp, r1, THREAD_SIZE
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movia r2, _current_thread /* Remember current thread */
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stw r1, 0(r2)
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movia r1, nios2_boot_init /* save args r4-r7 passed from u-boot */
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callr r1
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movia r1, start_kernel /* call start_kernel as a subroutine */
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callr r1
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/* If we return from start_kernel, break to the oci debugger and
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* buggered we are.
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*/
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break
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/* End of startup code */
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.set at
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@ -0,0 +1,218 @@
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/*
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* Nios2-specific parts of system setup
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*
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* Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
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* Copyright (C) 2004 Microtronix Datacom Ltd.
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* Copyright (C) 2001 Vic Phillips <vic@microtronix.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/console.h>
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#include <linux/bootmem.h>
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#include <linux/initrd.h>
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#include <linux/of_fdt.h>
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#include <asm/mmu_context.h>
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#include <asm/sections.h>
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#include <asm/setup.h>
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#include <asm/cpuinfo.h>
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unsigned long memory_start;
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EXPORT_SYMBOL(memory_start);
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unsigned long memory_end;
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EXPORT_SYMBOL(memory_end);
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unsigned long memory_size;
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static struct pt_regs fake_regs = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0,
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0};
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/* Copy a short hook instruction sequence to the exception address */
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static inline void copy_exception_handler(unsigned int addr)
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{
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unsigned int start = (unsigned int) exception_handler_hook;
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volatile unsigned int tmp = 0;
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if (start == addr) {
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/* The CPU exception address already points to the handler. */
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return;
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}
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__asm__ __volatile__ (
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"ldw %2,0(%0)\n"
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"stw %2,0(%1)\n"
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"ldw %2,4(%0)\n"
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"stw %2,4(%1)\n"
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"ldw %2,8(%0)\n"
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"stw %2,8(%1)\n"
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"flushd 0(%1)\n"
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"flushd 4(%1)\n"
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"flushd 8(%1)\n"
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"flushi %1\n"
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"addi %1,%1,4\n"
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"flushi %1\n"
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"addi %1,%1,4\n"
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"flushi %1\n"
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"flushp\n"
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: /* no output registers */
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: "r" (start), "r" (addr), "r" (tmp)
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: "memory"
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);
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}
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/* Copy the fast TLB miss handler */
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static inline void copy_fast_tlb_miss_handler(unsigned int addr)
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{
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unsigned int start = (unsigned int) fast_handler;
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unsigned int end = (unsigned int) fast_handler_end;
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volatile unsigned int tmp = 0;
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__asm__ __volatile__ (
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"1:\n"
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" ldw %3,0(%0)\n"
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" stw %3,0(%1)\n"
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" flushd 0(%1)\n"
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" flushi %1\n"
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" flushp\n"
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" addi %0,%0,4\n"
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" addi %1,%1,4\n"
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" bne %0,%2,1b\n"
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: /* no output registers */
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: "r" (start), "r" (addr), "r" (end), "r" (tmp)
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: "memory"
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);
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}
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/*
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* save args passed from u-boot, called from head.S
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*
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* @r4: NIOS magic
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* @r5: initrd start
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* @r6: initrd end or fdt
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* @r7: kernel command line
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*/
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asmlinkage void __init nios2_boot_init(unsigned r4, unsigned r5, unsigned r6,
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unsigned r7)
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{
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unsigned dtb_passed = 0;
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char cmdline_passed[COMMAND_LINE_SIZE] = { 0, };
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#if defined(CONFIG_NIOS2_PASS_CMDLINE)
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if (r4 == 0x534f494e) { /* r4 is magic NIOS */
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#if defined(CONFIG_BLK_DEV_INITRD)
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if (r5) { /* initramfs */
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initrd_start = r5;
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initrd_end = r6;
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}
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#endif /* CONFIG_BLK_DEV_INITRD */
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dtb_passed = r6;
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if (r7)
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strncpy(cmdline_passed, (char *)r7, COMMAND_LINE_SIZE);
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}
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#endif
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early_init_devtree((void *)dtb_passed);
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#ifndef CONFIG_CMDLINE_FORCE
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if (cmdline_passed[0])
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strncpy(boot_command_line, cmdline_passed, COMMAND_LINE_SIZE);
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#ifdef CONFIG_NIOS2_CMDLINE_IGNORE_DTB
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else
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strncpy(boot_command_line, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
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#endif
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#endif
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}
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||||
void __init setup_arch(char **cmdline_p)
|
||||
{
|
||||
int bootmap_size;
|
||||
|
||||
console_verbose();
|
||||
|
||||
memory_start = PAGE_ALIGN((unsigned long)__pa(_end));
|
||||
memory_end = (unsigned long) CONFIG_NIOS2_MEM_BASE + memory_size;
|
||||
|
||||
init_mm.start_code = (unsigned long) _stext;
|
||||
init_mm.end_code = (unsigned long) _etext;
|
||||
init_mm.end_data = (unsigned long) _edata;
|
||||
init_mm.brk = (unsigned long) _end;
|
||||
init_task.thread.kregs = &fake_regs;
|
||||
|
||||
/* Keep a copy of command line */
|
||||
*cmdline_p = boot_command_line;
|
||||
|
||||
min_low_pfn = PFN_UP(memory_start);
|
||||
max_low_pfn = PFN_DOWN(memory_end);
|
||||
max_mapnr = max_low_pfn;
|
||||
|
||||
/*
|
||||
* give all the memory to the bootmap allocator, tell it to put the
|
||||
* boot mem_map at the start of memory
|
||||
*/
|
||||
pr_debug("init_bootmem_node(?,%#lx, %#x, %#lx)\n",
|
||||
min_low_pfn, PFN_DOWN(PHYS_OFFSET), max_low_pfn);
|
||||
bootmap_size = init_bootmem_node(NODE_DATA(0),
|
||||
min_low_pfn, PFN_DOWN(PHYS_OFFSET),
|
||||
max_low_pfn);
|
||||
|
||||
/*
|
||||
* free the usable memory, we have to make sure we do not free
|
||||
* the bootmem bitmap so we then reserve it after freeing it :-)
|
||||
*/
|
||||
pr_debug("free_bootmem(%#lx, %#lx)\n",
|
||||
memory_start, memory_end - memory_start);
|
||||
free_bootmem(memory_start, memory_end - memory_start);
|
||||
|
||||
/*
|
||||
* Reserve the bootmem bitmap itself as well. We do this in two
|
||||
* steps (first step was init_bootmem()) because this catches
|
||||
* the (very unlikely) case of us accidentally initializing the
|
||||
* bootmem allocator with an invalid RAM area.
|
||||
*
|
||||
* Arguments are start, size
|
||||
*/
|
||||
pr_debug("reserve_bootmem(%#lx, %#x)\n", memory_start, bootmap_size);
|
||||
reserve_bootmem(memory_start, bootmap_size, BOOTMEM_DEFAULT);
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
if (initrd_start) {
|
||||
reserve_bootmem(virt_to_phys((void *)initrd_start),
|
||||
initrd_end - initrd_start, BOOTMEM_DEFAULT);
|
||||
}
|
||||
#endif /* CONFIG_BLK_DEV_INITRD */
|
||||
|
||||
unflatten_and_copy_device_tree();
|
||||
|
||||
setup_cpuinfo();
|
||||
|
||||
copy_exception_handler(cpuinfo.exception_addr);
|
||||
|
||||
mmu_init();
|
||||
|
||||
copy_fast_tlb_miss_handler(cpuinfo.fast_tlb_miss_exc_addr);
|
||||
|
||||
/*
|
||||
* Initialize MMU context handling here because data from cpuinfo is
|
||||
* needed for this.
|
||||
*/
|
||||
mmu_context_init();
|
||||
|
||||
/*
|
||||
* get kmalloc into gear
|
||||
*/
|
||||
paging_init();
|
||||
|
||||
#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
|
||||
conswitchp = &dummy_con;
|
||||
#endif
|
||||
}
|
||||
Loading…
Reference in New Issue