[PATCH] powerpc: Merge cacheflush.h and cache.h
The ppc32 and ppc64 versions of cacheflush.h were almost identical. The two versions of cache.h are fairly similar, except for a bunch of register definitions in the ppc32 version which probably belong better elsewhere. This patch, therefore, merges both headers. Notable points: - there are several functions in cacheflush.h which exist only on ppc32 or only on ppc64. These are handled by #ifdef for now, but these should probably be consolidated, along with the actual code behind them later. - Confusingly, both ppc32 and ppc64 have a flush_dcache_range(), but they're subtly different: it uses dcbf on ppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which uses dcbf. These too should be merged and consolidated later. - Also flush_dcache_range() was defined in cacheflush.h on ppc64, and in cache.h on ppc32. In the merged version it's in cacheflush.h - On ppc32 flush_icache_range() is a normal function from misc.S. On ppc64, it was wrapper, testing a feature bit before calling __flush_icache_range() which does the actual flush. This patch takes the ppc64 approach, which amounts to no change on ppc32, since CPU_FTR_COHERENT_ICACHE will never be set there, but does mean renaming flush_icache_range() to __flush_icache_range() in arch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S - The PReP register info from asm-ppc/cache.h has moved to arch/ppc/platforms/prep_setup.c - The 8xx register info from asm-ppc/cache.h has moved to a new asm-powerpc/reg_8xx.h, included from reg.h - flush_dcache_all() was defined on ppc32 (only), but was never called (although it was exported). Thus this patch removes it from cacheflush.h and from ARCH=powerpc (misc_32.S) entirely. It's left in ARCH=ppc for now, with the prototype moved to ppc_ksyms.c. Built for Walnut (ARCH=ppc), 32-bit multiplatform (pmac, CHRP and PReP ARCH=ppc, pmac and CHRP ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built for 32-bit powermac (ARCH=ppc and ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built and booted on G5 (ARCH=powerpc) Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
David Gibson
Paul Mackerras
parent
e130bedb7c
commit
26ef5c0957
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@ -519,7 +519,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_icache_range)
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_GLOBAL(__flush_icache_range)
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BEGIN_FTR_SECTION
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blr /* for 601, do nothing */
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END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
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@ -607,27 +607,6 @@ _GLOBAL(invalidate_dcache_range)
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sync /* wait for dcbi's to get to ram */
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blr
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#ifdef CONFIG_NOT_COHERENT_CACHE
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/*
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* 40x cores have 8K or 16K dcache and 32 byte line size.
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* 44x has a 32K dcache and 32 byte line size.
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* 8xx has 1, 2, 4, 8K variants.
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* For now, cover the worst case of the 44x.
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* Must be called with external interrupts disabled.
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*/
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#define CACHE_NWAYS 64
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#define CACHE_NLINES 16
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_GLOBAL(flush_dcache_all)
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li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
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mtctr r4
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lis r5, KERNELBASE@h
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1: lwz r3, 0(r5) /* Load one word from every line */
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addi r5, r5, L1_CACHE_BYTES
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bdnz 1b
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blr
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#endif /* CONFIG_NOT_COHERENT_CACHE */
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/*
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* Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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@ -497,9 +497,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
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* and invalidate the corresponding instruction cache blocks.
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* This is a no-op on the 601.
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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* __flush_icache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_icache_range)
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_GLOBAL(__flush_icache_range)
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BEGIN_FTR_SECTION
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blr /* for 601, do nothing */
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END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
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@ -175,6 +175,7 @@ EXPORT_SYMBOL(pci_bus_to_phys);
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_NOT_COHERENT_CACHE
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extern void flush_dcache_all(void);
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EXPORT_SYMBOL(flush_dcache_all);
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#endif
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@ -61,6 +61,15 @@
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#include <asm/pci-bridge.h>
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#include <asm/todc.h>
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/* prep registers for L2 */
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#define CACHECRBA 0x80000823 /* Cache configuration register address */
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#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
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#define L2CACHE_512KB 0x00 /* 512KB */
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#define L2CACHE_256KB 0x01 /* 256KB */
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#define L2CACHE_1MB 0x02 /* 1MB */
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#define L2CACHE_NONE 0x03 /* NONE */
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#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
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TODC_ALLOC();
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unsigned char ucSystemType;
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@ -0,0 +1,40 @@
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#ifndef _ASM_POWERPC_CACHE_H
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#define _ASM_POWERPC_CACHE_H
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#ifdef __KERNEL__
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#include <linux/config.h>
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/* bytes per L1 cache line */
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#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
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#define L1_CACHE_SHIFT 4
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#define MAX_COPY_PREFETCH 1
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#elif defined(CONFIG_PPC32)
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#define L1_CACHE_SHIFT 5
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#define MAX_COPY_PREFETCH 4
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#else /* CONFIG_PPC64 */
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#define L1_CACHE_SHIFT 7
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#endif
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
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#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
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struct ppc64_caches {
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u32 dsize; /* L1 d-cache size */
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u32 dline_size; /* L1 d-cache line size */
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u32 log_dline_size;
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u32 dlines_per_page;
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u32 isize; /* L1 i-cache size */
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u32 iline_size; /* L1 i-cache line size */
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u32 log_iline_size;
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u32 ilines_per_page;
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};
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extern struct ppc64_caches ppc64_caches;
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#endif /* __powerpc64__ && ! __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_CACHE_H */
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@ -1,13 +1,20 @@
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#ifndef _PPC64_CACHEFLUSH_H
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#define _PPC64_CACHEFLUSH_H
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_CACHEFLUSH_H
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#define _ASM_POWERPC_CACHEFLUSH_H
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#ifdef __KERNEL__
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#include <linux/mm.h>
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#include <asm/cputable.h>
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/*
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* No cache flushing is required when address mappings are
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* changed, because the caches on PowerPCs are physically
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* addressed.
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* No cache flushing is required when address mappings are changed,
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* because the caches on PowerPCs are physically addressed.
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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@ -22,27 +29,40 @@ extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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extern void __flush_icache_range(unsigned long, unsigned long);
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extern void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr,
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int len);
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extern void flush_dcache_range(unsigned long start, unsigned long stop);
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extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
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extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { memcpy(dst, src, len); \
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flush_icache_user_range(vma, page, vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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extern void __flush_dcache_icache(void *page_va);
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
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__flush_icache_range(start, stop);
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}
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#endif /* _PPC64_CACHEFLUSH_H */
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extern void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr,
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int len);
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extern void __flush_dcache_icache(void *page_va);
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extern void flush_dcache_icache_page(struct page *page);
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#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
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extern void __flush_dcache_icache_phys(unsigned long physaddr);
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#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
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extern void flush_dcache_range(unsigned long start, unsigned long stop);
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#ifdef CONFIG_PPC32
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extern void clean_dcache_range(unsigned long start, unsigned long stop);
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extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
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#endif /* CONFIG_PPC32 */
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#ifdef CONFIG_PPC64
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extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
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extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
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#endif
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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flush_icache_user_range(vma, page, vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_CACHEFLUSH_H */
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@ -16,7 +16,11 @@
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/* Pickup Book E specific registers. */
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#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
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#include <asm/reg_booke.h>
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#endif
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#endif /* CONFIG_BOOKE || CONFIG_40x */
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#ifdef CONFIG_8xx
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#include <asm/reg_8xx.h>
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#endif /* CONFIG_8xx */
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#define MSR_SF_LG 63 /* Enable 64 bit mode */
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#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
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@ -1,49 +1,9 @@
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/*
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* include/asm-ppc/cache.h
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* Contains register definitions common to PowerPC 8xx CPUs. Notice
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*/
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#ifdef __KERNEL__
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#ifndef __ARCH_PPC_CACHE_H
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#define __ARCH_PPC_CACHE_H
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#ifndef _ASM_POWERPC_REG_8xx_H
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#define _ASM_POWERPC_REG_8xx_H
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#include <linux/config.h>
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/* bytes per L1 cache line */
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#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
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#define L1_CACHE_SHIFT 4
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#define MAX_COPY_PREFETCH 1
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#elif defined(CONFIG_PPC64BRIDGE)
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#define L1_CACHE_SHIFT 7
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#define MAX_COPY_PREFETCH 1
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#else
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#define L1_CACHE_SHIFT 5
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#define MAX_COPY_PREFETCH 4
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#endif
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
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#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
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#define L1_CACHE_PAGES 8
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#ifndef __ASSEMBLY__
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extern void clean_dcache_range(unsigned long start, unsigned long stop);
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extern void flush_dcache_range(unsigned long start, unsigned long stop);
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extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
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extern void flush_dcache_all(void);
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#endif /* __ASSEMBLY__ */
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/* prep registers for L2 */
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#define CACHECRBA 0x80000823 /* Cache configuration register address */
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#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
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#define L2CACHE_512KB 0x00 /* 512KB */
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#define L2CACHE_256KB 0x01 /* 256KB */
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#define L2CACHE_1MB 0x02 /* 1MB */
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#define L2CACHE_NONE 0x03 /* NONE */
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#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
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#ifdef CONFIG_8xx
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/* Cache control on the MPC8xx is provided through some additional
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* special purpose registers.
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*/
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#define DC_DFWT 0x40000000 /* Data cache is forced write through */
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#define DC_LES 0x20000000 /* Caches are little endian mode */
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#endif /* CONFIG_8xx */
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_REG_8xx_H */
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@ -1,49 +0,0 @@
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/*
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* include/asm-ppc/cacheflush.h
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifdef __KERNEL__
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#ifndef _PPC_CACHEFLUSH_H
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#define _PPC_CACHEFLUSH_H
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#include <linux/mm.h>
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/*
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* No cache flushing is required when address mappings are
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* changed, because the caches on PowerPCs are physically
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* addressed. -- paulus
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* Also, when SMP we use the coherency (M) bit of the
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* BATs and PTEs. -- Cort
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_range(vma, a, b) do { } while (0)
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#define flush_cache_page(vma, p, pfn) do { } while (0)
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#define flush_icache_page(vma, page) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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extern void flush_icache_range(unsigned long, unsigned long);
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extern void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr, int len);
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { memcpy(dst, src, len); \
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flush_icache_user_range(vma, page, vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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extern void __flush_dcache_icache(void *page_va);
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extern void __flush_dcache_icache_phys(unsigned long physaddr);
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extern void flush_dcache_icache_page(struct page *page);
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#endif /* _PPC_CACHEFLUSH_H */
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#endif /* __KERNEL__ */
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@ -1,36 +0,0 @@
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __ARCH_PPC64_CACHE_H
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#define __ARCH_PPC64_CACHE_H
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#include <asm/types.h>
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/* bytes per L1 cache line */
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#define L1_CACHE_SHIFT 7
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
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#ifndef __ASSEMBLY__
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struct ppc64_caches {
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u32 dsize; /* L1 d-cache size */
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u32 dline_size; /* L1 d-cache line size */
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u32 log_dline_size;
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u32 dlines_per_page;
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u32 isize; /* L1 i-cache size */
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u32 iline_size; /* L1 i-cache line size */
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u32 log_iline_size;
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u32 ilines_per_page;
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};
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extern struct ppc64_caches ppc64_caches;
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#endif
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#endif
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