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Samsung DT updates for v3.14 

- Add support Octa Cores for exynos5420
   : populate CPU node entries to 8 Cores
   : extend mct to support 8 local interrupts
 - Update dwmmc nodes for exynos5250 and exynos5420
   : change status property of dwmmc nodes for exynos5250
   : move dwmmc nodes from exynos5 to exynos5250 because
     it's different between exynos5250 and exynos5420
   : rename mmc nodes from dwmmc for exynos5 SoCs
   : add dwmmc nodes for exynos5420
 - Add G-Scaler nodes for exynos5420
 - Add HS-i2c nodes in exynos5420
   : High Speed I2C 7 channels (4 to 10)
 - Update sysreg binding and node name in exynos4
 - Update min voltage on exynos5250-arndale
 - Move fifo-depth property from boards to exynos5250 SoC
   : because the fifo-depth property is SoC specific
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Merge tag 'samsung-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt

From Kukjin Kim:
Samsung DT updates for v3.14
- Add support Octa Cores for exynos5420
  : populate CPU node entries to 8 Cores
  : extend mct to support 8 local interrupts
- Update dwmmc nodes for exynos5250 and exynos5420
  : change status property of dwmmc nodes for exynos5250
  : move dwmmc nodes from exynos5 to exynos5250 because
    it's different between exynos5250 and exynos5420
  : rename mmc nodes from dwmmc for exynos5 SoCs
  : add dwmmc nodes for exynos5420
- Add G-Scaler nodes for exynos5420
- Add HS-i2c nodes in exynos5420
  : High Speed I2C 7 channels (4 to 10)
- Update sysreg binding and node name in exynos4
- Update min voltage on exynos5250-arndale
- Move fifo-depth property from boards to exynos5250 SoC
  : because the fifo-depth property is SoC specific

* tag 'samsung-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: dts: Update Samsung sysreg binding document
  ARM: dts: Fix sysreg node name in exynos4.dtsi
  ARM: dts: Add hs-i2c nodes to exynos5420
  ARM: dts: Update min voltage for vdd_arm on Arndale
  ARM: dts: populate cpu node entries to 8 cpus for exynos5420
  clocksource: mct: extend mct to support 8 local interrupts for Exynos5420
  ARM: dts: Add device nodes for GScaler blocks for exynos5420
  ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
  ARM: dts: rename mmc dts node for exynos5 series
  ARM: dts: Move fifo-depth property from exynos5250 board dts
  ARM: dts: change status property of dwmmc nodes for exynos5250
  ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2013-12-22 14:12:57 -08:00
parent 448e7edefa e0b51c2eae
commit 2652fbde3f
12 changed files with 280 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/devicetree/bindings/arm/samsung/sysreg.txt
View File

@ -1,7 +1,12 @@
SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
Properties:
- name : should be 'sysreg';
- compatible : should contain "samsung,<chip name>-sysreg", "syscon";
For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
- reg : offset and length of the register set.
Example:
syscon@10010000 {
compatible = "samsung,exynos4-sysreg", "syscon";
reg = <0x10010000 0x400>;
};

2
Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
View File

@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
specific extensions.
- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
unit (ciu) clock. This property is applicable only for Exynos5 SoC's and

11
arch/arm/boot/dts/cros5250-common.dtsi
View File

@ -241,11 +241,10 @@
};
};
dwmmc0@12200000 {
mmc@12200000 {
num-slots = <1>;
supports-highspeed;
broken-cd;
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@ -259,14 +258,13 @@
};
};
dwmmc1@12210000 {
mmc@12210000 {
status = "disabled";
};
dwmmc2@12220000 {
mmc@12220000 {
num-slots = <1>;
supports-highspeed;
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@ -281,11 +279,10 @@
};
};
dwmmc3@12230000 {
mmc@12230000 {
num-slots = <1>;
supports-highspeed;
broken-cd;
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;

2
arch/arm/boot/dts/exynos4.dtsi
View File

@ -99,7 +99,7 @@
reg = <0x10440000 0x1000>;
};
sys_reg: sysreg {
sys_reg: syscon@10010000 {
compatible = "samsung,exynos4-sysreg", "syscon";
reg = <0x10010000 0x400>;
};

21
arch/arm/boot/dts/exynos5.dtsi
View File

@ -50,27 +50,6 @@
interrupts = <1 9 0xf04>;
};
dwmmc_0: dwmmc0@12200000 {
compatible = "samsung,exynos5250-dw-mshc";
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
};
dwmmc_1: dwmmc1@12210000 {
compatible = "samsung,exynos5250-dw-mshc";
interrupts = <0 76 0>;
#address-cells = <1>;
#size-cells = <0>;
};
dwmmc_2: dwmmc2@12220000 {
compatible = "samsung,exynos5250-dw-mshc";
interrupts = <0 77 0>;
#address-cells = <1>;
#size-cells = <0>;
};
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;

18
arch/arm/boot/dts/exynos5250-arndale.dts
View File

@ -266,7 +266,7 @@
buck2_reg: BUCK2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <925000>;
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
@ -384,11 +384,11 @@
status = "disabled";
};
dwmmc_0: dwmmc0@12200000 {
mmc_0: mmc@12200000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@ -403,14 +403,10 @@
};
};
dwmmc_1: dwmmc1@12210000 {
status = "disabled";
};
dwmmc_2: dwmmc2@12220000 {
mmc_2: mmc@12220000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@ -426,10 +422,6 @@
};
};
dwmmc_3: dwmmc3@12230000 {
status = "disabled";
};
i2s0: i2s@03830000 {
status = "okay";
};

16
arch/arm/boot/dts/exynos5250-smdk5250.dts
View File

@ -140,11 +140,11 @@
};
};
dwmmc0@12200000 {
mmc@12200000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@ -158,14 +158,10 @@
};
};
dwmmc1@12210000 {
status = "disabled";
};
dwmmc2@12220000 {
mmc@12220000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@ -180,10 +176,6 @@
};
};
dwmmc3@12230000 {
status = "disabled";
};
spi_0: spi@12d20000 {
status = "disabled";
};

2
arch/arm/boot/dts/exynos5250-snow.dts
View File

@ -175,7 +175,7 @@
* On Snow we've got SIP WiFi and so can keep drive strengths low to
* reduce EMI.
*/
dwmmc3@12230000 {
mmc@12230000 {
slot@0 {
pinctrl-names = "default";
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;

36
arch/arm/boot/dts/exynos5250.dtsi
View File

@ -33,10 +33,10 @@
gsc1 = &gsc_1;
gsc2 = &gsc_2;
gsc3 = &gsc_3;
mshc0 = &dwmmc_0;
mshc1 = &dwmmc_1;
mshc2 = &dwmmc_2;
mshc3 = &dwmmc_3;
mshc0 = &mmc_0;
mshc1 = &mmc_1;
mshc2 = &mmc_2;
mshc3 = &mmc_3;
i2c0 = &i2c_0;
i2c1 = &i2c_1;
i2c2 = &i2c_2;
@ -392,25 +392,43 @@
pinctrl-0 = <&spi2_bus>;
};
dwmmc_0: dwmmc0@12200000 {
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5250-dw-mshc";
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x1000>;
clocks = <&clock 280>, <&clock 139>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
status = "disabled";
};
dwmmc_1: dwmmc1@12210000 {
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5250-dw-mshc";
interrupts = <0 76 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x1000>;
clocks = <&clock 281>, <&clock 140>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
status = "disabled";
};
dwmmc_2: dwmmc2@12220000 {
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5250-dw-mshc";
interrupts = <0 77 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
clocks = <&clock 282>, <&clock 141>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
status = "disabled";
};
dwmmc_3: dwmmc3@12230000 {
mmc_3: mmc@12230000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12230000 0x1000>;
interrupts = <0 78 0>;
@ -418,6 +436,8 @@
#size-cells = <0>;
clocks = <&clock 283>, <&clock 142>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
status = "disabled";
};
i2s0: i2s@03830000 {

33
arch/arm/boot/dts/exynos5420-smdk5420.dts
View File

@ -31,6 +31,39 @@
};
};
mmc@12200000 {
status = "okay";
broken-cd;
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
};
mmc@12220000 {
status = "okay";
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
dp-controller@145B0000 {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;

194
arch/arm/boot/dts/exynos5420.dtsi
View File

@ -22,6 +22,9 @@
compatible = "samsung,exynos5420";
aliases {
mshc0 = &mmc_0;
mshc1 = &mmc_1;
mshc2 = &mmc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@ -31,6 +34,15 @@
i2c1 = &i2c_1;
i2c2 = &i2c_2;
i2c3 = &i2c_3;
i2c4 = &hsi2c_4;
i2c5 = &hsi2c_5;
i2c6 = &hsi2c_6;
i2c7 = &hsi2c_7;
i2c8 = &hsi2c_8;
i2c9 = &hsi2c_9;
i2c10 = &hsi2c_10;
gsc0 = &gsc_0;
gsc1 = &gsc_1;
};
cpus {
@ -64,6 +76,34 @@
reg = <0x3>;
clock-frequency = <1800000000>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
clock-frequency = <1000000000>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
clock-frequency = <1000000000>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
clock-frequency = <1000000000>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
clock-frequency = <1000000000>;
};
};
clock: clock-controller@10010000 {
@ -88,13 +128,50 @@
clock-names = "mfc";
};
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x2000>;
clocks = <&clock 351>, <&clock 132>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
interrupts = <0 76 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x2000>;
clocks = <&clock 352>, <&clock 133>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5420-dw-mshc";
interrupts = <0 77 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
clocks = <&clock 353>, <&clock 134>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
mct@101C0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
interrupt-controller;
#interrups-cells = <1>;
interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>;
clocks = <&clock 1>, <&clock 315>;
clock-names = "fin_pll", "mct";
@ -109,7 +186,11 @@
<4 &gic 0 120 0>,
<5 &gic 0 121 0>,
<6 &gic 0 122 0>,
<7 &gic 0 123 0>;
<7 &gic 0 123 0>,
<8 &gic 0 128 0>,
<9 &gic 0 129 0>,
<10 &gic 0 130 0>,
<11 &gic 0 131 0>;
};
};
@ -292,6 +373,97 @@
status = "disabled";
};
hsi2c_4: i2c@12CA0000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CA0000 0x1000>;
interrupts = <0 60 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_hs_bus>;
clocks = <&clock 265>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_5: i2c@12CB0000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CB0000 0x1000>;
interrupts = <0 61 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_hs_bus>;
clocks = <&clock 266>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_6: i2c@12CC0000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CC0000 0x1000>;
interrupts = <0 62 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_hs_bus>;
clocks = <&clock 267>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_7: i2c@12CD0000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CD0000 0x1000>;
interrupts = <0 63 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_hs_bus>;
clocks = <&clock 268>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_8: i2c@12E00000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12E00000 0x1000>;
interrupts = <0 87 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8_hs_bus>;
clocks = <&clock 281>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_9: i2c@12E10000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12E10000 0x1000>;
interrupts = <0 88 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c9_hs_bus>;
clocks = <&clock 282>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_10: i2c@12E20000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12E20000 0x1000>;
interrupts = <0 203 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c10_hs_bus>;
clocks = <&clock 283>;
clock-names = "hsi2c";
status = "disabled";
};
hdmi@14530000 {
compatible = "samsung,exynos4212-hdmi";
reg = <0x14530000 0x70000>;
@ -310,4 +482,22 @@
clocks = <&clock 431>, <&clock 143>;
clock-names = "mixer", "sclk_hdmi";
};
gsc_0: video-scaler@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
interrupts = <0 85 0>;
clocks = <&clock 465>;
clock-names = "gscl";
samsung,power-domain = <&gsc_pd>;
};
gsc_1: video-scaler@13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
interrupts = <0 86 0>;
clocks = <&clock 466>;
clock-names = "gscl";
samsung,power-domain = <&gsc_pd>;
};
};

4
drivers/clocksource/exynos_mct.c
View File

@ -71,6 +71,10 @@ enum {
MCT_L1_IRQ,
MCT_L2_IRQ,
MCT_L3_IRQ,
MCT_L4_IRQ,
MCT_L5_IRQ,
MCT_L6_IRQ,
MCT_L7_IRQ,
MCT_NR_IRQS,
};