usb: gadget: ci13xxx: redo register access
Use lookup table instead of conditional macrodefinitions of register addresses. With two different possible register layouts and different register offsets, it's easiest to build a table with register addresses at probe time, based on the information supplied from the platform and device capabilities. This way we get rid of branch-per-register-access. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alexander Shishkin
Greg Kroah-Hartman
parent
d3595d132b
commit
262c16320a
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@ -136,26 +136,73 @@ static int ffs_nr(u32 x)
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#define ABS_AHBBURST (0x0090UL)
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#define ABS_AHBMODE (0x0098UL)
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/* UDC register map */
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#define CAP_CAPLENGTH (0x000UL)
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#define CAP_HCCPARAMS (0x008UL)
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#define CAP_DCCPARAMS (0x024UL)
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#define ABS_TESTMODE (udc->hw_bank.lpm ? 0x0FCUL : 0x138UL)
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/* offset to CAPLENTGH (addr + data) */
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#define OP_USBCMD (0x000UL)
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#define OP_USBSTS (0x004UL)
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#define OP_USBINTR (0x008UL)
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#define OP_DEVICEADDR (0x014UL)
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#define OP_ENDPTLISTADDR (0x018UL)
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#define OP_PORTSC (0x044UL)
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#define OP_DEVLC (0x084UL)
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#define OP_USBMODE (udc->hw_bank.lpm ? 0x0C8UL : 0x068UL)
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#define OP_ENDPTSETUPSTAT (udc->hw_bank.lpm ? 0x0D8UL : 0x06CUL)
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#define OP_ENDPTPRIME (udc->hw_bank.lpm ? 0x0DCUL : 0x070UL)
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#define OP_ENDPTFLUSH (udc->hw_bank.lpm ? 0x0E0UL : 0x074UL)
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#define OP_ENDPTSTAT (udc->hw_bank.lpm ? 0x0E4UL : 0x078UL)
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#define OP_ENDPTCOMPLETE (udc->hw_bank.lpm ? 0x0E8UL : 0x07CUL)
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#define OP_ENDPTCTRL (udc->hw_bank.lpm ? 0x0ECUL : 0x080UL)
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#define OP_LAST (udc->hw_bank.lpm ? 0x12CUL : 0x0C0UL)
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static uintptr_t ci_regs_nolpm[] = {
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[CAP_CAPLENGTH] = 0x000UL,
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[CAP_HCCPARAMS] = 0x008UL,
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[CAP_DCCPARAMS] = 0x024UL,
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[CAP_TESTMODE] = 0x038UL,
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[OP_USBCMD] = 0x000UL,
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[OP_USBSTS] = 0x004UL,
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[OP_USBINTR] = 0x008UL,
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[OP_DEVICEADDR] = 0x014UL,
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[OP_ENDPTLISTADDR] = 0x018UL,
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[OP_PORTSC] = 0x044UL,
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[OP_DEVLC] = 0x084UL,
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[OP_USBMODE] = 0x068UL,
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[OP_ENDPTSETUPSTAT] = 0x06CUL,
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[OP_ENDPTPRIME] = 0x070UL,
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[OP_ENDPTFLUSH] = 0x074UL,
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[OP_ENDPTSTAT] = 0x078UL,
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[OP_ENDPTCOMPLETE] = 0x07CUL,
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[OP_ENDPTCTRL] = 0x080UL,
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};
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static uintptr_t ci_regs_lpm[] = {
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[CAP_CAPLENGTH] = 0x000UL,
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[CAP_HCCPARAMS] = 0x008UL,
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[CAP_DCCPARAMS] = 0x024UL,
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[CAP_TESTMODE] = 0x0FCUL,
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[OP_USBCMD] = 0x000UL,
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[OP_USBSTS] = 0x004UL,
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[OP_USBINTR] = 0x008UL,
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[OP_DEVICEADDR] = 0x014UL,
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[OP_ENDPTLISTADDR] = 0x018UL,
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[OP_PORTSC] = 0x044UL,
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[OP_DEVLC] = 0x084UL,
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[OP_USBMODE] = 0x0C8UL,
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[OP_ENDPTSETUPSTAT] = 0x0D8UL,
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[OP_ENDPTPRIME] = 0x0DCUL,
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[OP_ENDPTFLUSH] = 0x0E0UL,
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[OP_ENDPTSTAT] = 0x0E4UL,
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[OP_ENDPTCOMPLETE] = 0x0E8UL,
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[OP_ENDPTCTRL] = 0x0ECUL,
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};
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static int hw_alloc_regmap(struct ci13xxx *udc, bool is_lpm)
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{
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int i;
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kfree(udc->hw_bank.regmap);
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udc->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
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GFP_KERNEL);
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if (!udc->hw_bank.regmap)
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return -ENOMEM;
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for (i = 0; i < OP_ENDPTCTRL; i++)
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udc->hw_bank.regmap[i] =
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(i <= CAP_LAST ? udc->hw_bank.cap : udc->hw_bank.op) +
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(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
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for (; i <= OP_LAST; i++)
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udc->hw_bank.regmap[i] = udc->hw_bank.op +
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4 * (i - OP_ENDPTCTRL) +
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(is_lpm
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? ci_regs_lpm[OP_ENDPTCTRL]
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: ci_regs_nolpm[OP_ENDPTCTRL]);
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return 0;
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}
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/**
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* hw_ep_bit: calculates the bit number
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@ -180,62 +227,64 @@ static int ep_to_bit(struct ci13xxx *udc, int n)
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}
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/**
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* hw_read: reads from a register bitfield
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* @base: register block address
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* @addr: address relative to operational register base
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* hw_read: reads from a hw register
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* @reg: register index
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* @mask: bitfield mask
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*
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* This function returns register bitfield data
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* This function returns register contents
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*/
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static u32 hw_read(void __iomem *base, u32 addr, u32 mask)
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static u32 hw_read(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask)
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{
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return ioread32(addr + base) & mask;
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return ioread32(udc->hw_bank.regmap[reg]) & mask;
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}
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/**
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* hw_write: writes to a register bitfield
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* @base: register block address
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* @addr: address relative to operational register base
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* hw_write: writes to a hw register
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* @reg: register index
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* @mask: bitfield mask
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* @data: new data
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* @data: new value
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*/
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static void hw_write(void __iomem *base, u32 addr, u32 mask, u32 data)
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static void hw_write(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask,
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u32 data)
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{
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iowrite32(hw_read(base, addr, ~mask) | (data & mask),
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addr + base);
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if (~mask)
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data = (ioread32(udc->hw_bank.regmap[reg]) & ~mask)
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| (data & mask);
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iowrite32(data, udc->hw_bank.regmap[reg]);
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}
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/**
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* hw_test_and_clear: tests & clears operational register bitfield
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* @base: register block address
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* @addr: address relative to operational register base
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* hw_test_and_clear: tests & clears a hw register
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* @reg: register index
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* @mask: bitfield mask
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*
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* This function returns register bitfield data
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* This function returns register contents
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*/
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static u32 hw_test_and_clear(void __iomem *base, u32 addr, u32 mask)
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static u32 hw_test_and_clear(struct ci13xxx *udc, enum ci13xxx_regs reg,
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u32 mask)
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{
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u32 reg = hw_read(base, addr, mask);
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u32 val = ioread32(udc->hw_bank.regmap[reg]) & mask;
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iowrite32(reg, addr + base);
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return reg;
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iowrite32(val, udc->hw_bank.regmap[reg]);
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return val;
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}
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/**
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* hw_test_and_write: tests & writes operational register bitfield
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* @base: register block address
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* @addr: address relative to operational register base
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* hw_test_and_write: tests & writes a hw register
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* @reg: register index
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* @mask: bitfield mask
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* @data: new data
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* @data: new value
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*
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* This function returns register bitfield data
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* This function returns register contents
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*/
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static u32 hw_test_and_write(void __iomem *base, u32 addr, u32 mask, u32 data)
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static u32 hw_test_and_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
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u32 mask, u32 data)
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{
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u32 reg = hw_read(base, addr, ~0);
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u32 val = hw_read(udc, reg, ~0);
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iowrite32((reg & ~mask) | (data & mask), addr + base);
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return (reg & mask) >> ffs_nr(mask);
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hw_write(udc, reg, mask, data);
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return (val & mask) >> ffs_nr(mask);
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}
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static int hw_device_init(struct ci13xxx *udc, void __iomem *base,
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@ -250,14 +299,16 @@ static int hw_device_init(struct ci13xxx *udc, void __iomem *base,
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udc->hw_bank.cap += cap_offset;
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udc->hw_bank.op = udc->hw_bank.cap + ioread8(udc->hw_bank.cap);
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reg = hw_read(udc->hw_bank.cap, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
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hw_alloc_regmap(udc, false);
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reg = hw_read(udc, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
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ffs_nr(HCCPARAMS_LEN);
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udc->hw_bank.lpm = reg;
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hw_alloc_regmap(udc, !!reg);
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udc->hw_bank.size = udc->hw_bank.op - udc->hw_bank.abs;
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udc->hw_bank.size += OP_LAST;
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udc->hw_bank.size /= sizeof(u32);
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reg = hw_read(udc->hw_bank.cap, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
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reg = hw_read(udc, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
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ffs_nr(DCCPARAMS_DEN);
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udc->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
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@ -281,11 +332,11 @@ static int hw_device_init(struct ci13xxx *udc, void __iomem *base,
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static int hw_device_reset(struct ci13xxx *udc)
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{
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/* should flush & stop before reset */
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hw_write(udc->hw_bank.op, OP_ENDPTFLUSH, ~0, ~0);
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hw_write(udc->hw_bank.op, OP_USBCMD, USBCMD_RS, 0);
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hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
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hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
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hw_write(udc->hw_bank.op, OP_USBCMD, USBCMD_RST, USBCMD_RST);
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while (hw_read(udc->hw_bank.op, OP_USBCMD, USBCMD_RST))
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hw_write(udc, OP_USBCMD, USBCMD_RST, USBCMD_RST);
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while (hw_read(udc, OP_USBCMD, USBCMD_RST))
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udelay(10); /* not RTOS friendly */
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@ -294,17 +345,15 @@ static int hw_device_reset(struct ci13xxx *udc)
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CI13XXX_CONTROLLER_RESET_EVENT);
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if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
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hw_write(udc->hw_bank.op, OP_USBMODE, USBMODE_SDIS,
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USBMODE_SDIS);
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hw_write(udc, OP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
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/* USBMODE should be configured step by step */
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hw_write(udc->hw_bank.op, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
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hw_write(udc->hw_bank.op, OP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
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hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
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hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
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/* HW >= 2.3 */
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hw_write(udc->hw_bank.op, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
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hw_write(udc, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
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if (hw_read(udc->hw_bank.op, OP_USBMODE, USBMODE_CM) !=
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USBMODE_CM_DEVICE) {
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if (hw_read(udc, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
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pr_err("cannot enter in device mode");
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pr_err("lpm = %i", udc->hw_bank.lpm);
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return -ENODEV;
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@ -323,14 +372,14 @@ static int hw_device_reset(struct ci13xxx *udc)
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static int hw_device_state(struct ci13xxx *udc, u32 dma)
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{
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if (dma) {
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hw_write(udc->hw_bank.op, OP_ENDPTLISTADDR, ~0, dma);
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hw_write(udc, OP_ENDPTLISTADDR, ~0, dma);
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/* interrupt, error, port change, reset, sleep/suspend */
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hw_write(udc->hw_bank.op, OP_USBINTR, ~0,
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hw_write(udc, OP_USBINTR, ~0,
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USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
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hw_write(udc->hw_bank.op, OP_USBCMD, USBCMD_RS, USBCMD_RS);
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hw_write(udc, OP_USBCMD, USBCMD_RS, USBCMD_RS);
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} else {
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hw_write(udc->hw_bank.op, OP_USBCMD, USBCMD_RS, 0);
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hw_write(udc->hw_bank.op, OP_USBINTR, ~0, 0);
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hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
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hw_write(udc, OP_USBINTR, ~0, 0);
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}
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return 0;
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}
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@ -348,10 +397,10 @@ static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
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do {
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/* flush any pending transfer */
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hw_write(udc->hw_bank.op, OP_ENDPTFLUSH, BIT(n), BIT(n));
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while (hw_read(udc->hw_bank.op, OP_ENDPTFLUSH, BIT(n)))
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hw_write(udc, OP_ENDPTFLUSH, BIT(n), BIT(n));
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while (hw_read(udc, OP_ENDPTFLUSH, BIT(n)))
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cpu_relax();
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} while (hw_read(udc->hw_bank.op, OP_ENDPTSTAT, BIT(n)));
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} while (hw_read(udc, OP_ENDPTSTAT, BIT(n)));
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return 0;
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}
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@ -366,7 +415,7 @@ static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
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static int hw_ep_disable(struct ci13xxx *udc, int num, int dir)
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{
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hw_ep_flush(udc, num, dir);
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hw_write(udc->hw_bank.op, OP_ENDPTCTRL + num * sizeof(u32),
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hw_write(udc, OP_ENDPTCTRL + num,
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dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
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return 0;
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}
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@ -402,7 +451,7 @@ static int hw_ep_enable(struct ci13xxx *udc, int num, int dir, int type)
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mask |= ENDPTCTRL_RXE; /* enable */
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data |= ENDPTCTRL_RXE;
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}
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hw_write(udc->hw_bank.op, OP_ENDPTCTRL + num * sizeof(u32), mask, data);
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hw_write(udc, OP_ENDPTCTRL + num, mask, data);
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return 0;
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}
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@ -417,8 +466,7 @@ static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
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{
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u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
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return !!hw_read(udc->hw_bank.op, OP_ENDPTCTRL + num * sizeof(u32),
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mask);
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return hw_read(udc, OP_ENDPTCTRL + num, mask) ? 1 : 0;
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}
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/**
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@ -431,7 +479,7 @@ static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
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static int hw_test_and_clear_setup_status(struct ci13xxx *udc, int n)
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{
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n = ep_to_bit(udc, n);
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return hw_test_and_clear(udc->hw_bank.op, OP_ENDPTSETUPSTAT, BIT(n));
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return hw_test_and_clear(udc, OP_ENDPTSETUPSTAT, BIT(n));
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}
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/**
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@ -446,16 +494,14 @@ static int hw_ep_prime(struct ci13xxx *udc, int num, int dir, int is_ctrl)
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{
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int n = hw_ep_bit(num, dir);
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if (is_ctrl && dir == RX &&
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hw_read(udc->hw_bank.op, OP_ENDPTSETUPSTAT, BIT(num)))
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if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
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return -EAGAIN;
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hw_write(udc->hw_bank.op, OP_ENDPTPRIME, BIT(n), BIT(n));
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hw_write(udc, OP_ENDPTPRIME, BIT(n), BIT(n));
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while (hw_read(udc->hw_bank.op, OP_ENDPTPRIME, BIT(n)))
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while (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
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cpu_relax();
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if (is_ctrl && dir == RX &&
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hw_read(udc->hw_bank.op, OP_ENDPTSETUPSTAT, BIT(num)))
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if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
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return -EAGAIN;
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/* status shoult be tested according with manual but it doesn't work */
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@ -477,14 +523,13 @@ static int hw_ep_set_halt(struct ci13xxx *udc, int num, int dir, int value)
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return -EINVAL;
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do {
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u32 addr = OP_ENDPTCTRL + num * sizeof(u32);
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enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
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u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
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u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
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/* data toggle - reserved for EP0 but it's in ESS */
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hw_write(udc->hw_bank.op, addr, mask_xs|mask_xr,
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hw_write(udc, reg, mask_xs|mask_xr,
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value ? mask_xs : mask_xr);
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} while (value != hw_ep_get_halt(udc, num, dir));
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return 0;
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@ -502,9 +547,8 @@ static int hw_intr_clear(struct ci13xxx *udc, int n)
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if (n >= REG_BITS)
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return -EINVAL;
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hw_write(udc->hw_bank.op, OP_USBINTR, BIT(n), 0);
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hw_write(udc->hw_bank.op, OP_USBSTS, BIT(n), BIT(n));
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hw_write(udc, OP_USBINTR, BIT(n), 0);
|
||||
hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -520,11 +564,10 @@ static int hw_intr_force(struct ci13xxx *udc, int n)
|
|||
if (n >= REG_BITS)
|
||||
return -EINVAL;
|
||||
|
||||
hw_write(udc->hw_bank.cap, ABS_TESTMODE, TESTMODE_FORCE,
|
||||
TESTMODE_FORCE);
|
||||
hw_write(udc->hw_bank.op, OP_USBINTR, BIT(n), BIT(n));
|
||||
hw_write(udc->hw_bank.op, OP_USBSTS, BIT(n), BIT(n));
|
||||
hw_write(udc->hw_bank.cap, ABS_TESTMODE, TESTMODE_FORCE, 0);
|
||||
hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
|
||||
hw_write(udc, OP_USBINTR, BIT(n), BIT(n));
|
||||
hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
|
||||
hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -535,9 +578,8 @@ static int hw_intr_force(struct ci13xxx *udc, int n)
|
|||
*/
|
||||
static int hw_port_is_high_speed(struct ci13xxx *udc)
|
||||
{
|
||||
return udc->hw_bank.lpm
|
||||
? hw_read(udc->hw_bank.op, OP_DEVLC, DEVLC_PSPD)
|
||||
: hw_read(udc->hw_bank.op, OP_PORTSC, PORTSC_HSP);
|
||||
return udc->hw_bank.lpm ? hw_read(udc, OP_DEVLC, DEVLC_PSPD) :
|
||||
hw_read(udc, OP_PORTSC, PORTSC_HSP);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -547,8 +589,7 @@ static int hw_port_is_high_speed(struct ci13xxx *udc)
|
|||
*/
|
||||
static u8 hw_port_test_get(struct ci13xxx *udc)
|
||||
{
|
||||
return hw_read(udc->hw_bank.op, OP_PORTSC, PORTSC_PTC) >>
|
||||
ffs_nr(PORTSC_PTC);
|
||||
return hw_read(udc, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -564,8 +605,7 @@ static int hw_port_test_set(struct ci13xxx *udc, u8 mode)
|
|||
if (mode > TEST_MODE_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
hw_write(udc->hw_bank.op, OP_PORTSC, PORTSC_PTC,
|
||||
mode << ffs_nr(PORTSC_PTC));
|
||||
hw_write(udc, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -576,7 +616,7 @@ static int hw_port_test_set(struct ci13xxx *udc, u8 mode)
|
|||
*/
|
||||
static u32 hw_read_intr_enable(struct ci13xxx *udc)
|
||||
{
|
||||
return hw_read(udc->hw_bank.op, OP_USBINTR, ~0);
|
||||
return hw_read(udc, OP_USBINTR, ~0);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -586,7 +626,7 @@ static u32 hw_read_intr_enable(struct ci13xxx *udc)
|
|||
*/
|
||||
static u32 hw_read_intr_status(struct ci13xxx *udc)
|
||||
{
|
||||
return hw_read(udc->hw_bank.op, OP_USBSTS, ~0);
|
||||
return hw_read(udc, OP_USBSTS, ~0);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -604,7 +644,7 @@ static size_t hw_register_read(struct ci13xxx *udc, u32 *buf, size_t size)
|
|||
size = udc->hw_bank.size;
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
buf[i] = hw_read(udc->hw_bank.cap, i * sizeof(u32), ~0);
|
||||
buf[i] = hw_read(udc, i * sizeof(u32), ~0);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
|
@ -627,7 +667,7 @@ static int hw_register_write(struct ci13xxx *udc, u16 addr, u32 data)
|
|||
/* align */
|
||||
addr *= sizeof(u32);
|
||||
|
||||
hw_write(udc->hw_bank.cap, addr, ~0, data);
|
||||
hw_write(udc, addr, ~0, data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -641,7 +681,7 @@ static int hw_register_write(struct ci13xxx *udc, u16 addr, u32 data)
|
|||
static int hw_test_and_clear_complete(struct ci13xxx *udc, int n)
|
||||
{
|
||||
n = ep_to_bit(udc, n);
|
||||
return hw_test_and_clear(udc->hw_bank.op, OP_ENDPTCOMPLETE, BIT(n));
|
||||
return hw_test_and_clear(udc, OP_ENDPTCOMPLETE, BIT(n));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -654,7 +694,7 @@ static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
|
|||
{
|
||||
u32 reg = hw_read_intr_status(udc) & hw_read_intr_enable(udc);
|
||||
|
||||
hw_write(udc->hw_bank.op, OP_USBSTS, ~0, reg);
|
||||
hw_write(udc, OP_USBSTS, ~0, reg);
|
||||
return reg;
|
||||
}
|
||||
|
||||
|
|
@ -666,7 +706,7 @@ static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
|
|||
*/
|
||||
static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
|
||||
{
|
||||
return hw_test_and_write(udc->hw_bank.op, OP_USBCMD, USBCMD_SUTW, 0);
|
||||
return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -677,8 +717,7 @@ static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
|
|||
*/
|
||||
static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
|
||||
{
|
||||
return hw_test_and_write(udc->hw_bank.op, OP_USBCMD, USBCMD_SUTW,
|
||||
USBCMD_SUTW);
|
||||
return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -690,8 +729,7 @@ static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
|
|||
static int hw_usb_set_address(struct ci13xxx *udc, u8 value)
|
||||
{
|
||||
/* advance */
|
||||
hw_write(udc->hw_bank.op, OP_DEVICEADDR,
|
||||
DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
|
||||
hw_write(udc, OP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
|
||||
value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -707,16 +745,16 @@ static int hw_usb_reset(struct ci13xxx *udc)
|
|||
hw_usb_set_address(udc, 0);
|
||||
|
||||
/* ESS flushes only at end?!? */
|
||||
hw_write(udc->hw_bank.op, OP_ENDPTFLUSH, ~0, ~0);
|
||||
hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
|
||||
|
||||
/* clear setup token semaphores */
|
||||
hw_write(udc->hw_bank.op, OP_ENDPTSETUPSTAT, 0, 0);
|
||||
hw_write(udc, OP_ENDPTSETUPSTAT, 0, 0);
|
||||
|
||||
/* clear complete status */
|
||||
hw_write(udc->hw_bank.op, OP_ENDPTCOMPLETE, 0, 0);
|
||||
hw_write(udc, OP_ENDPTCOMPLETE, 0, 0);
|
||||
|
||||
/* wait until all bits cleared */
|
||||
while (hw_read(udc->hw_bank.op, OP_ENDPTPRIME, ~0))
|
||||
while (hw_read(udc, OP_ENDPTPRIME, ~0))
|
||||
udelay(10); /* not RTOS friendly */
|
||||
|
||||
/* reset all endpoints ? */
|
||||
|
|
@ -1500,15 +1538,13 @@ static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
|
|||
else
|
||||
mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
|
||||
wmb();
|
||||
if (hw_read(udc->hw_bank.op, OP_ENDPTPRIME, BIT(n)))
|
||||
if (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
|
||||
goto done;
|
||||
do {
|
||||
hw_write(udc->hw_bank.op, OP_USBCMD, USBCMD_ATDTW,
|
||||
USBCMD_ATDTW);
|
||||
tmp_stat = hw_read(udc->hw_bank.op, OP_ENDPTSTAT,
|
||||
BIT(n));
|
||||
} while (!hw_read(udc->hw_bank.op, OP_USBCMD, USBCMD_ATDTW));
|
||||
hw_write(udc->hw_bank.op, OP_USBCMD, USBCMD_ATDTW, 0);
|
||||
hw_write(udc, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
|
||||
tmp_stat = hw_read(udc, OP_ENDPTSTAT, BIT(n));
|
||||
} while (!hw_read(udc, OP_USBCMD, USBCMD_ATDTW));
|
||||
hw_write(udc, OP_USBCMD, USBCMD_ATDTW, 0);
|
||||
if (tmp_stat)
|
||||
goto done;
|
||||
}
|
||||
|
|
@ -2513,12 +2549,12 @@ static int ci13xxx_wakeup(struct usb_gadget *_gadget)
|
|||
trace("remote wakeup feature is not enabled\n");
|
||||
goto out;
|
||||
}
|
||||
if (!hw_read(udc->hw_bank.op, OP_PORTSC, PORTSC_SUSP)) {
|
||||
if (!hw_read(udc, OP_PORTSC, PORTSC_SUSP)) {
|
||||
ret = -EINVAL;
|
||||
trace("port is not suspended\n");
|
||||
goto out;
|
||||
}
|
||||
hw_write(udc->hw_bank.op, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
|
||||
hw_write(udc, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
|
||||
out:
|
||||
spin_unlock_irqrestore(&udc->lock, flags);
|
||||
return ret;
|
||||
|
|
@ -2786,7 +2822,7 @@ static irqreturn_t udc_irq(void)
|
|||
spin_lock(&udc->lock);
|
||||
|
||||
if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
|
||||
if (hw_read(udc->hw_bank.op, OP_USBMODE, USBMODE_CM) !=
|
||||
if (hw_read(udc, OP_USBMODE, USBMODE_CM) !=
|
||||
USBMODE_CM_DEVICE) {
|
||||
spin_unlock(&udc->lock);
|
||||
return IRQ_NONE;
|
||||
|
|
@ -2993,6 +3029,7 @@ static void udc_remove(void)
|
|||
#endif
|
||||
device_unregister(&udc->gadget.dev);
|
||||
|
||||
kfree(udc->hw_bank.regmap);
|
||||
kfree(udc);
|
||||
_udc = NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -120,6 +120,7 @@ struct hw_bank {
|
|||
void __iomem *cap; /* bus map offset + CAP offset */
|
||||
void __iomem *op; /* bus map offset + OP offset */
|
||||
size_t size; /* bank size */
|
||||
void *__iomem *regmap;
|
||||
};
|
||||
|
||||
/* CI13XXX UDC descriptor & global resources */
|
||||
|
|
@ -158,6 +159,31 @@ struct ci13xxx {
|
|||
/* register size */
|
||||
#define REG_BITS (32)
|
||||
|
||||
/* register indices */
|
||||
enum ci13xxx_regs {
|
||||
CAP_CAPLENGTH,
|
||||
CAP_HCCPARAMS,
|
||||
CAP_DCCPARAMS,
|
||||
CAP_TESTMODE,
|
||||
CAP_LAST = CAP_TESTMODE,
|
||||
OP_USBCMD,
|
||||
OP_USBSTS,
|
||||
OP_USBINTR,
|
||||
OP_DEVICEADDR,
|
||||
OP_ENDPTLISTADDR,
|
||||
OP_PORTSC,
|
||||
OP_DEVLC,
|
||||
OP_USBMODE,
|
||||
OP_ENDPTSETUPSTAT,
|
||||
OP_ENDPTPRIME,
|
||||
OP_ENDPTFLUSH,
|
||||
OP_ENDPTSTAT,
|
||||
OP_ENDPTCOMPLETE,
|
||||
OP_ENDPTCTRL,
|
||||
/* endptctrl1..15 follow */
|
||||
OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
|
||||
};
|
||||
|
||||
/* HCCPARAMS */
|
||||
#define HCCPARAMS_LEN BIT(17)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue