staging:iio:light: V3 fix out of bounds reg_cache[] access
V3 is a straightforward forward port to teh current tree of V2. Simple fix is to just not cache REG_TEST (offset 8). Cache doesn't help REG_TEST anyway since we write all 8 bits exactly once (at resume/init time). Also fix an "off-by-one" allocation of reg_cache[] array size that was in the original code before I touched it. Reported-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Grant Grundler <grundler@chromium.org> Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -51,7 +51,7 @@
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#define ISL29018_REG_ADD_DATA_LSB 0x02
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#define ISL29018_REG_ADD_DATA_MSB 0x03
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#define ISL29018_MAX_REGS ISL29018_REG_ADD_DATA_MSB
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#define ISL29018_MAX_REGS (ISL29018_REG_ADD_DATA_MSB+1)
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#define ISL29018_REG_TEST 0x08
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#define ISL29018_TEST_SHIFT 0
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@ -70,22 +70,27 @@ struct isl29018_chip {
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static int isl29018_write_data(struct i2c_client *client, u8 reg,
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u8 val, u8 mask, u8 shift)
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{
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u8 regval;
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int ret = 0;
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u8 regval = val;
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int ret;
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struct isl29018_chip *chip = iio_priv(i2c_get_clientdata(client));
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regval = chip->reg_cache[reg];
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regval &= ~mask;
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regval |= val << shift;
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/* don't cache or mask REG_TEST */
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if (reg < ISL29018_MAX_REGS) {
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regval = chip->reg_cache[reg];
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regval &= ~mask;
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regval |= val << shift;
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}
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ret = i2c_smbus_write_byte_data(client, reg, regval);
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if (ret) {
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dev_err(&client->dev, "Write to device fails status %x\n", ret);
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return ret;
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} else {
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/* don't update cache on err */
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if (reg < ISL29018_MAX_REGS)
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chip->reg_cache[reg] = regval;
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}
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chip->reg_cache[reg] = regval;
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return 0;
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return ret;
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}
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static int isl29018_set_range(struct i2c_client *client, unsigned long range,
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