Merge commit 'kumar/next' into merge
This commit is contained in:
Benjamin Herrenschmidt
commit
2593f939a5
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@ -0,0 +1,42 @@
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|||
* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores
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||||
The OpenPIC specification does not specify which interrupt source has to
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become which interrupt number. This is up to the software implementation
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of the interrupt controller. The only requirement is that every
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interrupt source has to have an unique interrupt number / vector number.
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To accomplish this the current implementation assigns the number zero to
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the first source, the number one to the second source and so on until
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all interrupt sources have their unique number.
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Usually the assigned vector number equals the interrupt number mentioned
|
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in the documentation for a given core / CPU. This is however not true
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for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
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between internal and external interrupt sources and starts counting at
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zero for both of them.
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So what to write for external interrupt source X or internal interrupt
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source Y into the device tree? Here is an example:
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The memory map for the interrupt controller in the MPC8544[0] shows,
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that the first interrupt source starts at 0x5_0000 (PIC Register Address
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Map-Interrupt Source Configuration Registers). This source becomes the
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number zero therefore:
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External interrupt 0 = interrupt number 0
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External interrupt 1 = interrupt number 1
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External interrupt 2 = interrupt number 2
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...
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Every interrupt number allocates 0x20 bytes register space. So to get
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its number it is sufficient to shift the lower 16bits to right by five.
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So for the external interrupt 10 we have:
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0x0140 >> 5 = 10
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After the external sources, the internal sources follow. The in core I2C
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controller on the MPC8544 for instance has the internal source number
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27. Oo obtain its interrupt number we take the lower 16bits of its memory
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address (0x5_0560) and shift it right:
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0x0560 >> 5 = 43
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Therefore the I2C device node for the MPC8544 CPU has to have the
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interrupt number 43 specified in the device tree.
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[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual
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MPC8544ERM Rev. 1 10/2007
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@ -204,6 +204,7 @@
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interrupt-parent = <&ipic>;
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tbi-handle = <&tbi0>;
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phy-handle = < &phy0 >;
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fsl,magic-packet;
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mdio@520 {
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#address-cells = <1>;
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@ -246,6 +247,7 @@
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interrupt-parent = <&ipic>;
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tbi-handle = <&tbi1>;
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phy-handle = < &phy1 >;
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fsl,magic-packet;
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mdio@520 {
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#address-cells = <1>;
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|
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@ -309,6 +311,22 @@
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interrupt-parent = <&ipic>;
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};
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gtm1: timer@500 {
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compatible = "fsl,mpc8315-gtm", "fsl,gtm";
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reg = <0x500 0x100>;
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interrupts = <90 8 78 8 84 8 72 8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <133333333>;
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};
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timer@600 {
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compatible = "fsl,mpc8315-gtm", "fsl,gtm";
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reg = <0x600 0x100>;
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interrupts = <91 8 79 8 85 8 73 8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <133333333>;
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};
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/* IPIC
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* interrupts cell = <intr #, sense>
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* sense values match linux IORESOURCE_IRQ_* defines:
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|
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@ -337,6 +355,15 @@
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0x59 0x8>;
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interrupt-parent = < &ipic >;
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};
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pmc: power@b00 {
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compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
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"fsl,mpc8349-pmc";
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reg = <0xb00 0x100 0xa00 0x100>;
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interrupts = <80 8>;
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interrupt-parent = <&ipic>;
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fsl,mpc8313-wakeup-timer = <>m1>;
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};
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};
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pci0: pci@e0008500 {
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|
|
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|
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@ -63,6 +63,24 @@
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reg = <0x200 0x100>;
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};
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|
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gpio1: gpio-controller@c00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8349-gpio";
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reg = <0xc00 0x100>;
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interrupts = <74 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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};
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|
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gpio2: gpio-controller@d00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8349-gpio";
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reg = <0xd00 0x100>;
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interrupts = <75 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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};
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|
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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|
|
@ -72,6 +90,12 @@
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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eeprom: at24@50 {
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compatible = "st-micro,24c256";
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reg = <0x50>;
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};
|
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|
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};
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i2c@3100 {
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|
|
@ -91,6 +115,25 @@
|
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interrupt-parent = <&ipic>;
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};
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pcf1: iexp@38 {
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#gpio-cells = <2>;
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compatible = "ti,pcf8574a";
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reg = <0x38>;
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gpio-controller;
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};
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pcf2: iexp@39 {
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#gpio-cells = <2>;
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compatible = "ti,pcf8574a";
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reg = <0x39>;
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gpio-controller;
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};
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spd: at24@51 {
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compatible = "at24,spd";
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reg = <0x51>;
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};
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|
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mcu_pio: mcu@a {
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#gpio-cells = <2>;
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compatible = "fsl,mc9s08qg8-mpc8349emitx",
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|
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@ -275,6 +318,24 @@
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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|
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gpio-leds {
|
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compatible = "gpio-leds";
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|
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green {
|
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label = "Green";
|
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gpios = <&pcf1 0 1>;
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linux,default-trigger = "heartbeat";
|
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};
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yellow {
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label = "Yellow";
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gpios = <&pcf1 1 1>;
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/* linux,default-trigger = "heartbeat"; */
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default-state = "on";
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};
|
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};
|
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|
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};
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|
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pci0: pci@e0008500 {
|
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|
|
@ -331,7 +392,26 @@
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|||
compatible = "fsl,mpc8349e-localbus",
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"fsl,pq2pro-localbus";
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reg = <0xe0005000 0xd8>;
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ranges = <0x3 0x0 0xf0000000 0x210>;
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ranges = <0x0 0x0 0xfe000000 0x1000000 /* flash */
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0x1 0x0 0xf8000000 0x20000 /* VSC 7385 */
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0x2 0x0 0xf9000000 0x200000 /* exp slot */
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0x3 0x0 0xf0000000 0x210>; /* CF slot */
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|
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x800000>;
|
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bank-width = <2>;
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device-width = <1>;
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};
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|
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flash@0,800000 {
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#address-cells = <1>;
|
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x800000 0x800000>;
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bank-width = <2>;
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device-width = <1>;
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};
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|
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pata@3,0 {
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compatible = "fsl,mpc8349emitx-pata", "ata-generic";
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|
|
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|||
|
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@ -38,12 +38,9 @@ static inline int gpio_cansleep(unsigned int gpio)
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return __gpio_cansleep(gpio);
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}
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/*
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* Not implemented, yet.
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*/
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static inline int gpio_to_irq(unsigned int gpio)
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{
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return -ENOSYS;
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return __gpio_to_irq(gpio);
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}
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static inline int irq_to_gpio(unsigned int irq)
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|
|
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|
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@ -32,6 +32,7 @@
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#define PMCCR1_NEXT_STATE 0x0C /* Next state for power management */
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#define PMCCR1_NEXT_STATE_SHIFT 2
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#define PMCCR1_CURR_STATE 0x03 /* Current state for power management*/
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#define IMMR_SYSCR_OFFSET 0x100
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#define IMMR_RCW_OFFSET 0x900
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#define RCW_PCI_HOST 0x80000000
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@ -78,6 +79,22 @@ struct mpc83xx_clock {
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u32 sccr;
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};
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struct mpc83xx_syscr {
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__be32 sgprl;
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__be32 sgprh;
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__be32 spridr;
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__be32 :32;
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__be32 spcr;
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__be32 sicrl;
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__be32 sicrh;
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};
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|
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struct mpc83xx_saved {
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u32 sicrl;
|
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u32 sicrh;
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u32 sccr;
|
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};
|
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|
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struct pmc_type {
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int has_deep_sleep;
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};
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|
@ -87,6 +104,8 @@ static int has_deep_sleep, deep_sleeping;
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static int pmc_irq;
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static struct mpc83xx_pmc __iomem *pmc_regs;
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static struct mpc83xx_clock __iomem *clock_regs;
|
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static struct mpc83xx_syscr __iomem *syscr_regs;
|
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static struct mpc83xx_saved saved_regs;
|
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static int is_pci_agent, wake_from_pci;
|
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static phys_addr_t immrbase;
|
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static int pci_pm_state;
|
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|
|
@ -137,6 +156,20 @@ static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
|
|||
return ret;
|
||||
}
|
||||
|
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static void mpc83xx_suspend_restore_regs(void)
|
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{
|
||||
out_be32(&syscr_regs->sicrl, saved_regs.sicrl);
|
||||
out_be32(&syscr_regs->sicrh, saved_regs.sicrh);
|
||||
out_be32(&clock_regs->sccr, saved_regs.sccr);
|
||||
}
|
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|
||||
static void mpc83xx_suspend_save_regs(void)
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||||
{
|
||||
saved_regs.sicrl = in_be32(&syscr_regs->sicrl);
|
||||
saved_regs.sicrh = in_be32(&syscr_regs->sicrh);
|
||||
saved_regs.sccr = in_be32(&clock_regs->sccr);
|
||||
}
|
||||
|
||||
static int mpc83xx_suspend_enter(suspend_state_t state)
|
||||
{
|
||||
int ret = -EAGAIN;
|
||||
|
|
@ -166,6 +199,8 @@ static int mpc83xx_suspend_enter(suspend_state_t state)
|
|||
*/
|
||||
|
||||
if (deep_sleeping) {
|
||||
mpc83xx_suspend_save_regs();
|
||||
|
||||
out_be32(&pmc_regs->mask, PMCER_ALL);
|
||||
|
||||
out_be32(&pmc_regs->config1,
|
||||
|
|
@ -179,6 +214,8 @@ static int mpc83xx_suspend_enter(suspend_state_t state)
|
|||
in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
|
||||
|
||||
out_be32(&pmc_regs->mask, PMCER_PMCI);
|
||||
|
||||
mpc83xx_suspend_restore_regs();
|
||||
} else {
|
||||
out_be32(&pmc_regs->mask, PMCER_PMCI);
|
||||
|
||||
|
|
@ -194,7 +231,7 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void mpc83xx_suspend_finish(void)
|
||||
static void mpc83xx_suspend_end(void)
|
||||
{
|
||||
deep_sleeping = 0;
|
||||
}
|
||||
|
|
@ -278,7 +315,7 @@ static struct platform_suspend_ops mpc83xx_suspend_ops = {
|
|||
.valid = mpc83xx_suspend_valid,
|
||||
.begin = mpc83xx_suspend_begin,
|
||||
.enter = mpc83xx_suspend_enter,
|
||||
.finish = mpc83xx_suspend_finish,
|
||||
.end = mpc83xx_suspend_end,
|
||||
};
|
||||
|
||||
static int pmc_probe(struct of_device *ofdev,
|
||||
|
|
@ -333,12 +370,23 @@ static int pmc_probe(struct of_device *ofdev,
|
|||
goto out_pmc;
|
||||
}
|
||||
|
||||
if (has_deep_sleep) {
|
||||
syscr_regs = ioremap(immrbase + IMMR_SYSCR_OFFSET,
|
||||
sizeof(*syscr_regs));
|
||||
if (!syscr_regs) {
|
||||
ret = -ENOMEM;
|
||||
goto out_syscr;
|
||||
}
|
||||
}
|
||||
|
||||
if (is_pci_agent)
|
||||
mpc83xx_set_agent();
|
||||
|
||||
suspend_set_ops(&mpc83xx_suspend_ops);
|
||||
return 0;
|
||||
|
||||
out_syscr:
|
||||
iounmap(clock_regs);
|
||||
out_pmc:
|
||||
iounmap(pmc_regs);
|
||||
out:
|
||||
|
|
|
|||
|
|
@ -143,13 +143,23 @@ static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
|
|||
struct irq_desc *desc = irq_to_desc(virq);
|
||||
unsigned int vold, vnew, edibit;
|
||||
|
||||
if (flow_type == IRQ_TYPE_NONE)
|
||||
flow_type = IRQ_TYPE_LEVEL_LOW;
|
||||
/* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
|
||||
* IRQ_TYPE_EDGE_BOTH (default). All others are IRQ_TYPE_EDGE_FALLING
|
||||
* or IRQ_TYPE_LEVEL_LOW (default)
|
||||
*/
|
||||
if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) {
|
||||
if (flow_type == IRQ_TYPE_NONE)
|
||||
flow_type = IRQ_TYPE_EDGE_BOTH;
|
||||
|
||||
if (flow_type & IRQ_TYPE_EDGE_RISING) {
|
||||
printk(KERN_ERR "CPM2 PIC: sense type 0x%x not supported\n",
|
||||
flow_type);
|
||||
return -EINVAL;
|
||||
if (flow_type != IRQ_TYPE_EDGE_BOTH &&
|
||||
flow_type != IRQ_TYPE_EDGE_FALLING)
|
||||
goto err_sense;
|
||||
} else {
|
||||
if (flow_type == IRQ_TYPE_NONE)
|
||||
flow_type = IRQ_TYPE_LEVEL_LOW;
|
||||
|
||||
if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
|
||||
goto err_sense;
|
||||
}
|
||||
|
||||
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
|
||||
|
|
@ -181,6 +191,10 @@ static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
|
|||
if (vold != vnew)
|
||||
out_be32(&cpm2_intctl->ic_siexr, vnew);
|
||||
return 0;
|
||||
|
||||
err_sense:
|
||||
pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct irq_chip cpm2_pic = {
|
||||
|
|
|
|||
|
|
@ -464,8 +464,7 @@ static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
|
|||
{
|
||||
struct pci_controller *hose = pci_bus_to_host(bus);
|
||||
struct mpc83xx_pcie_priv *pcie = hose->dn->data;
|
||||
u8 bus_no = bus->number - hose->first_busno;
|
||||
u32 dev_base = bus_no << 24 | devfn << 16;
|
||||
u32 dev_base = bus->number << 24 | devfn << 16;
|
||||
int ret;
|
||||
|
||||
ret = mpc83xx_pcie_exclude_device(bus, devfn);
|
||||
|
|
@ -515,12 +514,17 @@ static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
|
|||
static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 val)
|
||||
{
|
||||
struct pci_controller *hose = pci_bus_to_host(bus);
|
||||
void __iomem *cfg_addr;
|
||||
|
||||
cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
|
||||
if (!cfg_addr)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
/* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
|
||||
if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
|
||||
val &= 0xffffff00;
|
||||
|
||||
switch (len) {
|
||||
case 1:
|
||||
out_8(cfg_addr, val);
|
||||
|
|
|
|||
|
|
@ -54,6 +54,22 @@ static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
|
|||
mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
|
||||
}
|
||||
|
||||
/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
|
||||
* defined as output cannot be determined by reading GPDAT register,
|
||||
* so we use shadow data register instead. The status of input pins
|
||||
* is determined by reading GPDAT register.
|
||||
*/
|
||||
static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
u32 val;
|
||||
struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
|
||||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
|
||||
|
||||
val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
|
||||
|
||||
return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
|
||||
}
|
||||
|
||||
static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
|
||||
|
|
@ -136,7 +152,10 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
|
|||
gc->ngpio = MPC8XXX_GPIO_PINS;
|
||||
gc->direction_input = mpc8xxx_gpio_dir_in;
|
||||
gc->direction_output = mpc8xxx_gpio_dir_out;
|
||||
gc->get = mpc8xxx_gpio_get;
|
||||
if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
|
||||
gc->get = mpc8572_gpio_get;
|
||||
else
|
||||
gc->get = mpc8xxx_gpio_get;
|
||||
gc->set = mpc8xxx_gpio_set;
|
||||
|
||||
ret = of_mm_gpiochip_add(np, mm_gc);
|
||||
|
|
|
|||
Loading…
Reference in New Issue