Merge branch 'stmmac-fixes'
Ong Boon Leong says: ==================== net: stmmac: general fixes for Ethernet functionality 1/5: It ensures that the previous value of GMAC_VLAN_TAG register is read first before for updating the register. 2/5: Similar to 2/6 patch but it is a fix for XGMAC_VLAN_TAG register as requested by Jose Abreu. 3/5: It ensures the GMAC IP v4.xx and above behaves correctly to:- ip link set <devname> multicast off|on 4/5: Added similar IFF_MULTICAST flag for xgmac2, similar to 4/6. 5/5: It ensures PCI platform data is using plat->phy_interface. Changes from v4:- patch 1/6 - this patch is dropped now and will take the input on handling return value from netif_set_real_num_rx| tx_queues() in future patch series. v3:- patch 1/6 - add rtnl_lock() and rtnl_unlock() for stmmac_hw_setup() called inside stmmac_resume() patch 3/6 - Added new patch to fix XGMAC_VLAN_TAG register writting v2:- patch 1/5 - added control for rtnl_lock() & rtnl_unlock() to ensure they are used forstmmac_resume() patch 4/5 - added IFF_MULTICAST flag check for xgmac to ensure multicast works correctly. v1:- - Drop v1 patches (1/7, 3/7 & 4/7) that are not valid. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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commit
259039fa30
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@ -420,7 +420,7 @@ static void dwmac4_set_filter(struct mac_device_info *hw,
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value |= GMAC_PACKET_FILTER_PM;
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value |= GMAC_PACKET_FILTER_PM;
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/* Set all the bits of the HASH tab */
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/* Set all the bits of the HASH tab */
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memset(mc_filter, 0xff, sizeof(mc_filter));
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memset(mc_filter, 0xff, sizeof(mc_filter));
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} else if (!netdev_mc_empty(dev)) {
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} else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
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struct netdev_hw_addr *ha;
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struct netdev_hw_addr *ha;
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/* Hash filter for multicast */
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/* Hash filter for multicast */
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@ -736,11 +736,14 @@ static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
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__le16 perfect_match, bool is_double)
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__le16 perfect_match, bool is_double)
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{
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{
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void __iomem *ioaddr = hw->pcsr;
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
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writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
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value = readl(ioaddr + GMAC_VLAN_TAG);
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if (hash) {
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if (hash) {
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u32 value = GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
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value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
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if (is_double) {
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if (is_double) {
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value |= GMAC_VLAN_EDVLP;
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value |= GMAC_VLAN_EDVLP;
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value |= GMAC_VLAN_ESVL;
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value |= GMAC_VLAN_ESVL;
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@ -759,8 +762,6 @@ static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
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writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
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writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
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} else {
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} else {
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u32 value = readl(ioaddr + GMAC_VLAN_TAG);
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value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
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value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
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value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
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value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
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value &= ~GMAC_VLAN_DOVLTC;
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value &= ~GMAC_VLAN_DOVLTC;
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@ -458,7 +458,7 @@ static void dwxgmac2_set_filter(struct mac_device_info *hw,
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for (i = 0; i < XGMAC_MAX_HASH_TABLE; i++)
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for (i = 0; i < XGMAC_MAX_HASH_TABLE; i++)
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writel(~0x0, ioaddr + XGMAC_HASH_TABLE(i));
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writel(~0x0, ioaddr + XGMAC_HASH_TABLE(i));
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} else if (!netdev_mc_empty(dev)) {
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} else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
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struct netdev_hw_addr *ha;
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struct netdev_hw_addr *ha;
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value |= XGMAC_FILTER_HMC;
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value |= XGMAC_FILTER_HMC;
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@ -569,7 +569,9 @@ static void dwxgmac2_update_vlan_hash(struct mac_device_info *hw, u32 hash,
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writel(value, ioaddr + XGMAC_PACKET_FILTER);
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writel(value, ioaddr + XGMAC_PACKET_FILTER);
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value = XGMAC_VLAN_VTHM | XGMAC_VLAN_ETV;
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value = readl(ioaddr + XGMAC_VLAN_TAG);
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value |= XGMAC_VLAN_VTHM | XGMAC_VLAN_ETV;
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if (is_double) {
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if (is_double) {
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value |= XGMAC_VLAN_EDVLP;
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value |= XGMAC_VLAN_EDVLP;
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value |= XGMAC_VLAN_ESVL;
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value |= XGMAC_VLAN_ESVL;
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@ -584,7 +586,9 @@ static void dwxgmac2_update_vlan_hash(struct mac_device_info *hw, u32 hash,
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writel(value, ioaddr + XGMAC_PACKET_FILTER);
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writel(value, ioaddr + XGMAC_PACKET_FILTER);
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value = XGMAC_VLAN_ETV;
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value = readl(ioaddr + XGMAC_VLAN_TAG);
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value |= XGMAC_VLAN_ETV;
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if (is_double) {
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if (is_double) {
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value |= XGMAC_VLAN_EDVLP;
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value |= XGMAC_VLAN_EDVLP;
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value |= XGMAC_VLAN_ESVL;
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value |= XGMAC_VLAN_ESVL;
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@ -95,7 +95,7 @@ static int stmmac_default_data(struct pci_dev *pdev,
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plat->bus_id = 1;
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plat->bus_id = 1;
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plat->phy_addr = 0;
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plat->phy_addr = 0;
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plat->interface = PHY_INTERFACE_MODE_GMII;
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plat->phy_interface = PHY_INTERFACE_MODE_GMII;
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plat->dma_cfg->pbl = 32;
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plat->dma_cfg->pbl = 32;
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plat->dma_cfg->pblx8 = true;
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plat->dma_cfg->pblx8 = true;
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@ -217,7 +217,8 @@ static int ehl_sgmii_data(struct pci_dev *pdev,
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{
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{
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plat->bus_id = 1;
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plat->bus_id = 1;
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plat->phy_addr = 0;
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plat->phy_addr = 0;
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plat->interface = PHY_INTERFACE_MODE_SGMII;
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plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
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return ehl_common_data(pdev, plat);
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return ehl_common_data(pdev, plat);
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}
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}
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@ -230,7 +231,8 @@ static int ehl_rgmii_data(struct pci_dev *pdev,
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{
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{
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plat->bus_id = 1;
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plat->bus_id = 1;
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plat->phy_addr = 0;
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plat->phy_addr = 0;
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plat->interface = PHY_INTERFACE_MODE_RGMII;
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plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
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return ehl_common_data(pdev, plat);
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return ehl_common_data(pdev, plat);
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}
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}
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@ -258,7 +260,7 @@ static int tgl_sgmii_data(struct pci_dev *pdev,
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{
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{
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plat->bus_id = 1;
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plat->bus_id = 1;
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plat->phy_addr = 0;
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plat->phy_addr = 0;
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plat->interface = PHY_INTERFACE_MODE_SGMII;
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plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
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return tgl_common_data(pdev, plat);
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return tgl_common_data(pdev, plat);
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}
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}
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@ -358,7 +360,7 @@ static int quark_default_data(struct pci_dev *pdev,
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plat->bus_id = pci_dev_id(pdev);
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plat->bus_id = pci_dev_id(pdev);
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plat->phy_addr = ret;
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plat->phy_addr = ret;
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plat->interface = PHY_INTERFACE_MODE_RMII;
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plat->phy_interface = PHY_INTERFACE_MODE_RMII;
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plat->dma_cfg->pbl = 16;
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plat->dma_cfg->pbl = 16;
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plat->dma_cfg->pblx8 = true;
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plat->dma_cfg->pblx8 = true;
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@ -415,7 +417,7 @@ static int snps_gmac5_default_data(struct pci_dev *pdev,
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plat->bus_id = 1;
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plat->bus_id = 1;
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plat->phy_addr = -1;
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plat->phy_addr = -1;
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plat->interface = PHY_INTERFACE_MODE_GMII;
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plat->phy_interface = PHY_INTERFACE_MODE_GMII;
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plat->dma_cfg->pbl = 32;
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plat->dma_cfg->pbl = 32;
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plat->dma_cfg->pblx8 = true;
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plat->dma_cfg->pblx8 = true;
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