hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem 

Conflicts:
	drivers/net/wireless/ath/ar9170/main.c
	drivers/net/wireless/ath/ar9170/phy.c
	drivers/net/wireless/zd1211rw/zd_rf_rf2959.c
This commit is contained in:
John W. Linville 2011-04-12 16:18:44 -04:00
parent 6ba1037c3d b37e3b6d64
commit 252f4bf400
230 changed files with 29848 additions and 12682 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
Documentation/feature-removal-schedule.txt
View File

@ -35,17 +35,6 @@ Who: Luis R. Rodriguez <lrodriguez@atheros.com>
---------------------------
What: AR9170USB
When: 2.6.40
Why: This driver is deprecated and the firmware is no longer
maintained. The replacement driver "carl9170" has been
around for a while, so the devices are still supported.
Who: Christian Lamparter <chunkeey@googlemail.com>
---------------------------
What: IRQF_SAMPLE_RANDOM
Check: IRQF_SAMPLE_RANDOM
When: July 2009

13
MAINTAINERS
View File

@ -1224,13 +1224,6 @@ W: http://wireless.kernel.org/en/users/Drivers/ath9k
S: Supported
F: drivers/net/wireless/ath/ath9k/
ATHEROS AR9170 WIRELESS DRIVER
M: Christian Lamparter <chunkeey@web.de>
L: linux-wireless@vger.kernel.org
W: http://wireless.kernel.org/en/users/Drivers/ar9170
S: Obsolete
F: drivers/net/wireless/ath/ar9170/
CARL9170 LINUX COMMUNITY WIRELESS DRIVER
M: Christian Lamparter <chunkeey@googlemail.com>
L: linux-wireless@vger.kernel.org
@ -3355,6 +3348,12 @@ F: Documentation/wimax/README.i2400m
F: drivers/net/wimax/i2400m/
F: include/linux/wimax/i2400m.h
INTEL WIRELESS 3945ABG/BG, 4965AGN (iwlegacy)
M: Stanislaw Gruszka <sgruszka@redhat.com>
L: linux-wireless@vger.kernel.org
S: Supported
F: drivers/net/wireless/iwlegacy/
INTEL WIRELESS WIFI LINK (iwlwifi)
M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>

1
drivers/net/wireless/Kconfig
View File

@ -284,5 +284,6 @@ source "drivers/net/wireless/rtlwifi/Kconfig"
source "drivers/net/wireless/wl1251/Kconfig"
source "drivers/net/wireless/wl12xx/Kconfig"
source "drivers/net/wireless/zd1211rw/Kconfig"
source "drivers/net/wireless/mwifiex/Kconfig"
endif # WLAN

2
drivers/net/wireless/Makefile
View File

@ -56,3 +56,5 @@ obj-$(CONFIG_WL12XX) += wl12xx/
obj-$(CONFIG_WL12XX_PLATFORM_DATA) += wl12xx/
obj-$(CONFIG_IWM) += iwmc3200wifi/
obj-$(CONFIG_MWIFIEX) += mwifiex/

1
drivers/net/wireless/ath/Kconfig
View File

@ -24,7 +24,6 @@ config ATH_DEBUG
source "drivers/net/wireless/ath/ath5k/Kconfig"
source "drivers/net/wireless/ath/ath9k/Kconfig"
source "drivers/net/wireless/ath/ar9170/Kconfig"
source "drivers/net/wireless/ath/carl9170/Kconfig"
endif

1
drivers/net/wireless/ath/Makefile
View File

@ -1,6 +1,5 @@
obj-$(CONFIG_ATH5K) += ath5k/
obj-$(CONFIG_ATH9K_HW) += ath9k/
obj-$(CONFIG_AR9170_USB) += ar9170/
obj-$(CONFIG_CARL9170) += carl9170/
obj-$(CONFIG_ATH_COMMON) += ath.o

20
drivers/net/wireless/ath/ar9170/Kconfig
View File

@ -1,20 +0,0 @@
config AR9170_USB
tristate "Atheros AR9170 802.11n USB support (OBSOLETE)"
depends on USB && MAC80211
select FW_LOADER
help
This driver is going to get replaced by carl9170.
This is a driver for the Atheros "otus" 802.11n USB devices.
These devices require additional firmware (2 files).
For now, these files can be downloaded from here:
http://wireless.kernel.org/en/users/Drivers/ar9170
If you choose to build a module, it'll be called ar9170usb.
config AR9170_LEDS
bool
depends on AR9170_USB && MAC80211_LEDS && (LEDS_CLASS = y || LEDS_CLASS = AR9170_USB)
default y

3
drivers/net/wireless/ath/ar9170/Makefile
View File

@ -1,3 +0,0 @@
ar9170usb-objs := usb.o main.o cmd.o mac.o phy.o led.o
obj-$(CONFIG_AR9170_USB) += ar9170usb.o

258
drivers/net/wireless/ath/ar9170/ar9170.h
View File

@ -1,258 +0,0 @@
/*
* Atheros AR9170 driver
*
* Driver specific definitions
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR9170_H
#define __AR9170_H
#include <linux/completion.h>
#include <linux/spinlock.h>
#include <net/cfg80211.h>
#include <net/mac80211.h>
#ifdef CONFIG_AR9170_LEDS
#include <linux/leds.h>
#endif /* CONFIG_AR9170_LEDS */
#include "eeprom.h"
#include "hw.h"
#include "../regd.h"
#define PAYLOAD_MAX (AR9170_MAX_CMD_LEN/4 - 1)
enum ar9170_bw {
AR9170_BW_20,
AR9170_BW_40_BELOW,
AR9170_BW_40_ABOVE,
__AR9170_NUM_BW,
};
static inline enum ar9170_bw nl80211_to_ar9170(enum nl80211_channel_type type)
{
switch (type) {
case NL80211_CHAN_NO_HT:
case NL80211_CHAN_HT20:
return AR9170_BW_20;
case NL80211_CHAN_HT40MINUS:
return AR9170_BW_40_BELOW;
case NL80211_CHAN_HT40PLUS:
return AR9170_BW_40_ABOVE;
default:
BUG();
}
}
enum ar9170_rf_init_mode {
AR9170_RFI_NONE,
AR9170_RFI_WARM,
AR9170_RFI_COLD,
};
#define AR9170_MAX_RX_BUFFER_SIZE 8192
#ifdef CONFIG_AR9170_LEDS
struct ar9170;
struct ar9170_led {
struct ar9170 *ar;
struct led_classdev l;
char name[32];
unsigned int toggled;
bool last_state;
bool registered;
};
#endif /* CONFIG_AR9170_LEDS */
enum ar9170_device_state {
AR9170_UNKNOWN_STATE,
AR9170_STOPPED,
AR9170_IDLE,
AR9170_STARTED,
};
struct ar9170_rxstream_mpdu_merge {
struct ar9170_rx_head plcp;
bool has_plcp;
};
struct ar9170_tx_queue_stats {
unsigned int len;
unsigned int limit;
unsigned int count;
};
#define AR9170_QUEUE_TIMEOUT 64
#define AR9170_TX_TIMEOUT 8
#define AR9170_JANITOR_DELAY 128
#define AR9170_TX_INVALID_RATE 0xffffffff
#define AR9170_NUM_TX_LIMIT_HARD AR9170_TXQ_DEPTH
#define AR9170_NUM_TX_LIMIT_SOFT (AR9170_TXQ_DEPTH - 10)
struct ar9170 {
struct ieee80211_hw *hw;
struct ath_common common;
struct mutex mutex;
enum ar9170_device_state state;
bool registered;
unsigned long bad_hw_nagger;
int (*open)(struct ar9170 *);
void (*stop)(struct ar9170 *);
int (*tx)(struct ar9170 *, struct sk_buff *);
int (*exec_cmd)(struct ar9170 *, enum ar9170_cmd, u32 ,
void *, u32 , void *);
void (*callback_cmd)(struct ar9170 *, u32 , void *);
int (*flush)(struct ar9170 *);
/* interface mode settings */
struct ieee80211_vif *vif;
/* beaconing */
struct sk_buff *beacon;
struct work_struct beacon_work;
bool enable_beacon;
/* cryptographic engine */
u64 usedkeys;
bool rx_software_decryption;
bool disable_offload;
/* filter settings */
u64 cur_mc_hash;
u32 cur_filter;
unsigned int filter_state;
bool sniffer_enabled;
/* PHY */
struct ieee80211_channel *channel;
int noise[4];
/* power calibration data */
u8 power_5G_leg[4];
u8 power_2G_cck[4];
u8 power_2G_ofdm[4];
u8 power_5G_ht20[8];
u8 power_5G_ht40[8];
u8 power_2G_ht20[8];
u8 power_2G_ht40[8];
u8 phy_heavy_clip;
#ifdef CONFIG_AR9170_LEDS
struct delayed_work led_work;
struct ar9170_led leds[AR9170_NUM_LEDS];
#endif /* CONFIG_AR9170_LEDS */
/* qos queue settings */
spinlock_t tx_stats_lock;
struct ar9170_tx_queue_stats tx_stats[5];
struct ieee80211_tx_queue_params edcf[5];
spinlock_t cmdlock;
__le32 cmdbuf[PAYLOAD_MAX + 1];
/* MAC statistics */
struct ieee80211_low_level_stats stats;
/* EEPROM */
struct ar9170_eeprom eeprom;
/* tx queues - as seen by hw - */
struct sk_buff_head tx_pending[__AR9170_NUM_TXQ];
struct sk_buff_head tx_status[__AR9170_NUM_TXQ];
struct delayed_work tx_janitor;
/* rxstream mpdu merge */
struct ar9170_rxstream_mpdu_merge rx_mpdu;
struct sk_buff *rx_failover;
int rx_failover_missing;
/* (cached) HW A-MPDU settings */
u8 global_ampdu_density;
u8 global_ampdu_factor;
};
struct ar9170_tx_info {
unsigned long timeout;
};
#define IS_STARTED(a) (((struct ar9170 *)a)->state >= AR9170_STARTED)
#define IS_ACCEPTING_CMD(a) (((struct ar9170 *)a)->state >= AR9170_IDLE)
/* exported interface */
void *ar9170_alloc(size_t priv_size);
int ar9170_register(struct ar9170 *ar, struct device *pdev);
void ar9170_rx(struct ar9170 *ar, struct sk_buff *skb);
void ar9170_unregister(struct ar9170 *ar);
void ar9170_tx_callback(struct ar9170 *ar, struct sk_buff *skb);
void ar9170_handle_command_response(struct ar9170 *ar, void *buf, u32 len);
int ar9170_nag_limiter(struct ar9170 *ar);
/* MAC */
void ar9170_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
int ar9170_init_mac(struct ar9170 *ar);
int ar9170_set_qos(struct ar9170 *ar);
int ar9170_update_multicast(struct ar9170 *ar, const u64 mc_hast);
int ar9170_update_frame_filter(struct ar9170 *ar, const u32 filter);
int ar9170_set_operating_mode(struct ar9170 *ar);
int ar9170_set_beacon_timers(struct ar9170 *ar);
int ar9170_set_dyn_sifs_ack(struct ar9170 *ar);
int ar9170_set_slot_time(struct ar9170 *ar);
int ar9170_set_basic_rates(struct ar9170 *ar);
int ar9170_set_hwretry_limit(struct ar9170 *ar, u32 max_retry);
int ar9170_update_beacon(struct ar9170 *ar);
void ar9170_new_beacon(struct work_struct *work);
int ar9170_upload_key(struct ar9170 *ar, u8 id, const u8 *mac, u8 ktype,
u8 keyidx, u8 *keydata, int keylen);
int ar9170_disable_key(struct ar9170 *ar, u8 id);
/* LEDs */
#ifdef CONFIG_AR9170_LEDS
int ar9170_register_leds(struct ar9170 *ar);
void ar9170_unregister_leds(struct ar9170 *ar);
#endif /* CONFIG_AR9170_LEDS */
int ar9170_init_leds(struct ar9170 *ar);
int ar9170_set_leds_state(struct ar9170 *ar, u32 led_state);
/* PHY / RF */
int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band);
int ar9170_init_rf(struct ar9170 *ar);
int ar9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
enum ar9170_rf_init_mode rfi, enum ar9170_bw bw);
#endif /* __AR9170_H */

127
drivers/net/wireless/ath/ar9170/cmd.c
View File

@ -1,127 +0,0 @@
/*
* Atheros AR9170 driver
*
* Basic HW register/memory/command access functions
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "ar9170.h"
#include "cmd.h"
int ar9170_write_mem(struct ar9170 *ar, const __le32 *data, size_t len)
{
int err;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return 0;
err = ar->exec_cmd(ar, AR9170_CMD_WMEM, len, (u8 *) data, 0, NULL);
if (err)
wiphy_debug(ar->hw->wiphy, "writing memory failed\n");
return err;
}
int ar9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val)
{
const __le32 buf[2] = {
cpu_to_le32(reg),
cpu_to_le32(val),
};
int err;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return 0;
err = ar->exec_cmd(ar, AR9170_CMD_WREG, sizeof(buf),
(u8 *) buf, 0, NULL);
if (err)
wiphy_debug(ar->hw->wiphy, "writing reg %#x (val %#x) failed\n",
reg, val);
return err;
}
int ar9170_read_mreg(struct ar9170 *ar, int nregs, const u32 *regs, u32 *out)
{
int i, err;
__le32 *offs, *res;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return 0;
/* abuse "out" for the register offsets, must be same length */
offs = (__le32 *)out;
for (i = 0; i < nregs; i++)
offs[i] = cpu_to_le32(regs[i]);
/* also use the same buffer for the input */
res = (__le32 *)out;
err = ar->exec_cmd(ar, AR9170_CMD_RREG,
4 * nregs, (u8 *)offs,
4 * nregs, (u8 *)res);
if (err)
return err;
/* convert result to cpu endian */
for (i = 0; i < nregs; i++)
out[i] = le32_to_cpu(res[i]);
return 0;
}
int ar9170_read_reg(struct ar9170 *ar, u32 reg, u32 *val)
{
return ar9170_read_mreg(ar, 1, &reg, val);
}
int ar9170_echo_test(struct ar9170 *ar, u32 v)
{
__le32 echobuf = cpu_to_le32(v);
__le32 echores;
int err;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return -ENODEV;
err = ar->exec_cmd(ar, AR9170_CMD_ECHO,
4, (u8 *)&echobuf,
4, (u8 *)&echores);
if (err)
return err;
if (echobuf != echores)
return -EINVAL;
return 0;
}

92
drivers/net/wireless/ath/ar9170/cmd.h
View File

@ -1,92 +0,0 @@
/*
* Atheros AR9170 driver
*
* Basic HW register/memory/command access functions
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __CMD_H
#define __CMD_H
#include "ar9170.h"
/* basic HW access */
int ar9170_write_mem(struct ar9170 *ar, const __le32 *data, size_t len);
int ar9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val);
int ar9170_read_reg(struct ar9170 *ar, u32 reg, u32 *val);
int ar9170_read_mreg(struct ar9170 *ar, int nregs, const u32 *regs, u32 *out);
int ar9170_echo_test(struct ar9170 *ar, u32 v);
/*
* Macros to facilitate writing multiple registers in a single
* write-combining USB command. Note that when the first group
* fails the whole thing will fail without any others attempted,
* but you won't know which write in the group failed.
*/
#define ar9170_regwrite_begin(ar) \
do { \
int __nreg = 0, __err = 0; \
struct ar9170 *__ar = ar;
#define ar9170_regwrite(r, v) do { \
__ar->cmdbuf[2 * __nreg + 1] = cpu_to_le32(r); \
__ar->cmdbuf[2 * __nreg + 2] = cpu_to_le32(v); \
__nreg++; \
if ((__nreg >= PAYLOAD_MAX/2)) { \
if (IS_ACCEPTING_CMD(__ar)) \
__err = ar->exec_cmd(__ar, AR9170_CMD_WREG, \
8 * __nreg, \
(u8 *) &__ar->cmdbuf[1], \
0, NULL); \
__nreg = 0; \
if (__err) \
goto __regwrite_out; \
} \
} while (0)
#define ar9170_regwrite_finish() \
__regwrite_out : \
if (__nreg) { \
if (IS_ACCEPTING_CMD(__ar)) \
__err = ar->exec_cmd(__ar, AR9170_CMD_WREG, \
8 * __nreg, \
(u8 *) &__ar->cmdbuf[1], \
0, NULL); \
__nreg = 0; \
}
#define ar9170_regwrite_result() \
__err; \
} while (0);
#endif /* __CMD_H */

179
drivers/net/wireless/ath/ar9170/eeprom.h
View File

@ -1,179 +0,0 @@
/*
* Atheros AR9170 driver
*
* EEPROM layout
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR9170_EEPROM_H
#define __AR9170_EEPROM_H
#define AR5416_MAX_CHAINS 2
#define AR5416_MODAL_SPURS 5
struct ar9170_eeprom_modal {
__le32 antCtrlChain[AR5416_MAX_CHAINS];
__le32 antCtrlCommon;
s8 antennaGainCh[AR5416_MAX_CHAINS];
u8 switchSettling;
u8 txRxAttenCh[AR5416_MAX_CHAINS];
u8 rxTxMarginCh[AR5416_MAX_CHAINS];
s8 adcDesiredSize;
s8 pgaDesiredSize;
u8 xlnaGainCh[AR5416_MAX_CHAINS];
u8 txEndToXpaOff;
u8 txEndToRxOn;
u8 txFrameToXpaOn;
u8 thresh62;
s8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
u8 xpdGain;
u8 xpd;
s8 iqCalICh[AR5416_MAX_CHAINS];
s8 iqCalQCh[AR5416_MAX_CHAINS];
u8 pdGainOverlap;
u8 ob;
u8 db;
u8 xpaBiasLvl;
u8 pwrDecreaseFor2Chain;
u8 pwrDecreaseFor3Chain;
u8 txFrameToDataStart;
u8 txFrameToPaOn;
u8 ht40PowerIncForPdadc;
u8 bswAtten[AR5416_MAX_CHAINS];
u8 bswMargin[AR5416_MAX_CHAINS];
u8 swSettleHt40;
u8 reserved[22];
struct spur_channel {
__le16 spurChan;
u8 spurRangeLow;
u8 spurRangeHigh;
} __packed spur_channels[AR5416_MODAL_SPURS];
} __packed;
#define AR5416_NUM_PD_GAINS 4
#define AR5416_PD_GAIN_ICEPTS 5
struct ar9170_calibration_data_per_freq {
u8 pwr_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
u8 vpd_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
} __packed;
#define AR5416_NUM_5G_CAL_PIERS 8
#define AR5416_NUM_2G_CAL_PIERS 4
#define AR5416_NUM_5G_TARGET_PWRS 8
#define AR5416_NUM_2G_CCK_TARGET_PWRS 3
#define AR5416_NUM_2G_OFDM_TARGET_PWRS 4
#define AR5416_MAX_NUM_TGT_PWRS 8
struct ar9170_calibration_target_power_legacy {
u8 freq;
u8 power[4];
} __packed;
struct ar9170_calibration_target_power_ht {
u8 freq;
u8 power[8];
} __packed;
#define AR5416_NUM_CTLS 24
struct ar9170_calctl_edges {
u8 channel;
#define AR9170_CALCTL_EDGE_FLAGS 0xC0
u8 power_flags;
} __packed;
#define AR5416_NUM_BAND_EDGES 8
struct ar9170_calctl_data {
struct ar9170_calctl_edges
control_edges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
} __packed;
struct ar9170_eeprom {
__le16 length;
__le16 checksum;
__le16 version;
u8 operating_flags;
#define AR9170_OPFLAG_5GHZ 1
#define AR9170_OPFLAG_2GHZ 2
u8 misc;
__le16 reg_domain[2];
u8 mac_address[6];
u8 rx_mask;
u8 tx_mask;
__le16 rf_silent;
__le16 bluetooth_options;
__le16 device_capabilities;
__le32 build_number;
u8 deviceType;
u8 reserved[33];
u8 customer_data[64];
struct ar9170_eeprom_modal
modal_header[2];
u8 cal_freq_pier_5G[AR5416_NUM_5G_CAL_PIERS];
u8 cal_freq_pier_2G[AR5416_NUM_2G_CAL_PIERS];
struct ar9170_calibration_data_per_freq
cal_pier_data_5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS],
cal_pier_data_2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
/* power calibration data */
struct ar9170_calibration_target_power_legacy
cal_tgt_pwr_5G[AR5416_NUM_5G_TARGET_PWRS];
struct ar9170_calibration_target_power_ht
cal_tgt_pwr_5G_ht20[AR5416_NUM_5G_TARGET_PWRS],
cal_tgt_pwr_5G_ht40[AR5416_NUM_5G_TARGET_PWRS];
struct ar9170_calibration_target_power_legacy
cal_tgt_pwr_2G_cck[AR5416_NUM_2G_CCK_TARGET_PWRS],
cal_tgt_pwr_2G_ofdm[AR5416_NUM_2G_OFDM_TARGET_PWRS];
struct ar9170_calibration_target_power_ht
cal_tgt_pwr_2G_ht20[AR5416_NUM_2G_OFDM_TARGET_PWRS],
cal_tgt_pwr_2G_ht40[AR5416_NUM_2G_OFDM_TARGET_PWRS];
/* conformance testing limits */
u8 ctl_index[AR5416_NUM_CTLS];
struct ar9170_calctl_data
ctl_data[AR5416_NUM_CTLS];
u8 pad;
__le16 subsystem_id;
} __packed;
#endif /* __AR9170_EEPROM_H */

430
drivers/net/wireless/ath/ar9170/hw.h
View File

@ -1,430 +0,0 @@
/*
* Atheros AR9170 driver
*
* Hardware-specific definitions
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR9170_HW_H
#define __AR9170_HW_H
#define AR9170_MAX_CMD_LEN 64
enum ar9170_cmd {
AR9170_CMD_RREG = 0x00,
AR9170_CMD_WREG = 0x01,
AR9170_CMD_RMEM = 0x02,
AR9170_CMD_WMEM = 0x03,
AR9170_CMD_BITAND = 0x04,
AR9170_CMD_BITOR = 0x05,
AR9170_CMD_EKEY = 0x28,
AR9170_CMD_DKEY = 0x29,
AR9170_CMD_FREQUENCY = 0x30,
AR9170_CMD_RF_INIT = 0x31,
AR9170_CMD_SYNTH = 0x32,
AR9170_CMD_FREQ_START = 0x33,
AR9170_CMD_ECHO = 0x80,
AR9170_CMD_TALLY = 0x81,
AR9170_CMD_TALLY_APD = 0x82,
AR9170_CMD_CONFIG = 0x83,
AR9170_CMD_RESET = 0x90,
AR9170_CMD_DKRESET = 0x91,
AR9170_CMD_DKTX_STATUS = 0x92,
AR9170_CMD_FDC = 0xA0,
AR9170_CMD_WREEPROM = 0xB0,
AR9170_CMD_WFLASH = 0xB0,
AR9170_CMD_FLASH_ERASE = 0xB1,
AR9170_CMD_FLASH_PROG = 0xB2,
AR9170_CMD_FLASH_CHKSUM = 0xB3,
AR9170_CMD_FLASH_READ = 0xB4,
AR9170_CMD_FW_DL_INIT = 0xB5,
AR9170_CMD_MEM_WREEPROM = 0xBB,
};
/* endpoints */
#define AR9170_EP_TX 1
#define AR9170_EP_RX 2
#define AR9170_EP_IRQ 3
#define AR9170_EP_CMD 4
#define AR9170_EEPROM_START 0x1600
#define AR9170_GPIO_REG_BASE 0x1d0100
#define AR9170_GPIO_REG_PORT_TYPE AR9170_GPIO_REG_BASE
#define AR9170_GPIO_REG_DATA (AR9170_GPIO_REG_BASE + 4)
#define AR9170_NUM_LEDS 2
#define AR9170_USB_REG_BASE 0x1e1000
#define AR9170_USB_REG_DMA_CTL (AR9170_USB_REG_BASE + 0x108)
#define AR9170_DMA_CTL_ENABLE_TO_DEVICE 0x1
#define AR9170_DMA_CTL_ENABLE_FROM_DEVICE 0x2
#define AR9170_DMA_CTL_HIGH_SPEED 0x4
#define AR9170_DMA_CTL_PACKET_MODE 0x8
#define AR9170_USB_REG_MAX_AGG_UPLOAD (AR9170_USB_REG_BASE + 0x110)
#define AR9170_USB_REG_UPLOAD_TIME_CTL (AR9170_USB_REG_BASE + 0x114)
#define AR9170_MAC_REG_BASE 0x1c3000
#define AR9170_MAC_REG_TSF_L (AR9170_MAC_REG_BASE + 0x514)
#define AR9170_MAC_REG_TSF_H (AR9170_MAC_REG_BASE + 0x518)
#define AR9170_MAC_REG_ATIM_WINDOW (AR9170_MAC_REG_BASE + 0x51C)
#define AR9170_MAC_REG_BCN_PERIOD (AR9170_MAC_REG_BASE + 0x520)
#define AR9170_MAC_REG_PRETBTT (AR9170_MAC_REG_BASE + 0x524)
#define AR9170_MAC_REG_MAC_ADDR_L (AR9170_MAC_REG_BASE + 0x610)
#define AR9170_MAC_REG_MAC_ADDR_H (AR9170_MAC_REG_BASE + 0x614)
#define AR9170_MAC_REG_BSSID_L (AR9170_MAC_REG_BASE + 0x618)
#define AR9170_MAC_REG_BSSID_H (AR9170_MAC_REG_BASE + 0x61c)
#define AR9170_MAC_REG_GROUP_HASH_TBL_L (AR9170_MAC_REG_BASE + 0x624)
#define AR9170_MAC_REG_GROUP_HASH_TBL_H (AR9170_MAC_REG_BASE + 0x628)
#define AR9170_MAC_REG_RX_TIMEOUT (AR9170_MAC_REG_BASE + 0x62C)
#define AR9170_MAC_REG_BASIC_RATE (AR9170_MAC_REG_BASE + 0x630)
#define AR9170_MAC_REG_MANDATORY_RATE (AR9170_MAC_REG_BASE + 0x634)
#define AR9170_MAC_REG_RTS_CTS_RATE (AR9170_MAC_REG_BASE + 0x638)
#define AR9170_MAC_REG_BACKOFF_PROTECT (AR9170_MAC_REG_BASE + 0x63c)
#define AR9170_MAC_REG_RX_THRESHOLD (AR9170_MAC_REG_BASE + 0x640)
#define AR9170_MAC_REG_RX_PE_DELAY (AR9170_MAC_REG_BASE + 0x64C)
#define AR9170_MAC_REG_DYNAMIC_SIFS_ACK (AR9170_MAC_REG_BASE + 0x658)
#define AR9170_MAC_REG_SNIFFER (AR9170_MAC_REG_BASE + 0x674)
#define AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC BIT(0)
#define AR9170_MAC_REG_SNIFFER_DEFAULTS 0x02000000
#define AR9170_MAC_REG_ENCRYPTION (AR9170_MAC_REG_BASE + 0x678)
#define AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE BIT(3)
#define AR9170_MAC_REG_ENCRYPTION_DEFAULTS 0x70
#define AR9170_MAC_REG_MISC_680 (AR9170_MAC_REG_BASE + 0x680)
#define AR9170_MAC_REG_TX_UNDERRUN (AR9170_MAC_REG_BASE + 0x688)
#define AR9170_MAC_REG_FRAMETYPE_FILTER (AR9170_MAC_REG_BASE + 0x68c)
#define AR9170_MAC_REG_FTF_ASSOC_REQ BIT(0)
#define AR9170_MAC_REG_FTF_ASSOC_RESP BIT(1)
#define AR9170_MAC_REG_FTF_REASSOC_REQ BIT(2)
#define AR9170_MAC_REG_FTF_REASSOC_RESP BIT(3)
#define AR9170_MAC_REG_FTF_PRB_REQ BIT(4)
#define AR9170_MAC_REG_FTF_PRB_RESP BIT(5)
#define AR9170_MAC_REG_FTF_BIT6 BIT(6)
#define AR9170_MAC_REG_FTF_BIT7 BIT(7)
#define AR9170_MAC_REG_FTF_BEACON BIT(8)
#define AR9170_MAC_REG_FTF_ATIM BIT(9)
#define AR9170_MAC_REG_FTF_DEASSOC BIT(10)
#define AR9170_MAC_REG_FTF_AUTH BIT(11)
#define AR9170_MAC_REG_FTF_DEAUTH BIT(12)
#define AR9170_MAC_REG_FTF_BIT13 BIT(13)
#define AR9170_MAC_REG_FTF_BIT14 BIT(14)
#define AR9170_MAC_REG_FTF_BIT15 BIT(15)
#define AR9170_MAC_REG_FTF_BAR BIT(24)
#define AR9170_MAC_REG_FTF_BA BIT(25)
#define AR9170_MAC_REG_FTF_PSPOLL BIT(26)
#define AR9170_MAC_REG_FTF_RTS BIT(27)
#define AR9170_MAC_REG_FTF_CTS BIT(28)
#define AR9170_MAC_REG_FTF_ACK BIT(29)
#define AR9170_MAC_REG_FTF_CFE BIT(30)
#define AR9170_MAC_REG_FTF_CFE_ACK BIT(31)
#define AR9170_MAC_REG_FTF_DEFAULTS 0x0700ffff
#define AR9170_MAC_REG_FTF_MONITOR 0xfd00ffff
#define AR9170_MAC_REG_RX_TOTAL (AR9170_MAC_REG_BASE + 0x6A0)
#define AR9170_MAC_REG_RX_CRC32 (AR9170_MAC_REG_BASE + 0x6A4)
#define AR9170_MAC_REG_RX_CRC16 (AR9170_MAC_REG_BASE + 0x6A8)
#define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI (AR9170_MAC_REG_BASE + 0x6AC)
#define AR9170_MAC_REG_RX_OVERRUN (AR9170_MAC_REG_BASE + 0x6B0)
#define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL (AR9170_MAC_REG_BASE + 0x6BC)
#define AR9170_MAC_REG_TX_RETRY (AR9170_MAC_REG_BASE + 0x6CC)
#define AR9170_MAC_REG_TX_TOTAL (AR9170_MAC_REG_BASE + 0x6F4)
#define AR9170_MAC_REG_ACK_EXTENSION (AR9170_MAC_REG_BASE + 0x690)
#define AR9170_MAC_REG_EIFS_AND_SIFS (AR9170_MAC_REG_BASE + 0x698)
#define AR9170_MAC_REG_SLOT_TIME (AR9170_MAC_REG_BASE + 0x6F0)
#define AR9170_MAC_REG_POWERMANAGEMENT (AR9170_MAC_REG_BASE + 0x700)
#define AR9170_MAC_REG_POWERMGT_IBSS 0xe0
#define AR9170_MAC_REG_POWERMGT_AP 0xa1
#define AR9170_MAC_REG_POWERMGT_STA 0x2
#define AR9170_MAC_REG_POWERMGT_AP_WDS 0x3
#define AR9170_MAC_REG_POWERMGT_DEFAULTS (0xf << 24)
#define AR9170_MAC_REG_ROLL_CALL_TBL_L (AR9170_MAC_REG_BASE + 0x704)
#define AR9170_MAC_REG_ROLL_CALL_TBL_H (AR9170_MAC_REG_BASE + 0x708)
#define AR9170_MAC_REG_AC0_CW (AR9170_MAC_REG_BASE + 0xB00)
#define AR9170_MAC_REG_AC1_CW (AR9170_MAC_REG_BASE + 0xB04)
#define AR9170_MAC_REG_AC2_CW (AR9170_MAC_REG_BASE + 0xB08)
#define AR9170_MAC_REG_AC3_CW (AR9170_MAC_REG_BASE + 0xB0C)
#define AR9170_MAC_REG_AC4_CW (AR9170_MAC_REG_BASE + 0xB10)
#define AR9170_MAC_REG_AC1_AC0_AIFS (AR9170_MAC_REG_BASE + 0xB14)
#define AR9170_MAC_REG_AC3_AC2_AIFS (AR9170_MAC_REG_BASE + 0xB18)
#define AR9170_MAC_REG_RETRY_MAX (AR9170_MAC_REG_BASE + 0xB28)
#define AR9170_MAC_REG_FCS_SELECT (AR9170_MAC_REG_BASE + 0xBB0)
#define AR9170_MAC_FCS_SWFCS 0x1
#define AR9170_MAC_FCS_FIFO_PROT 0x4
#define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND (AR9170_MAC_REG_BASE + 0xB30)
#define AR9170_MAC_REG_AC1_AC0_TXOP (AR9170_MAC_REG_BASE + 0xB44)
#define AR9170_MAC_REG_AC3_AC2_TXOP (AR9170_MAC_REG_BASE + 0xB48)
#define AR9170_MAC_REG_AMPDU_FACTOR (AR9170_MAC_REG_BASE + 0xB9C)
#define AR9170_MAC_REG_AMPDU_DENSITY (AR9170_MAC_REG_BASE + 0xBA0)
#define AR9170_MAC_REG_ACK_TABLE (AR9170_MAC_REG_BASE + 0xC00)
#define AR9170_MAC_REG_AMPDU_RX_THRESH (AR9170_MAC_REG_BASE + 0xC50)
#define AR9170_MAC_REG_TXRX_MPI (AR9170_MAC_REG_BASE + 0xD7C)
#define AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f
#define AR9170_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0
#define AR9170_MAC_TXRX_MPI_RX_MPI_MASK 0x000f0000
#define AR9170_MAC_TXRX_MPI_RX_TO_MASK 0xfff00000
#define AR9170_MAC_REG_BCN_ADDR (AR9170_MAC_REG_BASE + 0xD84)
#define AR9170_MAC_REG_BCN_LENGTH (AR9170_MAC_REG_BASE + 0xD88)
#define AR9170_MAC_REG_BCN_PLCP (AR9170_MAC_REG_BASE + 0xD90)
#define AR9170_MAC_REG_BCN_CTRL (AR9170_MAC_REG_BASE + 0xD94)
#define AR9170_MAC_REG_BCN_HT1 (AR9170_MAC_REG_BASE + 0xDA0)
#define AR9170_MAC_REG_BCN_HT2 (AR9170_MAC_REG_BASE + 0xDA4)
#define AR9170_PWR_REG_BASE 0x1D4000
#define AR9170_PWR_REG_CLOCK_SEL (AR9170_PWR_REG_BASE + 0x008)
#define AR9170_PWR_CLK_AHB_40MHZ 0
#define AR9170_PWR_CLK_AHB_20_22MHZ 1
#define AR9170_PWR_CLK_AHB_40_44MHZ 2
#define AR9170_PWR_CLK_AHB_80_88MHZ 3
#define AR9170_PWR_CLK_DAC_160_INV_DLY 0x70
/* put beacon here in memory */
#define AR9170_BEACON_BUFFER_ADDRESS 0x117900
struct ar9170_tx_control {
__le16 length;
__le16 mac_control;
__le32 phy_control;
u8 frame_data[0];
} __packed;
/* these are either-or */
#define AR9170_TX_MAC_PROT_RTS 0x0001
#define AR9170_TX_MAC_PROT_CTS 0x0002
#define AR9170_TX_MAC_NO_ACK 0x0004
/* if unset, MAC will only do SIFS space before frame */
#define AR9170_TX_MAC_BACKOFF 0x0008
#define AR9170_TX_MAC_BURST 0x0010
#define AR9170_TX_MAC_AGGR 0x0020
/* encryption is a two-bit field */
#define AR9170_TX_MAC_ENCR_NONE 0x0000
#define AR9170_TX_MAC_ENCR_RC4 0x0040
#define AR9170_TX_MAC_ENCR_CENC 0x0080
#define AR9170_TX_MAC_ENCR_AES 0x00c0
#define AR9170_TX_MAC_MMIC 0x0100
#define AR9170_TX_MAC_HW_DURATION 0x0200
#define AR9170_TX_MAC_QOS_SHIFT 10
#define AR9170_TX_MAC_QOS_MASK (3 << AR9170_TX_MAC_QOS_SHIFT)
#define AR9170_TX_MAC_AGGR_QOS_BIT1 0x0400
#define AR9170_TX_MAC_AGGR_QOS_BIT2 0x0800
#define AR9170_TX_MAC_DISABLE_TXOP 0x1000
#define AR9170_TX_MAC_TXOP_RIFS 0x2000
#define AR9170_TX_MAC_IMM_AMPDU 0x4000
#define AR9170_TX_MAC_RATE_PROBE 0x8000
/* either-or */
#define AR9170_TX_PHY_MOD_MASK 0x00000003
#define AR9170_TX_PHY_MOD_CCK 0x00000000
#define AR9170_TX_PHY_MOD_OFDM 0x00000001
#define AR9170_TX_PHY_MOD_HT 0x00000002
/* depends on modulation */
#define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004
#define AR9170_TX_PHY_GREENFIELD 0x00000004
#define AR9170_TX_PHY_BW_SHIFT 3
#define AR9170_TX_PHY_BW_MASK (3 << AR9170_TX_PHY_BW_SHIFT)
#define AR9170_TX_PHY_BW_20MHZ 0
#define AR9170_TX_PHY_BW_40MHZ 2
#define AR9170_TX_PHY_BW_40MHZ_DUP 3
#define AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT 6
#define AR9170_TX_PHY_TX_HEAVY_CLIP_MASK (7 << AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT)
#define AR9170_TX_PHY_TX_PWR_SHIFT 9
#define AR9170_TX_PHY_TX_PWR_MASK (0x3f << AR9170_TX_PHY_TX_PWR_SHIFT)
/* not part of the hw-spec */
#define AR9170_TX_PHY_QOS_SHIFT 25
#define AR9170_TX_PHY_QOS_MASK (3 << AR9170_TX_PHY_QOS_SHIFT)
#define AR9170_TX_PHY_TXCHAIN_SHIFT 15
#define AR9170_TX_PHY_TXCHAIN_MASK (7 << AR9170_TX_PHY_TXCHAIN_SHIFT)
#define AR9170_TX_PHY_TXCHAIN_1 1
/* use for cck, ofdm 6/9/12/18/24 and HT if capable */
#define AR9170_TX_PHY_TXCHAIN_2 5
#define AR9170_TX_PHY_MCS_SHIFT 18
#define AR9170_TX_PHY_MCS_MASK (0x7f << AR9170_TX_PHY_MCS_SHIFT)
#define AR9170_TX_PHY_SHORT_GI 0x80000000
#define AR5416_MAX_RATE_POWER 63
struct ar9170_rx_head {
u8 plcp[12];
} __packed;
struct ar9170_rx_phystatus {
union {
struct {
u8 rssi_ant0, rssi_ant1, rssi_ant2,
rssi_ant0x, rssi_ant1x, rssi_ant2x,
rssi_combined;
} __packed;
u8 rssi[7];
} __packed;
u8 evm_stream0[6], evm_stream1[6];
u8 phy_err;
} __packed;
struct ar9170_rx_macstatus {
u8 SAidx, DAidx;
u8 error;
u8 status;
} __packed;
#define AR9170_ENC_ALG_NONE 0x0
#define AR9170_ENC_ALG_WEP64 0x1
#define AR9170_ENC_ALG_TKIP 0x2
#define AR9170_ENC_ALG_AESCCMP 0x4
#define AR9170_ENC_ALG_WEP128 0x5
#define AR9170_ENC_ALG_WEP256 0x6
#define AR9170_ENC_ALG_CENC 0x7
#define AR9170_RX_ENC_SOFTWARE 0x8
static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
{
return (t->SAidx & 0xc0) >> 4 |
(t->DAidx & 0xc0) >> 6;
}
#define AR9170_RX_STATUS_MODULATION_MASK 0x03
#define AR9170_RX_STATUS_MODULATION_CCK 0x00
#define AR9170_RX_STATUS_MODULATION_OFDM 0x01
#define AR9170_RX_STATUS_MODULATION_HT 0x02
#define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03
/* depends on modulation */
#define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08
#define AR9170_RX_STATUS_GREENFIELD 0x08
#define AR9170_RX_STATUS_MPDU_MASK 0x30
#define AR9170_RX_STATUS_MPDU_SINGLE 0x00
#define AR9170_RX_STATUS_MPDU_FIRST 0x20
#define AR9170_RX_STATUS_MPDU_MIDDLE 0x30
#define AR9170_RX_STATUS_MPDU_LAST 0x10
#define AR9170_RX_ERROR_RXTO 0x01
#define AR9170_RX_ERROR_OVERRUN 0x02
#define AR9170_RX_ERROR_DECRYPT 0x04
#define AR9170_RX_ERROR_FCS 0x08
#define AR9170_RX_ERROR_WRONG_RA 0x10
#define AR9170_RX_ERROR_PLCP 0x20
#define AR9170_RX_ERROR_MMIC 0x40
#define AR9170_RX_ERROR_FATAL 0x80
struct ar9170_cmd_tx_status {
u8 dst[ETH_ALEN];
__le32 rate;
__le16 status;
} __packed;
#define AR9170_TX_STATUS_COMPLETE 0x00
#define AR9170_TX_STATUS_RETRY 0x01
#define AR9170_TX_STATUS_FAILED 0x02
struct ar9170_cmd_ba_failed_count {
__le16 failed;
__le16 rate;
} __packed;
struct ar9170_cmd_response {
u8 flag;
u8 type;
__le16 padding;
union {
struct ar9170_cmd_tx_status tx_status;
struct ar9170_cmd_ba_failed_count ba_fail_cnt;
u8 data[0];
};
} __packed;
/* QoS */
/* mac80211 queue to HW/FW map */
static const u8 ar9170_qos_hwmap[4] = { 3, 2, 0, 1 };
/* HW/FW queue to mac80211 map */
static const u8 ar9170_qos_mac80211map[4] = { 2, 3, 1, 0 };
enum ar9170_txq {
AR9170_TXQ_BE,
AR9170_TXQ_BK,
AR9170_TXQ_VI,
AR9170_TXQ_VO,
__AR9170_NUM_TXQ,
};
#define AR9170_TXQ_DEPTH 32
#define AR9170_TX_MAX_PENDING 128
#define AR9170_RX_STREAM_MAX_SIZE 65535
#endif /* __AR9170_HW_H */

181
drivers/net/wireless/ath/ar9170/led.c
View File

@ -1,181 +0,0 @@
/*
* Atheros AR9170 driver
*
* LED handling
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "ar9170.h"
#include "cmd.h"
int ar9170_set_leds_state(struct ar9170 *ar, u32 led_state)
{
return ar9170_write_reg(ar, AR9170_GPIO_REG_DATA, led_state);
}
int ar9170_init_leds(struct ar9170 *ar)
{
int err;
/* disable LEDs */
/* GPIO [0/1 mode: output, 2/3: input] */
err = ar9170_write_reg(ar, AR9170_GPIO_REG_PORT_TYPE, 3);
if (err)
goto out;
/* GPIO 0/1 value: off */
err = ar9170_set_leds_state(ar, 0);
out:
return err;
}
#ifdef CONFIG_AR9170_LEDS
static void ar9170_update_leds(struct work_struct *work)
{
struct ar9170 *ar = container_of(work, struct ar9170, led_work.work);
int i, tmp, blink_delay = 1000;
u32 led_val = 0;
bool rerun = false;
if (unlikely(!IS_ACCEPTING_CMD(ar)))
return ;
mutex_lock(&ar->mutex);
for (i = 0; i < AR9170_NUM_LEDS; i++)
if (ar->leds[i].registered && ar->leds[i].toggled) {
led_val |= 1 << i;
tmp = 70 + 200 / (ar->leds[i].toggled);
if (tmp < blink_delay)
blink_delay = tmp;
if (ar->leds[i].toggled > 1)
ar->leds[i].toggled = 0;
rerun = true;
}
ar9170_set_leds_state(ar, led_val);
mutex_unlock(&ar->mutex);
if (!rerun)
return;
ieee80211_queue_delayed_work(ar->hw,
&ar->led_work,
msecs_to_jiffies(blink_delay));
}
static void ar9170_led_brightness_set(struct led_classdev *led,
enum led_brightness brightness)
{
struct ar9170_led *arl = container_of(led, struct ar9170_led, l);
struct ar9170 *ar = arl->ar;
if (unlikely(!arl->registered))
return ;
if (arl->last_state != !!brightness) {
arl->toggled++;
arl->last_state = !!brightness;
}
if (likely(IS_ACCEPTING_CMD(ar) && arl->toggled))
ieee80211_queue_delayed_work(ar->hw, &ar->led_work, HZ/10);
}
static int ar9170_register_led(struct ar9170 *ar, int i, char *name,
char *trigger)
{
int err;
snprintf(ar->leds[i].name, sizeof(ar->leds[i].name),
"ar9170-%s::%s", wiphy_name(ar->hw->wiphy), name);
ar->leds[i].ar = ar;
ar->leds[i].l.name = ar->leds[i].name;
ar->leds[i].l.brightness_set = ar9170_led_brightness_set;
ar->leds[i].l.brightness = 0;
ar->leds[i].l.default_trigger = trigger;
err = led_classdev_register(wiphy_dev(ar->hw->wiphy),
&ar->leds[i].l);
if (err)
wiphy_err(ar->hw->wiphy, "failed to register %s LED (%d).\n",
ar->leds[i].name, err);
else
ar->leds[i].registered = true;
return err;
}
void ar9170_unregister_leds(struct ar9170 *ar)
{
int i;
for (i = 0; i < AR9170_NUM_LEDS; i++)
if (ar->leds[i].registered) {
led_classdev_unregister(&ar->leds[i].l);
ar->leds[i].registered = false;
ar->leds[i].toggled = 0;
}
cancel_delayed_work_sync(&ar->led_work);
}
int ar9170_register_leds(struct ar9170 *ar)
{
int err;
INIT_DELAYED_WORK(&ar->led_work, ar9170_update_leds);
err = ar9170_register_led(ar, 0, "tx",
ieee80211_get_tx_led_name(ar->hw));
if (err)
goto fail;
err = ar9170_register_led(ar, 1, "assoc",
ieee80211_get_assoc_led_name(ar->hw));
if (err)
goto fail;
return 0;
fail:
ar9170_unregister_leds(ar);
return err;
}
#endif /* CONFIG_AR9170_LEDS */

519
drivers/net/wireless/ath/ar9170/mac.c
View File

@ -1,519 +0,0 @@
/*
* Atheros AR9170 driver
*
* MAC programming
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <asm/unaligned.h>
#include "ar9170.h"
#include "cmd.h"
int ar9170_set_dyn_sifs_ack(struct ar9170 *ar)
{
u32 val;
if (conf_is_ht40(&ar->hw->conf))
val = 0x010a;
else {
if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ)
val = 0x105;
else
val = 0x104;
}
return ar9170_write_reg(ar, AR9170_MAC_REG_DYNAMIC_SIFS_ACK, val);
}
int ar9170_set_slot_time(struct ar9170 *ar)
{
u32 slottime = 20;
if (!ar->vif)
return 0;
if ((ar->hw->conf.channel->band == IEEE80211_BAND_5GHZ) ||
ar->vif->bss_conf.use_short_slot)
slottime = 9;
return ar9170_write_reg(ar, AR9170_MAC_REG_SLOT_TIME, slottime << 10);
}
int ar9170_set_basic_rates(struct ar9170 *ar)
{
u8 cck, ofdm;
if (!ar->vif)
return 0;
ofdm = ar->vif->bss_conf.basic_rates >> 4;
/* FIXME: is still necessary? */
if (ar->hw->conf.channel->band == IEEE80211_BAND_5GHZ)
cck = 0;
else
cck = ar->vif->bss_conf.basic_rates & 0xf;
return ar9170_write_reg(ar, AR9170_MAC_REG_BASIC_RATE,
ofdm << 8 | cck);
}
int ar9170_set_qos(struct ar9170 *ar)
{
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_AC0_CW, ar->edcf[0].cw_min |
(ar->edcf[0].cw_max << 16));
ar9170_regwrite(AR9170_MAC_REG_AC1_CW, ar->edcf[1].cw_min |
(ar->edcf[1].cw_max << 16));
ar9170_regwrite(AR9170_MAC_REG_AC2_CW, ar->edcf[2].cw_min |
(ar->edcf[2].cw_max << 16));
ar9170_regwrite(AR9170_MAC_REG_AC3_CW, ar->edcf[3].cw_min |
(ar->edcf[3].cw_max << 16));
ar9170_regwrite(AR9170_MAC_REG_AC4_CW, ar->edcf[4].cw_min |
(ar->edcf[4].cw_max << 16));
ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_AIFS,
((ar->edcf[0].aifs * 9 + 10)) |
((ar->edcf[1].aifs * 9 + 10) << 12) |
((ar->edcf[2].aifs * 9 + 10) << 24));
ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_AIFS,
((ar->edcf[2].aifs * 9 + 10) >> 8) |
((ar->edcf[3].aifs * 9 + 10) << 4) |
((ar->edcf[4].aifs * 9 + 10) << 16));
ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_TXOP,
ar->edcf[0].txop | ar->edcf[1].txop << 16);
ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_TXOP,
ar->edcf[2].txop | ar->edcf[3].txop << 16);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
static int ar9170_set_ampdu_density(struct ar9170 *ar, u8 mpdudensity)
{
u32 val;
/* don't allow AMPDU density > 8us */
if (mpdudensity > 6)
return -EINVAL;
/* Watch out! Otus uses slightly different density values. */
val = 0x140a00 | (mpdudensity ? (mpdudensity + 1) : 0);
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_AMPDU_DENSITY, val);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
int ar9170_init_mac(struct ar9170 *ar)
{
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_ACK_EXTENSION, 0x40);
ar9170_regwrite(AR9170_MAC_REG_RETRY_MAX, 0);
/* enable MMIC */
ar9170_regwrite(AR9170_MAC_REG_SNIFFER,
AR9170_MAC_REG_SNIFFER_DEFAULTS);
ar9170_regwrite(AR9170_MAC_REG_RX_THRESHOLD, 0xc1f80);
ar9170_regwrite(AR9170_MAC_REG_RX_PE_DELAY, 0x70);
ar9170_regwrite(AR9170_MAC_REG_EIFS_AND_SIFS, 0xa144000);
ar9170_regwrite(AR9170_MAC_REG_SLOT_TIME, 9 << 10);
/* CF-END mode */
ar9170_regwrite(0x1c3b2c, 0x19000000);
/* NAV protects ACK only (in TXOP) */
ar9170_regwrite(0x1c3b38, 0x201);
/* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
/* OTUS set AM to 0x1 */
ar9170_regwrite(AR9170_MAC_REG_BCN_HT1, 0x8000170);
ar9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT, 0x105);
/* AGG test code*/
/* Aggregation MAX number and timeout */
ar9170_regwrite(0x1c3b9c, 0x10000a);
ar9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
AR9170_MAC_REG_FTF_DEFAULTS);
/* Enable deaggregator, response in sniffer mode */
ar9170_regwrite(0x1c3c40, 0x1 | 1<<30);
/* rate sets */
ar9170_regwrite(AR9170_MAC_REG_BASIC_RATE, 0x150f);
ar9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, 0x150f);
ar9170_regwrite(AR9170_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
/* MIMO response control */
ar9170_regwrite(0x1c3694, 0x4003C1E);/* bit 26~28 otus-AM */
/* switch MAC to OTUS interface */
ar9170_regwrite(0x1c3600, 0x3);
ar9170_regwrite(AR9170_MAC_REG_AMPDU_RX_THRESH, 0xffff);
/* set PHY register read timeout (??) */
ar9170_regwrite(AR9170_MAC_REG_MISC_680, 0xf00008);
/* Disable Rx TimeOut, workaround for BB. */
ar9170_regwrite(AR9170_MAC_REG_RX_TIMEOUT, 0x0);
/* Set CPU clock frequency to 88/80MHz */
ar9170_regwrite(AR9170_PWR_REG_CLOCK_SEL,
AR9170_PWR_CLK_AHB_80_88MHZ |
AR9170_PWR_CLK_DAC_160_INV_DLY);
/* Set WLAN DMA interrupt mode: generate int per packet */
ar9170_regwrite(AR9170_MAC_REG_TXRX_MPI, 0x110011);
ar9170_regwrite(AR9170_MAC_REG_FCS_SELECT,
AR9170_MAC_FCS_FIFO_PROT);
/* Disables the CF_END frame, undocumented register */
ar9170_regwrite(AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND,
0x141E0F48);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
static int ar9170_set_mac_reg(struct ar9170 *ar, const u32 reg, const u8 *mac)
{
static const u8 zero[ETH_ALEN] = { 0 };
if (!mac)
mac = zero;
ar9170_regwrite_begin(ar);
ar9170_regwrite(reg, get_unaligned_le32(mac));
ar9170_regwrite(reg + 4, get_unaligned_le16(mac + 4));
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
int ar9170_update_multicast(struct ar9170 *ar, const u64 mc_hash)
{
int err;
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, mc_hash >> 32);
ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, mc_hash);
ar9170_regwrite_finish();
err = ar9170_regwrite_result();
if (err)
return err;
ar->cur_mc_hash = mc_hash;
return 0;
}
int ar9170_update_frame_filter(struct ar9170 *ar, const u32 filter)
{
int err;
err = ar9170_write_reg(ar, AR9170_MAC_REG_FRAMETYPE_FILTER, filter);
if (err)
return err;
ar->cur_filter = filter;
return 0;
}
static int ar9170_set_promiscouous(struct ar9170 *ar)
{
u32 encr_mode, sniffer;
int err;
err = ar9170_read_reg(ar, AR9170_MAC_REG_SNIFFER, &sniffer);
if (err)
return err;
err = ar9170_read_reg(ar, AR9170_MAC_REG_ENCRYPTION, &encr_mode);
if (err)
return err;
if (ar->sniffer_enabled) {
sniffer |= AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC;
/*
* Rx decryption works in place.
*
* If we don't disable it, the hardware will render all
* encrypted frames which are encrypted with an unknown
* key useless.
*/
encr_mode |= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
ar->sniffer_enabled = true;
} else {
sniffer &= ~AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC;
if (ar->rx_software_decryption)
encr_mode |= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
else
encr_mode &= ~AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
}
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_ENCRYPTION, encr_mode);
ar9170_regwrite(AR9170_MAC_REG_SNIFFER, sniffer);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
int ar9170_set_operating_mode(struct ar9170 *ar)
{
struct ath_common *common = &ar->common;
u32 pm_mode = AR9170_MAC_REG_POWERMGT_DEFAULTS;
u8 *mac_addr, *bssid;
int err;
if (ar->vif) {
mac_addr = common->macaddr;
bssid = common->curbssid;
switch (ar->vif->type) {
case NL80211_IFTYPE_MESH_POINT:
case NL80211_IFTYPE_ADHOC:
pm_mode |= AR9170_MAC_REG_POWERMGT_IBSS;
break;
case NL80211_IFTYPE_AP:
pm_mode |= AR9170_MAC_REG_POWERMGT_AP;
break;
case NL80211_IFTYPE_WDS:
pm_mode |= AR9170_MAC_REG_POWERMGT_AP_WDS;
break;
case NL80211_IFTYPE_MONITOR:
ar->sniffer_enabled = true;
ar->rx_software_decryption = true;
break;
default:
pm_mode |= AR9170_MAC_REG_POWERMGT_STA;
break;
}
} else {
mac_addr = NULL;
bssid = NULL;
}
err = ar9170_set_mac_reg(ar, AR9170_MAC_REG_MAC_ADDR_L, mac_addr);
if (err)
return err;
err = ar9170_set_mac_reg(ar, AR9170_MAC_REG_BSSID_L, bssid);
if (err)
return err;
err = ar9170_set_promiscouous(ar);
if (err)
return err;
/* set AMPDU density to 8us. */
err = ar9170_set_ampdu_density(ar, 6);
if (err)
return err;
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_POWERMANAGEMENT, pm_mode);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
int ar9170_set_hwretry_limit(struct ar9170 *ar, unsigned int max_retry)
{
u32 tmp = min_t(u32, 0x33333, max_retry * 0x11111);
return ar9170_write_reg(ar, AR9170_MAC_REG_RETRY_MAX, tmp);
}
int ar9170_set_beacon_timers(struct ar9170 *ar)
{
u32 v = 0;
u32 pretbtt = 0;
if (ar->vif) {
v |= ar->vif->bss_conf.beacon_int;
if (ar->enable_beacon) {
switch (ar->vif->type) {
case NL80211_IFTYPE_MESH_POINT:
case NL80211_IFTYPE_ADHOC:
v |= BIT(25);
break;
case NL80211_IFTYPE_AP:
v |= BIT(24);
pretbtt = (ar->vif->bss_conf.beacon_int - 6) <<
16;
break;
default:
break;
}
}
v |= ar->vif->bss_conf.dtim_period << 16;
}
ar9170_regwrite_begin(ar);
ar9170_regwrite(AR9170_MAC_REG_PRETBTT, pretbtt);
ar9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, v);
ar9170_regwrite_finish();
return ar9170_regwrite_result();
}
int ar9170_update_beacon(struct ar9170 *ar)
{
struct sk_buff *skb;
__le32 *data, *old = NULL;
u32 word;
int i;
skb = ieee80211_beacon_get(ar->hw, ar->vif);
if (!skb)
return -ENOMEM;
data = (__le32 *)skb->data;
if (ar->beacon)
old = (__le32 *)ar->beacon->data;
ar9170_regwrite_begin(ar);
for (i = 0; i < DIV_ROUND_UP(skb->len, 4); i++) {
/*
* XXX: This accesses beyond skb data for up
* to the last 3 bytes!!
*/
if (old && (data[i] == old[i]))
continue;
word = le32_to_cpu(data[i]);
ar9170_regwrite(AR9170_BEACON_BUFFER_ADDRESS + 4 * i, word);
}
/* XXX: use skb->cb info */
if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ)
ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP,
((skb->len + 4) << (3 + 16)) + 0x0400);
else
ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP,
((skb->len + 4) << 16) + 0x001b);
ar9170_regwrite(AR9170_MAC_REG_BCN_LENGTH, skb->len + 4);
ar9170_regwrite(AR9170_MAC_REG_BCN_ADDR, AR9170_BEACON_BUFFER_ADDRESS);
ar9170_regwrite(AR9170_MAC_REG_BCN_CTRL, 1);
ar9170_regwrite_finish();
dev_kfree_skb(ar->beacon);
ar->beacon = skb;
return ar9170_regwrite_result();
}
void ar9170_new_beacon(struct work_struct *work)
{
struct ar9170 *ar = container_of(work, struct ar9170,
beacon_work);
struct sk_buff *skb;
if (unlikely(!IS_STARTED(ar)))
return ;
mutex_lock(&ar->mutex);
if (!ar->vif)
goto out;
ar9170_update_beacon(ar);
rcu_read_lock();
while ((skb = ieee80211_get_buffered_bc(ar->hw, ar->vif)))
ar9170_op_tx(ar->hw, skb);
rcu_read_unlock();
out:
mutex_unlock(&ar->mutex);
}
int ar9170_upload_key(struct ar9170 *ar, u8 id, const u8 *mac, u8 ktype,
u8 keyidx, u8 *keydata, int keylen)
{
__le32 vals[7];
static const u8 bcast[ETH_ALEN] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
u8 dummy;
mac = mac ? : bcast;
vals[0] = cpu_to_le32((keyidx << 16) + id);
vals[1] = cpu_to_le32(mac[1] << 24 | mac[0] << 16 | ktype);
vals[2] = cpu_to_le32(mac[5] << 24 | mac[4] << 16 |
mac[3] << 8 | mac[2]);
memset(&vals[3], 0, 16);
if (keydata)
memcpy(&vals[3], keydata, keylen);
return ar->exec_cmd(ar, AR9170_CMD_EKEY,
sizeof(vals), (u8 *)vals,
1, &dummy);
}
int ar9170_disable_key(struct ar9170 *ar, u8 id)
{
__le32 val = cpu_to_le32(id);
u8 dummy;
return ar->exec_cmd(ar, AR9170_CMD_EKEY,
sizeof(val), (u8 *)&val,
1, &dummy);
}

2190
drivers/net/wireless/ath/ar9170/main.c
View File

File diff suppressed because it is too large Load Diff

1719
drivers/net/wireless/ath/ar9170/phy.c
View File

File diff suppressed because it is too large Load Diff

1008
drivers/net/wireless/ath/ar9170/usb.c
View File

File diff suppressed because it is too large Load Diff

82
drivers/net/wireless/ath/ar9170/usb.h
View File

@ -1,82 +0,0 @@
/*
* Atheros AR9170 USB driver
*
* Driver specific definitions
*
* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
* Copyright 2009, Christian Lamparter <chunkeey@web.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, see
* http://www.gnu.org/licenses/.
*
* This file incorporates work covered by the following copyright and
* permission notice:
* Copyright (c) 2007-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __USB_H
#define __USB_H
#include <linux/usb.h>
#include <linux/completion.h>
#include <linux/spinlock.h>
#include <linux/leds.h>
#include <net/cfg80211.h>
#include <net/mac80211.h>
#include <linux/firmware.h>
#include "eeprom.h"
#include "hw.h"
#include "ar9170.h"
#define AR9170_NUM_RX_URBS 16
#define AR9170_NUM_TX_URBS 8
struct firmware;
struct ar9170_usb {
struct ar9170 common;
struct usb_device *udev;
struct usb_interface *intf;
struct usb_anchor rx_submitted;
struct usb_anchor tx_pending;
struct usb_anchor tx_submitted;
bool req_one_stage_fw;
spinlock_t tx_urb_lock;
atomic_t tx_submitted_urbs;
unsigned int tx_pending_urbs;
struct completion cmd_wait;
struct completion firmware_loading_complete;
int readlen;
u8 *readbuf;
const struct firmware *init_values;
const struct firmware *firmware;
};
#endif /* __USB_H */

1
drivers/net/wireless/ath/ath.h
View File

@ -119,6 +119,7 @@ struct ath_ops {
void (*write)(void *, u32 val, u32 reg_offset);
void (*enable_write_buffer)(void *);
void (*write_flush) (void *);
u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
};
struct ath_common;

45
drivers/net/wireless/ath/ath9k/ar5008_phy.c
View File

@ -44,6 +44,34 @@ static const int m1ThreshExt_off = 127;
static const int m2ThreshExt_off = 127;
static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
int col)
{
int i;
for (i = 0; i < array->ia_rows; i++)
bank[i] = INI_RA(array, i, col);
}
#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
u32 *data, unsigned int *writecnt)
{
int r;
ENABLE_REGWRITE_BUFFER(ah);
for (r = 0; r < array->ia_rows; r++) {
REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
DO_DELAY(*writecnt);
}
REGWRITE_BUFFER_FLUSH(ah);
}
/**
* ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
* @rfbuf:
@ -530,16 +558,16 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
/* Setup Bank 0 Write */
RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
/* Setup Bank 1 Write */
RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
/* Setup Bank 2 Write */
RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
/* Setup Bank 6 Write */
RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
modesIndex);
{
int i;
@ -569,7 +597,7 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
}
/* Setup Bank 7 Setup */
RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
/* Write Analog registers */
REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
@ -729,6 +757,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
struct ath9k_channel *chan)
{
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ath_common *common = ath9k_hw_common(ah);
int i, regWrites = 0;
struct ieee80211_channel *channel = chan->chan;
u32 modesIndex, freqIndex;
@ -805,7 +834,8 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
REG_WRITE(ah, reg, val);
if (reg >= 0x7800 && reg < 0x78a0
&& ah->config.analog_shiftreg) {
&& ah->config.analog_shiftreg
&& (common->bus_ops->ath_bus_type != ATH_USB)) {
udelay(100);
}
@ -835,7 +865,8 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
REG_WRITE(ah, reg, val);
if (reg >= 0x7800 && reg < 0x78a0
&& ah->config.analog_shiftreg) {
&& ah->config.analog_shiftreg
&& (common->bus_ops->ath_bus_type != ATH_USB)) {
udelay(100);
}

43
drivers/net/wireless/ath/ath9k/ar9002_calib.c
View File

@ -26,6 +26,27 @@ enum ar9002_cal_types {
IQ_MISMATCH_CAL = BIT(2),
};
static bool ar9002_hw_is_cal_supported(struct ath_hw *ah,
struct ath9k_channel *chan,
enum ar9002_cal_types cal_type)
{
bool supported = false;
switch (ah->supp_cals & cal_type) {
case IQ_MISMATCH_CAL:
/* Run IQ Mismatch for non-CCK only */
if (!IS_CHAN_B(chan))
supported = true;
break;
case ADC_GAIN_CAL:
case ADC_DC_CAL:
/* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */
if (!IS_CHAN_B(chan) &&
!(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
supported = true;
break;
}
return supported;
}
static void ar9002_hw_setup_calibration(struct ath_hw *ah,
struct ath9k_cal_list *currCal)
@ -858,26 +879,32 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
ah->supp_cals = IQ_MISMATCH_CAL;
if (AR_SREV_9160_10_OR_LATER(ah) &&
!(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan))) {
if (AR_SREV_9160_10_OR_LATER(ah))
ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL;
if (AR_SREV_9287(ah))
ah->supp_cals &= ~ADC_GAIN_CAL;
if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) {
INIT_CAL(&ah->adcgain_caldata);
INSERT_CAL(ah, &ah->adcgain_caldata);
ath_dbg(common, ATH_DBG_CALIBRATE,
"enabling ADC Gain Calibration.\n");
"enabling ADC Gain Calibration.\n");
}
if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) {
INIT_CAL(&ah->adcdc_caldata);
INSERT_CAL(ah, &ah->adcdc_caldata);
ath_dbg(common, ATH_DBG_CALIBRATE,
"enabling ADC DC Calibration.\n");
"enabling ADC DC Calibration.\n");
}
INIT_CAL(&ah->iq_caldata);
INSERT_CAL(ah, &ah->iq_caldata);
ath_dbg(common, ATH_DBG_CALIBRATE,
"enabling IQ Calibration.\n");
if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) {
INIT_CAL(&ah->iq_caldata);
INSERT_CAL(ah, &ah->iq_caldata);
ath_dbg(common, ATH_DBG_CALIBRATE,
"enabling IQ Calibration.\n");
}
ah->cal_list_curr = ah->cal_list;

12
drivers/net/wireless/ath/ath9k/ar9002_mac.c
View File

@ -415,17 +415,6 @@ static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
}
static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
u32 vmf)
{
struct ar5416_desc *ads = AR5416DESC(ds);
if (vmf)
ads->ds_ctl0 |= AR_VirtMoreFrag;
else
ads->ds_ctl0 &= ~AR_VirtMoreFrag;
}
void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
u32 size, u32 flags)
{
@ -459,5 +448,4 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
}

98
drivers/net/wireless/ath/ath9k/ar9003_hw.c
View File

@ -66,8 +66,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
/* rx/tx gain */
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9485_common_rx_gain_1_1,
ARRAY_SIZE(ar9485_common_rx_gain_1_1), 2);
ar9485Common_wo_xlna_rx_gain_1_1,
ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9485_modes_lowest_ob_db_tx_gain_1_1,
ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
@ -88,66 +88,6 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9485_1_1_pcie_phy_clkreq_disable_L1,
ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
2);
} else if (AR_SREV_9485(ah)) {
/* mac */
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
ar9485_1_0_mac_core,
ARRAY_SIZE(ar9485_1_0_mac_core), 2);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
ar9485_1_0_mac_postamble,
ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
/* bb */
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
ARRAY_SIZE(ar9485_1_0), 2);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
ar9485_1_0_baseband_core,
ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
ar9485_1_0_baseband_postamble,
ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
/* radio */
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
ar9485_1_0_radio_core,
ARRAY_SIZE(ar9485_1_0_radio_core), 2);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
ar9485_1_0_radio_postamble,
ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
/* soc */
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
ar9485_1_0_soc_preamble,
ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
/* rx/tx gain */
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9485Common_rx_gain_1_0,
ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9485Modes_lowest_ob_db_tx_gain_1_0,
ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
5);
/* Load PCIE SERDES settings from INI */
/* Awake Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
2);
/* Sleep Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
2);
} else {
/* mac */
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@ -228,11 +168,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
ar9485_modes_lowest_ob_db_tx_gain_1_1,
ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
5);
else if (AR_SREV_9485(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9485Modes_lowest_ob_db_tx_gain_1_0,
ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
5);
else
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
@ -245,11 +180,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
ar9485Modes_high_ob_db_tx_gain_1_1,
ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
5);
else if (AR_SREV_9485(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9485Modes_high_ob_db_tx_gain_1_0,
ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_0),
5);
else
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9300Modes_high_ob_db_tx_gain_table_2p2,
@ -262,11 +192,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
ar9485Modes_low_ob_db_tx_gain_1_1,
ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
5);
else if (AR_SREV_9485(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9485Modes_low_ob_db_tx_gain_1_0,
ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_0),
5);
else
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9300Modes_low_ob_db_tx_gain_table_2p2,
@ -279,11 +204,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
ar9485Modes_high_power_tx_gain_1_1,
ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
5);
else if (AR_SREV_9485(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9485Modes_high_power_tx_gain_1_0,
ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_0),
5);
else
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9300Modes_high_power_tx_gain_table_2p2,
@ -300,13 +220,8 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
default:
if (AR_SREV_9485_11(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9485_common_rx_gain_1_1,
ARRAY_SIZE(ar9485_common_rx_gain_1_1),
2);
else if (AR_SREV_9485(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9485Common_rx_gain_1_0,
ARRAY_SIZE(ar9485Common_rx_gain_1_0),
ar9485Common_wo_xlna_rx_gain_1_1,
ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
2);
else
INIT_INI_ARRAY(&ah->iniModesRxGain,
@ -320,11 +235,6 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
ar9485Common_wo_xlna_rx_gain_1_1,
ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
2);
else if (AR_SREV_9485(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9485Common_wo_xlna_rx_gain_1_0,
ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_0),
2);
else
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9300Common_wo_xlna_rx_gain_table_2p2,

12
drivers/net/wireless/ath/ath9k/ar9003_mac.c
View File

@ -485,17 +485,6 @@ static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
}
static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
u32 vmf)
{
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
if (vmf)
ads->ctl11 |= AR_VirtMoreFrag;
else
ads->ctl11 &= ~AR_VirtMoreFrag;
}
void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains)
{
struct ar9003_txc *ads = ds;
@ -521,7 +510,6 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
}
void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)

925
drivers/net/wireless/ath/ath9k/ar9485_initvals.h
View File

@ -17,931 +17,6 @@
#ifndef INITVALS_9485_H
#define INITVALS_9485_H
static const u32 ar9485Common_1_0[][2] = {
/* Addr allmodes */
{0x00007010, 0x00000022},
{0x00007020, 0x00000000},
{0x00007034, 0x00000002},
{0x00007038, 0x000004c2},
};
static const u32 ar9485_1_0_mac_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
{0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
{0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
{0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
{0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
};
static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
/* Addr allmodes */
{0x00018c00, 0x10212e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000580c},
};
static const u32 ar9485Common_wo_xlna_rx_gain_1_0[][2] = {
/* Addr allmodes */
{0x0000a000, 0x00010000},
{0x0000a004, 0x00030002},
{0x0000a008, 0x00050004},
{0x0000a00c, 0x00810080},
{0x0000a010, 0x01800082},
{0x0000a014, 0x01820181},
{0x0000a018, 0x01840183},
{0x0000a01c, 0x01880185},
{0x0000a020, 0x018a0189},
{0x0000a024, 0x02850284},
{0x0000a028, 0x02890288},
{0x0000a02c, 0x03850384},
{0x0000a030, 0x03890388},
{0x0000a034, 0x038b038a},
{0x0000a038, 0x038d038c},
{0x0000a03c, 0x03910390},
{0x0000a040, 0x03930392},
{0x0000a044, 0x03950394},
{0x0000a048, 0x00000396},
{0x0000a04c, 0x00000000},
{0x0000a050, 0x00000000},
{0x0000a054, 0x00000000},
{0x0000a058, 0x00000000},
{0x0000a05c, 0x00000000},
{0x0000a060, 0x00000000},
{0x0000a064, 0x00000000},
{0x0000a068, 0x00000000},
{0x0000a06c, 0x00000000},
{0x0000a070, 0x00000000},
{0x0000a074, 0x00000000},
{0x0000a078, 0x00000000},
{0x0000a07c, 0x00000000},
{0x0000a080, 0x28282828},
{0x0000a084, 0x28282828},
{0x0000a088, 0x28282828},
{0x0000a08c, 0x28282828},
{0x0000a090, 0x28282828},
{0x0000a094, 0x21212128},
{0x0000a098, 0x171c1c1c},
{0x0000a09c, 0x02020212},
{0x0000a0a0, 0x00000202},
{0x0000a0a4, 0x00000000},
{0x0000a0a8, 0x00000000},
{0x0000a0ac, 0x00000000},
{0x0000a0b0, 0x00000000},
{0x0000a0b4, 0x00000000},
{0x0000a0b8, 0x00000000},
{0x0000a0bc, 0x00000000},
{0x0000a0c0, 0x001f0000},
{0x0000a0c4, 0x111f1100},
{0x0000a0c8, 0x111d111e},
{0x0000a0cc, 0x111b111c},
{0x0000a0d0, 0x22032204},
{0x0000a0d4, 0x22012202},
{0x0000a0d8, 0x221f2200},
{0x0000a0dc, 0x221d221e},
{0x0000a0e0, 0x33013302},
{0x0000a0e4, 0x331f3300},
{0x0000a0e8, 0x4402331e},
{0x0000a0ec, 0x44004401},
{0x0000a0f0, 0x441e441f},
{0x0000a0f4, 0x55015502},
{0x0000a0f8, 0x551f5500},
{0x0000a0fc, 0x6602551e},
{0x0000a100, 0x66006601},
{0x0000a104, 0x661e661f},
{0x0000a108, 0x7703661d},
{0x0000a10c, 0x77017702},
{0x0000a110, 0x00007700},
{0x0000a114, 0x00000000},
{0x0000a118, 0x00000000},
{0x0000a11c, 0x00000000},
{0x0000a120, 0x00000000},
{0x0000a124, 0x00000000},
{0x0000a128, 0x00000000},
{0x0000a12c, 0x00000000},
{0x0000a130, 0x00000000},
{0x0000a134, 0x00000000},
{0x0000a138, 0x00000000},
{0x0000a13c, 0x00000000},
{0x0000a140, 0x001f0000},
{0x0000a144, 0x111f1100},
{0x0000a148, 0x111d111e},
{0x0000a14c, 0x111b111c},
{0x0000a150, 0x22032204},
{0x0000a154, 0x22012202},
{0x0000a158, 0x221f2200},
{0x0000a15c, 0x221d221e},
{0x0000a160, 0x33013302},
{0x0000a164, 0x331f3300},
{0x0000a168, 0x4402331e},
{0x0000a16c, 0x44004401},
{0x0000a170, 0x441e441f},
{0x0000a174, 0x55015502},
{0x0000a178, 0x551f5500},
{0x0000a17c, 0x6602551e},
{0x0000a180, 0x66006601},
{0x0000a184, 0x661e661f},
{0x0000a188, 0x7703661d},
{0x0000a18c, 0x77017702},
{0x0000a190, 0x00007700},
{0x0000a194, 0x00000000},
{0x0000a198, 0x00000000},
{0x0000a19c, 0x00000000},
{0x0000a1a0, 0x00000000},
{0x0000a1a4, 0x00000000},
{0x0000a1a8, 0x00000000},
{0x0000a1ac, 0x00000000},
{0x0000a1b0, 0x00000000},
{0x0000a1b4, 0x00000000},
{0x0000a1b8, 0x00000000},
{0x0000a1bc, 0x00000000},
{0x0000a1c0, 0x00000000},
{0x0000a1c4, 0x00000000},
{0x0000a1c8, 0x00000000},
{0x0000a1cc, 0x00000000},
{0x0000a1d0, 0x00000000},
{0x0000a1d4, 0x00000000},
{0x0000a1d8, 0x00000000},
{0x0000a1dc, 0x00000000},
{0x0000a1e0, 0x00000000},
{0x0000a1e4, 0x00000000},
{0x0000a1e8, 0x00000000},
{0x0000a1ec, 0x00000000},
{0x0000a1f0, 0x00000396},
{0x0000a1f4, 0x00000396},
{0x0000a1f8, 0x00000396},
{0x0000a1fc, 0x00000296},
};
static const u32 ar9485Modes_high_power_tx_gain_1_0[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
{0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
{0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
{0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
{0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
{0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
{0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
{0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
{0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
{0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
{0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
{0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
{0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
{0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
{0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
{0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
{0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
{0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
{0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
{0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
{0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
{0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
{0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
{0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
{0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
{0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
{0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
{0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
};
static const u32 ar9485_1_0[][2] = {
/* Addr allmodes */
{0x0000a580, 0x00000000},
{0x0000a584, 0x00000000},
{0x0000a588, 0x00000000},
{0x0000a58c, 0x00000000},
{0x0000a590, 0x00000000},
{0x0000a594, 0x00000000},
{0x0000a598, 0x00000000},
{0x0000a59c, 0x00000000},
{0x0000a5a0, 0x00000000},
{0x0000a5a4, 0x00000000},
{0x0000a5a8, 0x00000000},
{0x0000a5ac, 0x00000000},
{0x0000a5b0, 0x00000000},
{0x0000a5b4, 0x00000000},
{0x0000a5b8, 0x00000000},
{0x0000a5bc, 0x00000000},
};
static const u32 ar9485_1_0_radio_core[][2] = {
/* Addr allmodes */
{0x00016000, 0x36db6db6},
{0x00016004, 0x6db6db40},
{0x00016008, 0x73800000},
{0x0001600c, 0x00000000},
{0x00016040, 0x7f80fff8},
{0x00016048, 0x6c92426e},
{0x0001604c, 0x000f0278},
{0x00016050, 0x6db6db6c},
{0x00016054, 0x6db60000},
{0x00016080, 0x00080000},
{0x00016084, 0x0e48048c},
{0x00016088, 0x14214514},
{0x0001608c, 0x119f081e},
{0x00016090, 0x24926490},
{0x00016098, 0xd28b3330},
{0x000160a0, 0xc2108ffe},
{0x000160a4, 0x812fc370},
{0x000160a8, 0x423c8000},
{0x000160b4, 0x92480040},
{0x000160c0, 0x006db6db},
{0x000160c4, 0x0186db60},
{0x000160c8, 0x6db6db6c},
{0x000160cc, 0x6de6fbe0},
{0x000160d0, 0xf7dfcf3c},
{0x00016100, 0x04cb0001},
{0x00016104, 0xfff80015},
{0x00016108, 0x00080010},
{0x00016144, 0x01884080},
{0x00016148, 0x00008040},
{0x00016180, 0x08453333},
{0x00016184, 0x18e82f01},
{0x00016188, 0x00000000},
{0x0001618c, 0x00000000},
{0x00016240, 0x08400000},
{0x00016244, 0x1bf90f00},
{0x00016248, 0x00000000},
{0x0001624c, 0x00000000},
{0x00016280, 0x01000015},
{0x00016284, 0x00d30000},
{0x00016288, 0x00318000},
{0x0001628c, 0x50000000},
{0x00016290, 0x4b96210f},
{0x00016380, 0x00000000},
{0x00016384, 0x00000000},
{0x00016388, 0x00800700},
{0x0001638c, 0x00800700},
{0x00016390, 0x00800700},
{0x00016394, 0x00000000},
{0x00016398, 0x00000000},
{0x0001639c, 0x00000000},
{0x000163a0, 0x00000001},
{0x000163a4, 0x00000001},
{0x000163a8, 0x00000000},
{0x000163ac, 0x00000000},
{0x000163b0, 0x00000000},
{0x000163b4, 0x00000000},
{0x000163b8, 0x00000000},
{0x000163bc, 0x00000000},
{0x000163c0, 0x000000a0},
{0x000163c4, 0x000c0000},
{0x000163c8, 0x14021402},
{0x000163cc, 0x00001402},
{0x000163d0, 0x00000000},
{0x000163d4, 0x00000000},
{0x00016c40, 0x1319c178},
{0x00016c44, 0x10000000},
};
static const u32 ar9485Modes_lowest_ob_db_tx_gain_1_0[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
{0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
{0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
{0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
{0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
{0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
{0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
{0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
{0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
{0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
{0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
{0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
{0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
{0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
{0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
{0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
{0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
{0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
{0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
{0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
{0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
{0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
{0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
{0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
{0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
{0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
{0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
{0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
};
static const u32 ar9485_1_0_baseband_core[][2] = {
/* Addr allmodes */
{0x00009800, 0xafe68e30},
{0x00009804, 0xfd14e000},
{0x00009808, 0x9c0a8f6b},
{0x0000980c, 0x04800000},
{0x00009814, 0x9280c00a},
{0x00009818, 0x00000000},
{0x0000981c, 0x00020028},
{0x00009834, 0x5f3ca3de},
{0x00009838, 0x0108ecff},
{0x0000983c, 0x14750600},
{0x00009880, 0x201fff00},
{0x00009884, 0x00001042},
{0x000098a4, 0x00200400},
{0x000098b0, 0x52440bbe},
{0x000098bc, 0x00000002},
{0x000098d0, 0x004b6a8e},
{0x000098d4, 0x00000820},
{0x000098dc, 0x00000000},
{0x000098f0, 0x00000000},
{0x000098f4, 0x00000000},
{0x00009c04, 0x00000000},
{0x00009c08, 0x03200000},
{0x00009c0c, 0x00000000},
{0x00009c10, 0x00000000},
{0x00009c14, 0x00046384},
{0x00009c18, 0x05b6b440},
{0x00009c1c, 0x00b6b440},
{0x00009d00, 0xc080a333},
{0x00009d04, 0x40206c10},
{0x00009d08, 0x009c4060},
{0x00009d0c, 0x1883800a},
{0x00009d10, 0x01834061},
{0x00009d14, 0x00c00400},
{0x00009d18, 0x00000000},
{0x00009d1c, 0x00000000},
{0x00009e08, 0x0038233c},
{0x00009e24, 0x990bb515},
{0x00009e28, 0x0a6f0000},
{0x00009e30, 0x06336f77},
{0x00009e34, 0x6af6532f},
{0x00009e38, 0x0cc80c00},
{0x00009e40, 0x0d261820},
{0x00009e4c, 0x00001004},
{0x00009e50, 0x00ff03f1},
{0x00009fc0, 0x80be4788},
{0x00009fc4, 0x0001efb5},
{0x00009fcc, 0x40000014},
{0x0000a20c, 0x00000000},
{0x0000a210, 0x00000000},
{0x0000a220, 0x00000000},
{0x0000a224, 0x00000000},
{0x0000a228, 0x10002310},
{0x0000a23c, 0x00000000},
{0x0000a244, 0x0c000000},
{0x0000a2a0, 0x00000001},
{0x0000a2c0, 0x00000001},
{0x0000a2c8, 0x00000000},
{0x0000a2cc, 0x18c43433},
{0x0000a2d4, 0x00000000},
{0x0000a2dc, 0x00000000},
{0x0000a2e0, 0x00000000},
{0x0000a2e4, 0x00000000},
{0x0000a2e8, 0x00000000},
{0x0000a2ec, 0x00000000},
{0x0000a2f0, 0x00000000},
{0x0000a2f4, 0x00000000},
{0x0000a2f8, 0x00000000},
{0x0000a344, 0x00000000},
{0x0000a34c, 0x00000000},
{0x0000a350, 0x0000a000},
{0x0000a364, 0x00000000},
{0x0000a370, 0x00000000},
{0x0000a390, 0x00000001},
{0x0000a394, 0x00000444},
{0x0000a398, 0x001f0e0f},
{0x0000a39c, 0x0075393f},
{0x0000a3a0, 0xb79f6427},
{0x0000a3a4, 0x00000000},
{0x0000a3a8, 0xaaaaaaaa},
{0x0000a3ac, 0x3c466478},
{0x0000a3c0, 0x20202020},
{0x0000a3c4, 0x22222220},
{0x0000a3c8, 0x20200020},
{0x0000a3cc, 0x20202020},
{0x0000a3d0, 0x20202020},
{0x0000a3d4, 0x20202020},
{0x0000a3d8, 0x20202020},
{0x0000a3dc, 0x20202020},
{0x0000a3e0, 0x20202020},
{0x0000a3e4, 0x20202020},
{0x0000a3e8, 0x20202020},
{0x0000a3ec, 0x20202020},
{0x0000a3f0, 0x00000000},
{0x0000a3f4, 0x00000006},
{0x0000a3f8, 0x0cdbd380},
{0x0000a3fc, 0x000f0f01},
{0x0000a400, 0x8fa91f01},
{0x0000a404, 0x00000000},
{0x0000a408, 0x0e79e5c6},
{0x0000a40c, 0x00820820},
{0x0000a414, 0x1ce739ce},
{0x0000a418, 0x2d0011ce},
{0x0000a41c, 0x1ce739ce},
{0x0000a420, 0x000001ce},
{0x0000a424, 0x1ce739ce},
{0x0000a428, 0x000001ce},
{0x0000a42c, 0x1ce739ce},
{0x0000a430, 0x1ce739ce},
{0x0000a434, 0x00000000},
{0x0000a438, 0x00001801},
{0x0000a43c, 0x00000000},
{0x0000a440, 0x00000000},
{0x0000a444, 0x00000000},
{0x0000a448, 0x04000000},
{0x0000a44c, 0x00000001},
{0x0000a450, 0x00010000},
{0x0000a458, 0x00000000},
{0x0000a5c4, 0x3fad9d74},
{0x0000a5c8, 0x0048060a},
{0x0000a5cc, 0x00000637},
{0x0000a760, 0x03020100},
{0x0000a764, 0x09080504},
{0x0000a768, 0x0d0c0b0a},
{0x0000a76c, 0x13121110},
{0x0000a770, 0x31301514},
{0x0000a774, 0x35343332},
{0x0000a778, 0x00000036},
{0x0000a780, 0x00000838},
{0x0000a7c0, 0x00000000},
{0x0000a7c4, 0xfffffffc},
{0x0000a7c8, 0x00000000},
{0x0000a7cc, 0x00000000},
{0x0000a7d0, 0x00000000},
{0x0000a7d4, 0x00000004},
{0x0000a7dc, 0x00000001},
};
static const u32 ar9485Modes_high_ob_db_tx_gain_1_0[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
{0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
{0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
{0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
{0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
{0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
{0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
{0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
{0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
{0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
{0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
{0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
{0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
{0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
{0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
{0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
{0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
{0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
{0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
{0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
{0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
{0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
{0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
{0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
{0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
{0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
{0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
{0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
};
static const u32 ar9485Common_rx_gain_1_0[][2] = {
/* Addr allmodes */
{0x0000a000, 0x00010000},
{0x0000a004, 0x00030002},
{0x0000a008, 0x00050004},
{0x0000a00c, 0x00810080},
{0x0000a010, 0x01800082},
{0x0000a014, 0x01820181},
{0x0000a018, 0x01840183},
{0x0000a01c, 0x01880185},
{0x0000a020, 0x018a0189},
{0x0000a024, 0x02850284},
{0x0000a028, 0x02890288},
{0x0000a02c, 0x03850384},
{0x0000a030, 0x03890388},
{0x0000a034, 0x038b038a},
{0x0000a038, 0x038d038c},
{0x0000a03c, 0x03910390},
{0x0000a040, 0x03930392},
{0x0000a044, 0x03950394},
{0x0000a048, 0x00000396},
{0x0000a04c, 0x00000000},
{0x0000a050, 0x00000000},
{0x0000a054, 0x00000000},
{0x0000a058, 0x00000000},
{0x0000a05c, 0x00000000},
{0x0000a060, 0x00000000},
{0x0000a064, 0x00000000},
{0x0000a068, 0x00000000},
{0x0000a06c, 0x00000000},
{0x0000a070, 0x00000000},
{0x0000a074, 0x00000000},
{0x0000a078, 0x00000000},
{0x0000a07c, 0x00000000},
{0x0000a080, 0x28282828},
{0x0000a084, 0x28282828},
{0x0000a088, 0x28282828},
{0x0000a08c, 0x28282828},
{0x0000a090, 0x28282828},
{0x0000a094, 0x21212128},
{0x0000a098, 0x171c1c1c},
{0x0000a09c, 0x02020212},
{0x0000a0a0, 0x00000202},
{0x0000a0a4, 0x00000000},
{0x0000a0a8, 0x00000000},
{0x0000a0ac, 0x00000000},
{0x0000a0b0, 0x00000000},
{0x0000a0b4, 0x00000000},
{0x0000a0b8, 0x00000000},
{0x0000a0bc, 0x00000000},
{0x0000a0c0, 0x001f0000},
{0x0000a0c4, 0x111f1100},
{0x0000a0c8, 0x111d111e},
{0x0000a0cc, 0x111b111c},
{0x0000a0d0, 0x22032204},
{0x0000a0d4, 0x22012202},
{0x0000a0d8, 0x221f2200},
{0x0000a0dc, 0x221d221e},
{0x0000a0e0, 0x33013302},
{0x0000a0e4, 0x331f3300},
{0x0000a0e8, 0x4402331e},
{0x0000a0ec, 0x44004401},
{0x0000a0f0, 0x441e441f},
{0x0000a0f4, 0x55015502},
{0x0000a0f8, 0x551f5500},
{0x0000a0fc, 0x6602551e},
{0x0000a100, 0x66006601},
{0x0000a104, 0x661e661f},
{0x0000a108, 0x7703661d},
{0x0000a10c, 0x77017702},
{0x0000a110, 0x00007700},
{0x0000a114, 0x00000000},
{0x0000a118, 0x00000000},
{0x0000a11c, 0x00000000},
{0x0000a120, 0x00000000},
{0x0000a124, 0x00000000},
{0x0000a128, 0x00000000},
{0x0000a12c, 0x00000000},
{0x0000a130, 0x00000000},
{0x0000a134, 0x00000000},
{0x0000a138, 0x00000000},
{0x0000a13c, 0x00000000},
{0x0000a140, 0x001f0000},
{0x0000a144, 0x111f1100},
{0x0000a148, 0x111d111e},
{0x0000a14c, 0x111b111c},
{0x0000a150, 0x22032204},
{0x0000a154, 0x22012202},
{0x0000a158, 0x221f2200},
{0x0000a15c, 0x221d221e},
{0x0000a160, 0x33013302},
{0x0000a164, 0x331f3300},
{0x0000a168, 0x4402331e},
{0x0000a16c, 0x44004401},
{0x0000a170, 0x441e441f},
{0x0000a174, 0x55015502},
{0x0000a178, 0x551f5500},
{0x0000a17c, 0x6602551e},
{0x0000a180, 0x66006601},
{0x0000a184, 0x661e661f},
{0x0000a188, 0x7703661d},
{0x0000a18c, 0x77017702},
{0x0000a190, 0x00007700},
{0x0000a194, 0x00000000},
{0x0000a198, 0x00000000},
{0x0000a19c, 0x00000000},
{0x0000a1a0, 0x00000000},
{0x0000a1a4, 0x00000000},
{0x0000a1a8, 0x00000000},
{0x0000a1ac, 0x00000000},
{0x0000a1b0, 0x00000000},
{0x0000a1b4, 0x00000000},
{0x0000a1b8, 0x00000000},
{0x0000a1bc, 0x00000000},
{0x0000a1c0, 0x00000000},
{0x0000a1c4, 0x00000000},
{0x0000a1c8, 0x00000000},
{0x0000a1cc, 0x00000000},
{0x0000a1d0, 0x00000000},
{0x0000a1d4, 0x00000000},
{0x0000a1d8, 0x00000000},
{0x0000a1dc, 0x00000000},
{0x0000a1e0, 0x00000000},
{0x0000a1e4, 0x00000000},
{0x0000a1e8, 0x00000000},
{0x0000a1ec, 0x00000000},
{0x0000a1f0, 0x00000396},
{0x0000a1f4, 0x00000396},
{0x0000a1f8, 0x00000396},
{0x0000a1fc, 0x00000296},
};
static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
/* Addr allmodes */
{0x00018c00, 0x10252e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000580c},
};
static const u32 ar9485_1_0_pcie_phy_clkreq_enable_L1[][2] = {
/* Addr allmodes */
{0x00018c00, 0x10253e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000580c},
};
static const u32 ar9485_1_0_soc_preamble[][2] = {
/* Addr allmodes */
{0x00004090, 0x00aa10aa},
{0x000040a4, 0x00a0c9c9},
{0x00007048, 0x00000004},
};
static const u32 ar9485_fast_clock_1_0_baseband_postamble[][3] = {
/* Addr 5G_HT20 5G_HT40 */
{0x00009e00, 0x03721821, 0x03721821},
{0x0000a230, 0x0000400b, 0x00004016},
{0x0000a254, 0x00000898, 0x00001130},
};
static const u32 ar9485_1_0_baseband_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
{0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
{0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
{0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
{0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
{0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
{0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
{0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
{0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
{0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
{0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e},
{0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
{0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
{0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
{0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
{0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
{0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
{0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
{0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
{0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0},
{0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
{0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
{0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff},
{0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
{0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
{0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
{0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
{0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
{0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
{0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
{0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
{0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0},
{0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
{0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
{0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
{0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
{0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
};
static const u32 ar9485Modes_low_ob_db_tx_gain_1_0[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
{0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
{0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
{0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
{0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
{0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
{0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
{0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
{0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
{0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
{0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
{0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
{0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
{0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
{0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
{0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
{0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
{0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
{0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
{0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
{0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
{0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
{0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
{0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
{0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
{0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
{0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
{0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
{0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
};
static const u32 ar9485_1_0_pcie_phy_clkreq_disable_L1[][2] = {
/* Addr allmodes */
{0x00018c00, 0x10213e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000580c},
};
static const u32 ar9485_1_0_radio_postamble[][2] = {
/* Addr allmodes */
{0x0001609c, 0x0b283f31},
{0x000160ac, 0x24611800},
{0x000160b0, 0x03284f3e},
{0x0001610c, 0x00170000},
{0x00016140, 0x10804008},
};
static const u32 ar9485_1_0_mac_core[][2] = {
/* Addr allmodes */
{0x00000008, 0x00000000},
{0x00000030, 0x00020085},
{0x00000034, 0x00000005},
{0x00000040, 0x00000000},
{0x00000044, 0x00000000},
{0x00000048, 0x00000008},
{0x0000004c, 0x00000010},
{0x00000050, 0x00000000},
{0x00001040, 0x002ffc0f},
{0x00001044, 0x002ffc0f},
{0x00001048, 0x002ffc0f},
{0x0000104c, 0x002ffc0f},
{0x00001050, 0x002ffc0f},
{0x00001054, 0x002ffc0f},
{0x00001058, 0x002ffc0f},
{0x0000105c, 0x002ffc0f},
{0x00001060, 0x002ffc0f},
{0x00001064, 0x002ffc0f},
{0x000010f0, 0x00000100},
{0x00001270, 0x00000000},
{0x000012b0, 0x00000000},
{0x000012f0, 0x00000000},
{0x0000143c, 0x00000000},
{0x0000147c, 0x00000000},
{0x00008000, 0x00000000},
{0x00008004, 0x00000000},
{0x00008008, 0x00000000},
{0x0000800c, 0x00000000},
{0x00008018, 0x00000000},
{0x00008020, 0x00000000},
{0x00008038, 0x00000000},
{0x0000803c, 0x00000000},
{0x00008040, 0x00000000},
{0x00008044, 0x00000000},
{0x00008048, 0x00000000},
{0x0000804c, 0xffffffff},
{0x00008054, 0x00000000},
{0x00008058, 0x00000000},
{0x0000805c, 0x000fc78f},
{0x00008060, 0x0000000f},
{0x00008064, 0x00000000},
{0x00008070, 0x00000310},
{0x00008074, 0x00000020},
{0x00008078, 0x00000000},
{0x0000809c, 0x0000000f},
{0x000080a0, 0x00000000},
{0x000080a4, 0x02ff0000},
{0x000080a8, 0x0e070605},
{0x000080ac, 0x0000000d},
{0x000080b0, 0x00000000},
{0x000080b4, 0x00000000},
{0x000080b8, 0x00000000},
{0x000080bc, 0x00000000},
{0x000080c0, 0x2a800000},
{0x000080c4, 0x06900168},
{0x000080c8, 0x13881c20},
{0x000080cc, 0x01f40000},
{0x000080d0, 0x00252500},
{0x000080d4, 0x00a00000},
{0x000080d8, 0x00400000},
{0x000080dc, 0x00000000},
{0x000080e0, 0xffffffff},
{0x000080e4, 0x0000ffff},
{0x000080e8, 0x3f3f3f3f},
{0x000080ec, 0x00000000},
{0x000080f0, 0x00000000},
{0x000080f4, 0x00000000},
{0x000080fc, 0x00020000},
{0x00008100, 0x00000000},
{0x00008108, 0x00000052},
{0x0000810c, 0x00000000},
{0x00008110, 0x00000000},
{0x00008114, 0x000007ff},
{0x00008118, 0x000000aa},
{0x0000811c, 0x00003210},
{0x00008124, 0x00000000},
{0x00008128, 0x00000000},
{0x0000812c, 0x00000000},
{0x00008130, 0x00000000},
{0x00008134, 0x00000000},
{0x00008138, 0x00000000},
{0x0000813c, 0x0000ffff},
{0x00008144, 0xffffffff},
{0x00008168, 0x00000000},
{0x0000816c, 0x00000000},
{0x00008170, 0x18486200},
{0x00008174, 0x33332210},
{0x00008178, 0x00000000},
{0x0000817c, 0x00020000},
{0x000081c0, 0x00000000},
{0x000081c4, 0x33332210},
{0x000081c8, 0x00000000},
{0x000081cc, 0x00000000},
{0x000081d4, 0x00000000},
{0x000081ec, 0x00000000},
{0x000081f0, 0x00000000},
{0x000081f4, 0x00000000},
{0x000081f8, 0x00000000},
{0x000081fc, 0x00000000},
{0x00008240, 0x00100000},
{0x00008244, 0x0010f400},
{0x00008248, 0x00000800},
{0x0000824c, 0x0001e800},
{0x00008250, 0x00000000},
{0x00008254, 0x00000000},
{0x00008258, 0x00000000},
{0x0000825c, 0x40000000},
{0x00008260, 0x00080922},
{0x00008264, 0x9ca00010},
{0x00008268, 0xffffffff},
{0x0000826c, 0x0000ffff},
{0x00008270, 0x00000000},
{0x00008274, 0x40000000},
{0x00008278, 0x003e4180},
{0x0000827c, 0x00000004},
{0x00008284, 0x0000002c},
{0x00008288, 0x0000002c},
{0x0000828c, 0x000000ff},
{0x00008294, 0x00000000},
{0x00008298, 0x00000000},
{0x0000829c, 0x00000000},
{0x00008300, 0x00000140},
{0x00008314, 0x00000000},
{0x0000831c, 0x0000010d},
{0x00008328, 0x00000000},
{0x0000832c, 0x00000007},
{0x00008330, 0x00000302},
{0x00008334, 0x00000700},
{0x00008338, 0x00ff0000},
{0x0000833c, 0x02400000},
{0x00008340, 0x000107ff},
{0x00008344, 0xa248105b},
{0x00008348, 0x008f0000},
{0x0000835c, 0x00000000},
{0x00008360, 0xffffffff},
{0x00008364, 0xffffffff},
{0x00008368, 0x00000000},
{0x00008370, 0x00000000},
{0x00008374, 0x000000ff},
{0x00008378, 0x00000000},
{0x0000837c, 0x00000000},
{0x00008380, 0xffffffff},
{0x00008384, 0xffffffff},
{0x00008390, 0xffffffff},
{0x00008394, 0xffffffff},
{0x00008398, 0x00000000},
{0x0000839c, 0x00000000},
{0x000083a0, 0x00000000},
{0x000083a4, 0x0000fa14},
{0x000083a8, 0x000f0c00},
{0x000083ac, 0x33332210},
{0x000083b0, 0x33332210},
{0x000083b4, 0x33332210},
{0x000083b8, 0x33332210},
{0x000083bc, 0x00000000},
{0x000083c0, 0x00000000},
{0x000083c4, 0x00000000},
{0x000083c8, 0x00000000},
{0x000083cc, 0x00000200},
{0x000083d0, 0x000301ff},
};
static const u32 ar9485_1_1_mac_core[][2] = {
/* Addr allmodes */
{0x00000008, 0x00000000},

14
drivers/net/wireless/ath/ath9k/ath9k.h
View File

@ -120,13 +120,11 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
/* RX / TX */
/***********/
#define ATH_MAX_ANTENNA 3
#define ATH_RXBUF 512
#define ATH_TXBUF 512
#define ATH_TXBUF_RESERVE 5
#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
#define ATH_TXMAXTRY 13
#define ATH_MGT_TXMAXTRY 4
#define TID_TO_WME_AC(_tid) \
((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
@ -346,11 +344,9 @@ void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid
struct ath_vif {
int av_bslot;
bool is_bslot_active;
bool is_bslot_active, primary_sta_vif;
__le64 tsf_adjust; /* TSF adjustment for staggered beacons */
enum nl80211_iftype av_opmode;
struct ath_buf *av_bcbuf;
u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
};
/*******************/
@ -362,7 +358,7 @@ struct ath_vif {
* number of BSSIDs) if a given beacon does not go out even after waiting this
* number of beacon intervals, the game's up.
*/
#define BSTUCK_THRESH (9 * ATH_BCBUF)
#define BSTUCK_THRESH 9
#define ATH_BCBUF 4
#define ATH_DEFAULT_BINTVAL 100 /* TU */
#define ATH_DEFAULT_BMISS_LIMIT 10
@ -386,7 +382,7 @@ struct ath_beacon {
u32 beaconq;
u32 bmisscnt;
u32 ast_be_xmit;
u64 bc_tstamp;
u32 bc_tstamp;
struct ieee80211_vif *bslot[ATH_BCBUF];
int slottime;
int slotupdate;
@ -401,6 +397,7 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
int ath_beaconq_config(struct ath_softc *sc);
void ath_set_beacon(struct ath_softc *sc);
void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
/*******/
@ -550,6 +547,7 @@ struct ath_ant_comb {
#define SC_OP_BT_SCAN BIT(13)
#define SC_OP_ANI_RUN BIT(14)
#define SC_OP_ENABLE_APM BIT(15)
#define SC_OP_PRIM_STA_VIF BIT(16)
/* Powersave flags */
#define PS_WAIT_FOR_BEACON BIT(0)
@ -688,8 +686,6 @@ void ath9k_ps_restore(struct ath_softc *sc);
u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
void ath_start_rfkill_poll(struct ath_softc *sc);
extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
void ath9k_calculate_iter_data(struct ieee80211_hw *hw,

205
drivers/net/wireless/ath/ath9k/beacon.c
View File

@ -57,8 +57,8 @@ int ath_beaconq_config(struct ath_softc *sc)
/*
* Associates the beacon frame buffer with a transmit descriptor. Will set
* up all required antenna switch parameters, rate codes, and channel flags.
* Beacons are always sent out at the lowest rate, and are not retried.
* up rate codes, and channel flags. Beacons are always sent out at the
* lowest rate, and are not retried.
*/
static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
struct ath_buf *bf, int rateidx)
@ -68,7 +68,7 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
struct ath_common *common = ath9k_hw_common(ah);
struct ath_desc *ds;
struct ath9k_11n_rate_series series[4];
int flags, antenna, ctsrate = 0, ctsduration = 0;
int flags, ctsrate = 0, ctsduration = 0;
struct ieee80211_supported_band *sband;
u8 rate = 0;
@ -76,12 +76,6 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
flags = ATH9K_TXDESC_NOACK;
ds->ds_link = 0;
/*
* Switch antenna every beacon.
* Should only switch every beacon period, not for every SWBA
* XXX assumes two antennae
*/
antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1);
sband = &sc->sbands[common->hw->conf.channel->band];
rate = sband->bitrates[rateidx].hw_value;
@ -278,7 +272,7 @@ int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif)
return -ENOMEM;
tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
sc->beacon.bc_tstamp = le64_to_cpu(tstamp);
sc->beacon.bc_tstamp = (u32) le64_to_cpu(tstamp);
/* Calculate a TSF adjustment factor required for staggered beacons. */
if (avp->av_bslot > 0) {
u64 tsfadjust;
@ -294,8 +288,8 @@ int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif)
* adjustment. Other slots are adjusted to get the timestamp
* close to the TBTT for the BSS.
*/
tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
tsfadjust = TU_TO_USEC(intval * avp->av_bslot) / ATH_BCBUF;
avp->tsf_adjust = cpu_to_le64(tsfadjust);
ath_dbg(common, ATH_DBG_BEACON,
"stagger beacons, bslot %d intval %u tsfadjust %llu\n",
@ -329,6 +323,7 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp)
if (avp->av_bslot != -1) {
sc->beacon.bslot[avp->av_bslot] = NULL;
sc->nbcnvifs--;
avp->av_bslot = -1;
}
bf = avp->av_bcbuf;
@ -369,12 +364,13 @@ void ath_beacon_tasklet(unsigned long data)
if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0) {
sc->beacon.bmisscnt++;
if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
if (sc->beacon.bmisscnt < BSTUCK_THRESH * sc->nbcnvifs) {
ath_dbg(common, ATH_DBG_BSTUCK,
"missed %u consecutive beacons\n",
sc->beacon.bmisscnt);
ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
ath9k_hw_bstuck_nfcal(ah);
if (sc->beacon.bmisscnt > 3)
ath9k_hw_bstuck_nfcal(ah);
} else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
ath_dbg(common, ATH_DBG_BSTUCK,
"beacon is officially stuck\n");
@ -385,13 +381,6 @@ void ath_beacon_tasklet(unsigned long data)
return;
}
if (sc->beacon.bmisscnt != 0) {
ath_dbg(common, ATH_DBG_BSTUCK,
"resume beacon xmit after %u misses\n",
sc->beacon.bmisscnt);
sc->beacon.bmisscnt = 0;
}
/*
* Generate beacon frames. we are sending frames
* staggered so calculate the slot for this frame based
@ -401,21 +390,14 @@ void ath_beacon_tasklet(unsigned long data)
intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
tsf = ath9k_hw_gettsf64(ah);
tsftu = TSF_TO_TU(tsf>>32, tsf);
slot = ((tsftu % intval) * ATH_BCBUF) / intval;
/*
* Reverse the slot order to get slot 0 on the TBTT offset that does
* not require TSF adjustment and other slots adding
* slot/ATH_BCBUF * beacon_int to timestamp. For example, with
* ATH_BCBUF = 4, we process beacon slots as follows: 3 2 1 0 3 2 1 ..
* and slot 0 is at correct offset to TBTT.
*/
slot = ATH_BCBUF - slot - 1;
tsf += TU_TO_USEC(ah->config.sw_beacon_response_time);
tsftu = TSF_TO_TU((tsf * ATH_BCBUF) >>32, tsf * ATH_BCBUF);
slot = (tsftu % (intval * ATH_BCBUF)) / intval;
vif = sc->beacon.bslot[slot];
ath_dbg(common, ATH_DBG_BEACON,
"slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
slot, tsf, tsftu, intval, vif);
slot, tsf, tsftu / ATH_BCBUF, intval, vif);
bfaddr = 0;
if (vif) {
@ -424,6 +406,13 @@ void ath_beacon_tasklet(unsigned long data)
bfaddr = bf->bf_daddr;
bc = 1;
}
if (sc->beacon.bmisscnt != 0) {
ath_dbg(common, ATH_DBG_BSTUCK,
"resume beacon xmit after %u misses\n",
sc->beacon.bmisscnt);
sc->beacon.bmisscnt = 0;
}
}
/*
@ -463,13 +452,17 @@ static void ath9k_beacon_init(struct ath_softc *sc,
u32 next_beacon,
u32 beacon_period)
{
if (beacon_period & ATH9K_BEACON_RESET_TSF)
if (sc->sc_flags & SC_OP_TSF_RESET) {
ath9k_ps_wakeup(sc);
ath9k_hw_reset_tsf(sc->sc_ah);
}
ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period);
if (beacon_period & ATH9K_BEACON_RESET_TSF)
if (sc->sc_flags & SC_OP_TSF_RESET) {
ath9k_ps_restore(sc);
sc->sc_flags &= ~SC_OP_TSF_RESET;
}
}
/*
@ -484,18 +477,14 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
u32 nexttbtt, intval;
/* NB: the beacon interval is kept internally in TU's */
intval = conf->beacon_interval & ATH9K_BEACON_PERIOD;
intval = TU_TO_USEC(conf->beacon_interval & ATH9K_BEACON_PERIOD);
intval /= ATH_BCBUF; /* for staggered beacons */
nexttbtt = intval;
if (sc->sc_flags & SC_OP_TSF_RESET)
intval |= ATH9K_BEACON_RESET_TSF;
/*
* In AP mode we enable the beacon timers and SWBA interrupts to
* prepare beacon frames.
*/
intval |= ATH9K_BEACON_ENA;
ah->imask |= ATH9K_INT_SWBA;
ath_beaconq_config(sc);
@ -505,11 +494,6 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
ath9k_beacon_init(sc, nexttbtt, intval);
sc->beacon.bmisscnt = 0;
ath9k_hw_set_interrupts(ah, ah->imask);
/* Clear the reset TSF flag, so that subsequent beacon updation
will not reset the HW TSF. */
sc->sc_flags &= ~SC_OP_TSF_RESET;
}
/*
@ -643,25 +627,20 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
{
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
u64 tsf;
u32 tsftu, intval, nexttbtt;
u32 tsf, delta, intval, nexttbtt;
intval = conf->beacon_interval & ATH9K_BEACON_PERIOD;
tsf = ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE);
intval = TU_TO_USEC(conf->beacon_interval & ATH9K_BEACON_PERIOD);
/* Pull nexttbtt forward to reflect the current TSF */
nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp);
if (nexttbtt == 0)
nexttbtt = intval;
else if (intval)
nexttbtt = roundup(nexttbtt, intval);
tsf = ath9k_hw_gettsf64(ah);
tsftu = TSF_TO_TU((u32)(tsf>>32), (u32)tsf) + FUDGE;
do {
nexttbtt += intval;
} while (nexttbtt < tsftu);
if (!sc->beacon.bc_tstamp)
nexttbtt = tsf + intval;
else {
if (tsf > sc->beacon.bc_tstamp)
delta = (tsf - sc->beacon.bc_tstamp);
else
delta = (tsf + 1 + (~0U - sc->beacon.bc_tstamp));
nexttbtt = tsf + roundup(delta, intval);
}
ath_dbg(common, ATH_DBG_BEACON,
"IBSS nexttbtt %u intval %u (%u)\n",
@ -672,7 +651,6 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
* if we need to manually prepare beacon frames. Otherwise we use a
* self-linked tx descriptor and let the hardware deal with things.
*/
intval |= ATH9K_BEACON_ENA;
ah->imask |= ATH9K_INT_SWBA;
ath_beaconq_config(sc);
@ -685,22 +663,63 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
ath9k_hw_set_interrupts(ah, ah->imask);
}
void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
static bool ath9k_allow_beacon_config(struct ath_softc *sc,
struct ieee80211_vif *vif)
{
struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
enum nl80211_iftype iftype;
struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
struct ath_vif *avp = (void *)vif->drv_priv;
/*
* Can not have different beacon interval on multiple
* AP interface case
*/
if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
(sc->nbcnvifs > 1) &&
(vif->type == NL80211_IFTYPE_AP) &&
(cur_conf->beacon_interval != bss_conf->beacon_int)) {
ath_dbg(common, ATH_DBG_CONFIG,
"Changing beacon interval of multiple \
AP interfaces !\n");
return false;
}
/*
* Can not configure station vif's beacon config
* while on AP opmode
*/
if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
(vif->type != NL80211_IFTYPE_AP)) {
ath_dbg(common, ATH_DBG_CONFIG,
"STA vif's beacon not allowed on AP mode\n");
return false;
}
/*
* Do not allow beacon config if HW was already configured
* with another STA vif
*/
if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
(vif->type == NL80211_IFTYPE_STATION) &&
(sc->sc_flags & SC_OP_BEACONS) &&
!avp->primary_sta_vif) {
ath_dbg(common, ATH_DBG_CONFIG,
"Beacon already configured for a station interface\n");
return false;
}
return true;
}
void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
{
struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
if (!ath9k_allow_beacon_config(sc, vif))
return;
/* Setup the beacon configuration parameters */
if (vif) {
struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
iftype = vif->type;
cur_conf->beacon_interval = bss_conf->beacon_int;
cur_conf->dtim_period = bss_conf->dtim_period;
} else {
iftype = sc->sc_ah->opmode;
}
cur_conf->beacon_interval = bss_conf->beacon_int;
cur_conf->dtim_period = bss_conf->dtim_period;
cur_conf->listen_interval = 1;
cur_conf->dtim_count = 1;
cur_conf->bmiss_timeout =
@ -723,7 +742,16 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
if (cur_conf->dtim_period == 0)
cur_conf->dtim_period = 1;
switch (iftype) {
ath_set_beacon(sc);
sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
}
void ath_set_beacon(struct ath_softc *sc)
{
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
switch (sc->sc_ah->opmode) {
case NL80211_IFTYPE_AP:
ath_beacon_config_ap(sc, cur_conf);
break;
@ -750,22 +778,23 @@ void ath9k_set_beaconing_status(struct ath_softc *sc, bool status)
int slot;
bool found = false;
ath9k_ps_wakeup(sc);
if (status) {
for (slot = 0; slot < ATH_BCBUF; slot++) {
if (sc->beacon.bslot[slot]) {
avp = (void *)sc->beacon.bslot[slot]->drv_priv;
if (avp->is_bslot_active) {
found = true;
break;
}
for (slot = 0; slot < ATH_BCBUF; slot++) {
if (sc->beacon.bslot[slot]) {
avp = (void *)sc->beacon.bslot[slot]->drv_priv;
if (avp->is_bslot_active) {
found = true;
break;
}
}
if (found) {
/* Re-enable beaconing */
ah->imask |= ATH9K_INT_SWBA;
ath9k_hw_set_interrupts(ah, ah->imask);
}
}
if (!found)
return;
ath9k_ps_wakeup(sc);
if (status) {
/* Re-enable beaconing */
ah->imask |= ATH9K_INT_SWBA;
ath9k_hw_set_interrupts(ah, ah->imask);
} else {
/* Disable SWBA interrupt */
ah->imask &= ~ATH9K_INT_SWBA;

2
drivers/net/wireless/ath/ath9k/common.c
View File

@ -116,7 +116,7 @@ void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
if (chan->band == IEEE80211_BAND_2GHZ) {
ichan->chanmode = CHANNEL_G;
ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
} else {
ichan->chanmode = CHANNEL_A;
ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;

90
drivers/net/wireless/ath/ath9k/debug.c
View File

@ -1088,67 +1088,43 @@ int ath9k_init_debug(struct ath_hw *ah)
return -ENOMEM;
#ifdef CONFIG_ATH_DEBUG
if (!debugfs_create_file("debug", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, sc, &fops_debug))
goto err;
debugfs_create_file("debug", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
sc, &fops_debug);
#endif
debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
&fops_dma);
debugfs_create_file("interrupt", S_IRUSR, sc->debug.debugfs_phy, sc,
&fops_interrupt);
debugfs_create_file("wiphy", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
sc, &fops_wiphy);
debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy, sc,
&fops_xmit);
debugfs_create_file("stations", S_IRUSR, sc->debug.debugfs_phy, sc,
&fops_stations);
debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy, sc,
&fops_misc);
debugfs_create_file("recv", S_IRUSR, sc->debug.debugfs_phy, sc,
&fops_recv);
debugfs_create_file("rx_chainmask", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, sc, &fops_rx_chainmask);
debugfs_create_file("tx_chainmask", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, sc, &fops_tx_chainmask);
debugfs_create_file("regidx", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
sc, &fops_regidx);
debugfs_create_file("regval", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
sc, &fops_regval);
debugfs_create_bool("ignore_extcca", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy,
&ah->config.cwm_ignore_extcca);
debugfs_create_file("regdump", S_IRUSR, sc->debug.debugfs_phy, sc,
&fops_regdump);
if (!debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy,
sc, &fops_dma))
goto err;
debugfs_create_u32("gpio_mask", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask);
if (!debugfs_create_file("interrupt", S_IRUSR, sc->debug.debugfs_phy,
sc, &fops_interrupt))
goto err;
if (!debugfs_create_file("wiphy", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, sc, &fops_wiphy))
goto err;
if (!debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy,
sc, &fops_xmit))
goto err;
if (!debugfs_create_file("stations", S_IRUSR, sc->debug.debugfs_phy,
sc, &fops_stations))
goto err;
if (!debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy,
sc, &fops_misc))
goto err;
if (!debugfs_create_file("recv", S_IRUSR, sc->debug.debugfs_phy,
sc, &fops_recv))
goto err;
if (!debugfs_create_file("rx_chainmask", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, sc, &fops_rx_chainmask))
goto err;
if (!debugfs_create_file("tx_chainmask", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, sc, &fops_tx_chainmask))
goto err;
if (!debugfs_create_file("regidx", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, sc, &fops_regidx))
goto err;
if (!debugfs_create_file("regval", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, sc, &fops_regval))
goto err;
if (!debugfs_create_bool("ignore_extcca", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, &ah->config.cwm_ignore_extcca))
goto err;
if (!debugfs_create_file("regdump", S_IRUSR, sc->debug.debugfs_phy,
sc, &fops_regdump))
goto err;
debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, &sc->sc_ah->gpio_val);
sc->debug.regidx = 0;
return 0;
err:
debugfs_remove_recursive(sc->debug.debugfs_phy);
sc->debug.debugfs_phy = NULL;
return -ENOMEM;
}

6
drivers/net/wireless/ath/ath9k/eeprom_9287.c
View File

@ -392,6 +392,8 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
numXpdGain);
}
ENABLE_REGWRITE_BUFFER(ah);
if (i == 0) {
if (!ath9k_hw_ar9287_get_eeprom(ah,
EEP_OL_PWRCTRL)) {
@ -442,6 +444,7 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
regOffset += 4;
}
}
REGWRITE_BUFFER_FLUSH(ah);
}
}
@ -757,6 +760,8 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
}
ENABLE_REGWRITE_BUFFER(ah);
/* OFDM power per rate */
REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
ATH9K_POW_SM(ratesArray[rate18mb], 24)
@ -840,6 +845,7 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
| ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
| ATH9K_POW_SM(ratesArray[rateDupCck], 0));
}
REGWRITE_BUFFER_FLUSH(ah);
}
static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,

7
drivers/net/wireless/ath/ath9k/eeprom_def.c
View File

@ -799,6 +799,8 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
pwr_table_offset,
&diff);
ENABLE_REGWRITE_BUFFER(ah);
if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
if (OLC_FOR_AR9280_20_LATER) {
REG_WRITE(ah,
@ -847,6 +849,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
regOffset += 4;
}
REGWRITE_BUFFER_FLUSH(ah);
}
}
@ -1205,6 +1208,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
}
}
ENABLE_REGWRITE_BUFFER(ah);
REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
ATH9K_POW_SM(ratesArray[rate18mb], 24)
| ATH9K_POW_SM(ratesArray[rate12mb], 16)
@ -1291,6 +1296,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
| ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
REGWRITE_BUFFER_FLUSH(ah);
}
static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)

14
drivers/net/wireless/ath/ath9k/gpio.c
View File

@ -41,12 +41,14 @@ void ath_init_leds(struct ath_softc *sc)
{
int ret;
if (AR_SREV_9287(sc->sc_ah))
sc->sc_ah->led_pin = ATH_LED_PIN_9287;
else if (AR_SREV_9485(sc->sc_ah))
sc->sc_ah->led_pin = ATH_LED_PIN_9485;
else
sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
if (sc->sc_ah->led_pin < 0) {
if (AR_SREV_9287(sc->sc_ah))
sc->sc_ah->led_pin = ATH_LED_PIN_9287;
else if (AR_SREV_9485(sc->sc_ah))
sc->sc_ah->led_pin = ATH_LED_PIN_9485;
else
sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
}
/* Configure gpio 1 for output */
ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,

2
drivers/net/wireless/ath/ath9k/htc.h
View File

@ -328,7 +328,7 @@ struct ath9k_debug {
#endif /* CONFIG_ATH9K_HTC_DEBUGFS */
#define ATH_LED_PIN_DEF 1
#define ATH_LED_PIN_9287 8
#define ATH_LED_PIN_9287 10
#define ATH_LED_PIN_9271 15
#define ATH_LED_PIN_7010 12
#define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */

9
drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
View File

@ -155,7 +155,7 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
nexttbtt = intval;
if (priv->op_flags & OP_TSF_RESET) {
intval |= ATH9K_BEACON_RESET_TSF;
ath9k_hw_reset_tsf(priv->ah);
priv->op_flags &= ~OP_TSF_RESET;
} else {
/*
@ -168,8 +168,6 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
} while (nexttbtt < tsftu);
}
intval |= ATH9K_BEACON_ENA;
if (priv->op_flags & OP_ENABLE_BEACON)
imask |= ATH9K_INT_SWBA;
@ -178,7 +176,7 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
bss_conf->beacon_interval, nexttbtt, imask);
WMI_CMD(WMI_DISABLE_INTR_CMDID);
ath9k_hw_beaconinit(priv->ah, nexttbtt, intval);
ath9k_hw_beaconinit(priv->ah, TU_TO_USEC(nexttbtt), TU_TO_USEC(intval));
priv->bmiss_cnt = 0;
htc_imask = cpu_to_be32(imask);
WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask);
@ -207,7 +205,6 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
nexttbtt += intval;
} while (nexttbtt < tsftu);
intval |= ATH9K_BEACON_ENA;
if (priv->op_flags & OP_ENABLE_BEACON)
imask |= ATH9K_INT_SWBA;
@ -216,7 +213,7 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
bss_conf->beacon_interval, nexttbtt, imask);
WMI_CMD(WMI_DISABLE_INTR_CMDID);
ath9k_hw_beaconinit(priv->ah, nexttbtt, intval);
ath9k_hw_beaconinit(priv->ah, TU_TO_USEC(nexttbtt), TU_TO_USEC(intval));
priv->bmiss_cnt = 0;
htc_imask = cpu_to_be32(imask);
WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask);

33
drivers/net/wireless/ath/ath9k/htc_drv_init.c
View File

@ -430,13 +430,16 @@ static void ath9k_regwrite_flush(void *hw_priv)
mutex_unlock(&priv->wmi->multi_write_mutex);
}
static const struct ath_ops ath9k_common_ops = {
.read = ath9k_regread,
.multi_read = ath9k_multi_regread,
.write = ath9k_regwrite,
.enable_write_buffer = ath9k_enable_regwrite_buffer,
.write_flush = ath9k_regwrite_flush,
};
static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
{
u32 val;
val = ath9k_regread(hw_priv, reg_offset);
val &= ~clr;
val |= set;
ath9k_regwrite(hw_priv, val, reg_offset);
return val;
}
static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
{
@ -561,13 +564,7 @@ static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
int i = 0;
/* Get the hardware key cache size. */
common->keymax = priv->ah->caps.keycache_size;
if (common->keymax > ATH_KEYMAX) {
ath_dbg(common, ATH_DBG_ANY,
"Warning, using only %u entries in %u key cache\n",
ATH_KEYMAX, common->keymax);
common->keymax = ATH_KEYMAX;
}
common->keymax = AR_KEYTABLE_SIZE;
if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
@ -658,10 +655,16 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
ah->hw_version.subsysid = 0; /* FIXME */
ah->hw_version.usbdev = drv_info;
ah->ah_flags |= AH_USE_EEPROM;
ah->reg_ops.read = ath9k_regread;
ah->reg_ops.multi_read = ath9k_multi_regread;
ah->reg_ops.write = ath9k_regwrite;
ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
ah->reg_ops.write_flush = ath9k_regwrite_flush;
ah->reg_ops.rmw = ath9k_reg_rmw;
priv->ah = ah;
common = ath9k_hw_common(ah);
common->ops = &ath9k_common_ops;
common->ops = &ah->reg_ops;
common->bus_ops = &ath9k_usb_bus_ops;
common->ah = ah;
common->hw = priv->hw;

6
drivers/net/wireless/ath/ath9k/hw-ops.h
View File

@ -122,12 +122,6 @@ static inline void ath9k_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
ath9k_hw_ops(ah)->set11n_burstduration(ah, ds, burstDuration);
}
static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
u32 vmf)
{
ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
}
/* Private hardware call ops */
/* PHY ops */

206
drivers/net/wireless/ath/ath9k/hw.c
View File

@ -130,6 +130,20 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
}
EXPORT_SYMBOL(ath9k_hw_wait);
void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
int column, unsigned int *writecnt)
{
int r;
ENABLE_REGWRITE_BUFFER(ah);
for (r = 0; r < array->ia_rows; r++) {
REG_WRITE(ah, INI_RA(array, r, 0),
INI_RA(array, r, column));
DO_DELAY(*writecnt);
}
REGWRITE_BUFFER_FLUSH(ah);
}
u32 ath9k_hw_reverse_bits(u32 val, u32 n)
{
u32 retval;
@ -142,25 +156,6 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n)
return retval;
}
bool ath9k_get_channel_edges(struct ath_hw *ah,
u16 flags, u16 *low,
u16 *high)
{
struct ath9k_hw_capabilities *pCap = &ah->caps;
if (flags & CHANNEL_5GHZ) {
*low = pCap->low_5ghz_chan;
*high = pCap->high_5ghz_chan;
return true;
}
if ((flags & CHANNEL_2GHZ)) {
*low = pCap->low_2ghz_chan;
*high = pCap->high_2ghz_chan;
return true;
}
return false;
}
u16 ath9k_hw_computetxtime(struct ath_hw *ah,
u8 phy, int kbps,
u32 frameLen, u16 rateix,
@ -364,11 +359,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
ah->config.spurchans[i][1] = AR_NO_SPUR;
}
if (ah->hw_version.devid != AR2427_DEVID_PCIE)
ah->config.ht_enable = 1;
else
ah->config.ht_enable = 0;
/* PAPRD needs some more work to be enabled */
ah->config.paprd_disable = 1;
@ -410,6 +400,8 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
ah->sta_id1_defaults =
AR_STA_ID1_CRPT_MIC_ENABLE |
AR_STA_ID1_MCAST_KSRCH;
if (AR_SREV_9100(ah))
ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
ah->enable_32kHz_clock = DONT_USE_32KHZ;
ah->slottime = 20;
ah->globaltxtimeout = (u32) -1;
@ -673,14 +665,14 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
{
REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK)));
REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
udelay(100);
REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
udelay(100);
REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK));
while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
udelay(100);
return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
}
EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
@ -830,8 +822,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
ah->misc_mode);
if (ah->misc_mode != 0)
REG_WRITE(ah, AR_PCU_MISC,
REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
sifstime = 16;
@ -899,23 +890,19 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
static inline void ath9k_hw_set_dma(struct ath_hw *ah)
{
struct ath_common *common = ath9k_hw_common(ah);
u32 regval;
ENABLE_REGWRITE_BUFFER(ah);
/*
* set AHB_MODE not to do cacheline prefetches
*/
if (!AR_SREV_9300_20_OR_LATER(ah)) {
regval = REG_READ(ah, AR_AHB_MODE);
REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
}
if (!AR_SREV_9300_20_OR_LATER(ah))
REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
/*
* let mac dma reads be in 128 byte chunks
*/
regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
REGWRITE_BUFFER_FLUSH(ah);
@ -932,8 +919,7 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
/*
* let mac dma writes be in 128 byte chunks
*/
regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
/*
* Setup receive FIFO threshold to hold off TX activities
@ -972,30 +958,27 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
{
u32 val;
u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
u32 set = AR_STA_ID1_KSRCH_MODE;
val = REG_READ(ah, AR_STA_ID1);
val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
switch (opmode) {
case NL80211_IFTYPE_AP:
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
| AR_STA_ID1_KSRCH_MODE);
REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
break;
case NL80211_IFTYPE_ADHOC:
case NL80211_IFTYPE_MESH_POINT:
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
| AR_STA_ID1_KSRCH_MODE);
set |= AR_STA_ID1_ADHOC;
REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
break;
case NL80211_IFTYPE_AP:
set |= AR_STA_ID1_STA_AP;
/* fall through */
case NL80211_IFTYPE_STATION:
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
break;
default:
if (ah->is_monitoring)
REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
if (!ah->is_monitoring)
set = 0;
break;
}
REG_RMW(ah, AR_STA_ID1, set, mask);
}
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
@ -1021,10 +1004,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
u32 tmpReg;
if (AR_SREV_9100(ah)) {
u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
val &= ~AR_RTC_DERIVED_CLK_PERIOD;
val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
AR_RTC_DERIVED_CLK_PERIOD, 1);
(void)REG_READ(ah, AR_RTC_DERIVED_CLK);
}
@ -1212,6 +1193,20 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
return true;
}
static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
{
u32 gpio_mask = ah->gpio_mask;
int i;
for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
if (!(gpio_mask & 1))
continue;
ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
}
}
bool ath9k_hw_check_alive(struct ath_hw *ah)
{
int count = 50;
@ -1418,7 +1413,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
REGWRITE_BUFFER_FLUSH(ah);
ah->intr_txqs = 0;
for (i = 0; i < ah->caps.total_queues; i++)
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
ath9k_hw_resettxqueue(ah, i);
ath9k_hw_init_interrupt_masks(ah, ah->opmode);
@ -1435,8 +1430,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ar9002_hw_enable_wep_aggregation(ah);
}
REG_WRITE(ah, AR_STA_ID1,
REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
ath9k_hw_set_dma(ah);
@ -1500,6 +1494,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
if (AR_SREV_9300_20_OR_LATER(ah))
ar9003_hw_bb_watchdog_config(ah);
ath9k_hw_apply_gpio_override(ah);
return 0;
}
EXPORT_SYMBOL(ath9k_hw_reset);
@ -1679,21 +1675,15 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
case NL80211_IFTYPE_MESH_POINT:
REG_SET_BIT(ah, AR_TXCFG,
AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
REG_WRITE(ah, AR_NEXT_NDP_TIMER,
TU_TO_USEC(next_beacon +
(ah->atim_window ? ah->
atim_window : 1)));
REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
flags |= AR_NDP_TIMER_EN;
case NL80211_IFTYPE_AP:
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
TU_TO_USEC(next_beacon -
ah->config.
dma_beacon_response_time));
REG_WRITE(ah, AR_NEXT_SWBA,
TU_TO_USEC(next_beacon -
ah->config.
sw_beacon_response_time));
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
TU_TO_USEC(ah->config.dma_beacon_response_time));
REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
TU_TO_USEC(ah->config.sw_beacon_response_time));
flags |=
AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
break;
@ -1705,18 +1695,13 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
break;
}
REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
REGWRITE_BUFFER_FLUSH(ah);
beacon_period &= ~ATH9K_BEACON_ENA;
if (beacon_period & ATH9K_BEACON_RESET_TSF) {
ath9k_hw_reset_tsf(ah);
}
REG_SET_BIT(ah, AR_TIMER_MODE, flags);
}
EXPORT_SYMBOL(ath9k_hw_beaconinit);
@ -1851,6 +1836,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
!(AR_SREV_9271(ah)))
/* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
else if (AR_SREV_9100(ah))
pCap->rx_chainmask = 0x7;
else
/* Use rx_chainmask from EEPROM. */
pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
@ -1861,36 +1848,13 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
if (AR_SREV_9300_20_OR_LATER(ah))
ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
pCap->low_2ghz_chan = 2312;
pCap->high_2ghz_chan = 2732;
pCap->low_5ghz_chan = 4920;
pCap->high_5ghz_chan = 6100;
common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
if (ah->config.ht_enable)
if (ah->hw_version.devid != AR2427_DEVID_PCIE)
pCap->hw_caps |= ATH9K_HW_CAP_HT;
else
pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
if (capField & AR_EEPROM_EEPCAP_MAXQCU)
pCap->total_queues =
MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
else
pCap->total_queues = ATH9K_NUM_TX_QUEUES;
if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
pCap->keycache_size =
1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
else
pCap->keycache_size = AR_KEYTABLE_SIZE;
if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
else
pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
if (AR_SREV_9271(ah))
pCap->num_gpio_pins = AR9271_NUM_GPIO;
else if (AR_DEVID_7010(ah))
@ -1909,8 +1873,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
pCap->rts_aggr_limit = (8 * 1024);
}
pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
@ -1932,23 +1894,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
else
pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
pCap->reg_cap =
AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
AR_EEPROM_EEREGCAP_EN_KK_U2 |
AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
} else {
pCap->reg_cap =
AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
}
/* Advertise midband for AR5416 with FCC midband set in eeprom */
if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
AR_SREV_5416(ah))
pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
@ -2195,11 +2140,9 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
REG_WRITE(ah, AR_PHY_ERR, phybits);
if (phybits)
REG_WRITE(ah, AR_RXCFG,
REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
else
REG_WRITE(ah, AR_RXCFG,
REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
REGWRITE_BUFFER_FLUSH(ah);
}
@ -2375,10 +2318,11 @@ static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
return timer_table->gen_timer_index[b];
}
static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
u32 ath9k_hw_gettsf32(struct ath_hw *ah)
{
return REG_READ(ah, AR_TSF_L32);
}
EXPORT_SYMBOL(ath9k_hw_gettsf32);
struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
void (*trigger)(void *),

66
drivers/net/wireless/ath/ath9k/hw.h
View File

@ -65,53 +65,49 @@
/* Register read/write primitives */
#define REG_WRITE(_ah, _reg, _val) \
ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
(_ah)->reg_ops.write((_ah), (_val), (_reg))
#define REG_READ(_ah, _reg) \
ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
(_ah)->reg_ops.read((_ah), (_reg))
#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
ath9k_hw_common(_ah)->ops->multi_read((_ah), (_addr), (_val), (_cnt))
(_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
#define REG_RMW(_ah, _reg, _set, _clr) \
(_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
#define ENABLE_REGWRITE_BUFFER(_ah) \
do { \
if (ath9k_hw_common(_ah)->ops->enable_write_buffer) \
ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
if ((_ah)->reg_ops.enable_write_buffer) \
(_ah)->reg_ops.enable_write_buffer((_ah)); \
} while (0)
#define REGWRITE_BUFFER_FLUSH(_ah) \
do { \
if (ath9k_hw_common(_ah)->ops->write_flush) \
ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
if ((_ah)->reg_ops.write_flush) \
(_ah)->reg_ops.write_flush((_ah)); \
} while (0)
#define SM(_v, _f) (((_v) << _f##_S) & _f)
#define MS(_v, _f) (((_v) & _f) >> _f##_S)
#define REG_RMW(_a, _r, _set, _clr) \
REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
#define REG_RMW_FIELD(_a, _r, _f, _v) \
REG_WRITE(_a, _r, \
(REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
#define REG_READ_FIELD(_a, _r, _f) \
(((REG_READ(_a, _r) & _f) >> _f##_S))
#define REG_SET_BIT(_a, _r, _f) \
REG_WRITE(_a, _r, REG_READ(_a, _r) | (_f))
REG_RMW(_a, _r, (_f), 0)
#define REG_CLR_BIT(_a, _r, _f) \
REG_WRITE(_a, _r, REG_READ(_a, _r) & ~(_f))
REG_RMW(_a, _r, 0, (_f))
#define DO_DELAY(x) do { \
if ((++(x) % 64) == 0) \
udelay(1); \
#define DO_DELAY(x) do { \
if (((++(x) % 64) == 0) && \
(ath9k_hw_common(ah)->bus_ops->ath_bus_type \
!= ATH_USB)) \
udelay(1); \
} while (0)
#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
int r; \
for (r = 0; r < ((iniarray)->ia_rows); r++) { \
REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
INI_RA((iniarray), r, (column))); \
DO_DELAY(regWr); \
} \
} while (0)
#define REG_WRITE_ARRAY(iniarray, column, regWr) \
ath9k_hw_write_array(ah, iniarray, column, &(regWr))
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
@ -178,7 +174,6 @@ enum ath9k_hw_caps {
ATH9K_HW_CAP_HT = BIT(0),
ATH9K_HW_CAP_RFSILENT = BIT(1),
ATH9K_HW_CAP_CST = BIT(2),
ATH9K_HW_CAP_ENHANCEDPM = BIT(3),
ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
ATH9K_HW_CAP_EDMA = BIT(6),
@ -195,17 +190,11 @@ enum ath9k_hw_caps {
struct ath9k_hw_capabilities {
u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
u16 total_queues;
u16 keycache_size;
u16 low_5ghz_chan, high_5ghz_chan;
u16 low_2ghz_chan, high_2ghz_chan;
u16 rts_aggr_limit;
u8 tx_chainmask;
u8 rx_chainmask;
u8 max_txchains;
u8 max_rxchains;
u16 tx_triglevel_max;
u16 reg_cap;
u8 num_gpio_pins;
u8 rx_hp_qdepth;
u8 rx_lp_qdepth;
@ -227,7 +216,6 @@ struct ath9k_ops_config {
u8 pcie_clock_req;
u32 pcie_waen;
u8 analog_shiftreg;
u8 ht_enable;
u8 paprd_disable;
u32 ofdm_trig_low;
u32 ofdm_trig_high;
@ -412,8 +400,6 @@ struct ath9k_beacon_state {
u32 bs_nextdtim;
u32 bs_intval;
#define ATH9K_BEACON_PERIOD 0x0000ffff
#define ATH9K_BEACON_ENA 0x00800000
#define ATH9K_BEACON_RESET_TSF 0x01000000
#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
u32 bs_dtimperiod;
u16 bs_cfpperiod;
@ -640,8 +626,6 @@ struct ath_hw_ops {
void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
u32 burstDuration);
void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
u32 vmf);
};
struct ath_nf_limits {
@ -655,6 +639,8 @@ struct ath_nf_limits {
#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
struct ath_hw {
struct ath_ops reg_ops;
struct ieee80211_hw *hw;
struct ath_common common;
struct ath9k_hw_version hw_version;
@ -794,7 +780,9 @@ struct ath_hw {
u32 originalGain[22];
int initPDADC;
int PDADCdelta;
u8 led_pin;
int led_pin;
u32 gpio_mask;
u32 gpio_val;
struct ar5416IniArray iniModes;
struct ar5416IniArray iniCommon;
@ -907,8 +895,9 @@ void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
/* General Operation */
bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
int column, unsigned int *writecnt);
u32 ath9k_hw_reverse_bits(u32 val, u32 n);
bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
u16 ath9k_hw_computetxtime(struct ath_hw *ah,
u8 phy, int kbps,
u32 frameLen, u16 rateix, bool shortPreamble);
@ -924,6 +913,7 @@ void ath9k_hw_setopmode(struct ath_hw *ah);
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
void ath9k_hw_setbssidmask(struct ath_hw *ah);
void ath9k_hw_write_associd(struct ath_hw *ah);
u32 ath9k_hw_gettsf32(struct ath_hw *ah);
u64 ath9k_hw_gettsf64(struct ath_hw *ah);
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
void ath9k_hw_reset_tsf(struct ath_hw *ah);

53
drivers/net/wireless/ath/ath9k/init.c
View File

@ -15,6 +15,7 @@
*/
#include <linux/slab.h>
#include <linux/ath9k_platform.h>
#include "ath9k.h"
@ -195,10 +196,27 @@ static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
return val;
}
static const struct ath_ops ath9k_common_ops = {
.read = ath9k_ioread32,
.write = ath9k_iowrite32,
};
static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
{
struct ath_hw *ah = (struct ath_hw *) hw_priv;
struct ath_common *common = ath9k_hw_common(ah);
struct ath_softc *sc = (struct ath_softc *) common->priv;
unsigned long uninitialized_var(flags);
u32 val;
if (ah->config.serialize_regmode == SER_REG_MODE_ON)
spin_lock_irqsave(&sc->sc_serial_rw, flags);
val = ioread32(sc->mem + reg_offset);
val &= ~clr;
val |= set;
iowrite32(val, sc->mem + reg_offset);
if (ah->config.serialize_regmode == SER_REG_MODE_ON)
spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
return val;
}
/**************************/
/* Initialization */
@ -389,13 +407,7 @@ void ath9k_init_crypto(struct ath_softc *sc)
int i = 0;
/* Get the hardware key cache size. */
common->keymax = sc->sc_ah->caps.keycache_size;
if (common->keymax > ATH_KEYMAX) {
ath_dbg(common, ATH_DBG_ANY,
"Warning, using only %u entries in %u key cache\n",
ATH_KEYMAX, common->keymax);
common->keymax = ATH_KEYMAX;
}
common->keymax = AR_KEYTABLE_SIZE;
/*
* Reset the key cache since some parts do not
@ -537,6 +549,7 @@ static void ath9k_init_misc(struct ath_softc *sc)
static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
const struct ath_bus_ops *bus_ops)
{
struct ath9k_platform_data *pdata = sc->dev->platform_data;
struct ath_hw *ah = NULL;
struct ath_common *common;
int ret = 0, i;
@ -549,13 +562,22 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
ah->hw = sc->hw;
ah->hw_version.devid = devid;
ah->hw_version.subsysid = subsysid;
ah->reg_ops.read = ath9k_ioread32;
ah->reg_ops.write = ath9k_iowrite32;
ah->reg_ops.rmw = ath9k_reg_rmw;
sc->sc_ah = ah;
if (!sc->dev->platform_data)
if (!pdata) {
ah->ah_flags |= AH_USE_EEPROM;
sc->sc_ah->led_pin = -1;
} else {
sc->sc_ah->gpio_mask = pdata->gpio_mask;
sc->sc_ah->gpio_val = pdata->gpio_val;
sc->sc_ah->led_pin = pdata->led_pin;
}
common = ath9k_hw_common(ah);
common->ops = &ath9k_common_ops;
common->ops = &ah->reg_ops;
common->bus_ops = bus_ops;
common->ah = ah;
common->hw = sc->hw;
@ -587,6 +609,9 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
if (ret)
goto err_hw;
if (pdata && pdata->macaddr)
memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
ret = ath9k_init_queues(sc);
if (ret)
goto err_queues;
@ -679,6 +704,8 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
if (AR_SREV_5416(sc->sc_ah))
hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
hw->queues = 4;
hw->max_rates = 4;
hw->channel_change_time = 5000;

113
drivers/net/wireless/ath/ath9k/mac.c
View File

@ -209,15 +209,8 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
{
u32 cw;
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) {
ath_dbg(common, ATH_DBG_QUEUE,
"Set TXQ properties, invalid queue: %u\n", q);
return false;
}
qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
ath_dbg(common, ATH_DBG_QUEUE,
@ -280,15 +273,8 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
struct ath9k_tx_queue_info *qinfo)
{
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) {
ath_dbg(common, ATH_DBG_QUEUE,
"Get TXQ properties, invalid queue: %u\n", q);
return false;
}
qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
ath_dbg(common, ATH_DBG_QUEUE,
@ -320,28 +306,27 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
{
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_tx_queue_info *qi;
struct ath9k_hw_capabilities *pCap = &ah->caps;
int q;
switch (type) {
case ATH9K_TX_QUEUE_BEACON:
q = pCap->total_queues - 1;
q = ATH9K_NUM_TX_QUEUES - 1;
break;
case ATH9K_TX_QUEUE_CAB:
q = pCap->total_queues - 2;
q = ATH9K_NUM_TX_QUEUES - 2;
break;
case ATH9K_TX_QUEUE_PSPOLL:
q = 1;
break;
case ATH9K_TX_QUEUE_UAPSD:
q = pCap->total_queues - 3;
q = ATH9K_NUM_TX_QUEUES - 3;
break;
case ATH9K_TX_QUEUE_DATA:
for (q = 0; q < pCap->total_queues; q++)
for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
if (ah->txq[q].tqi_type ==
ATH9K_TX_QUEUE_INACTIVE)
break;
if (q == pCap->total_queues) {
if (q == ATH9K_NUM_TX_QUEUES) {
ath_err(common, "No available TX queue\n");
return -1;
}
@ -382,15 +367,9 @@ EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
{
struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) {
ath_dbg(common, ATH_DBG_QUEUE,
"Release TXQ, invalid queue: %u\n", q);
return false;
}
qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
ath_dbg(common, ATH_DBG_QUEUE,
@ -414,18 +393,11 @@ EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
{
struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_channel *chan = ah->curchan;
struct ath9k_tx_queue_info *qi;
u32 cwMin, chanCwMin, value;
if (q >= pCap->total_queues) {
ath_dbg(common, ATH_DBG_QUEUE,
"Reset TXQ, invalid queue: %u\n", q);
return false;
}
qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
ath_dbg(common, ATH_DBG_QUEUE,
@ -465,10 +437,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
REG_WRITE(ah, AR_QCBRCFG(q),
SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
REG_WRITE(ah, AR_QMISC(q),
REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
(qi->tqi_cbrOverflowLimit ?
AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
(qi->tqi_cbrOverflowLimit ?
AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
}
if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
REG_WRITE(ah, AR_QRDYTIMECFG(q),
@ -481,40 +452,31 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
(qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
if (qi->tqi_burstTime
&& (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
REG_WRITE(ah, AR_QMISC(q),
REG_READ(ah, AR_QMISC(q)) |
AR_Q_MISC_RDYTIME_EXP_POLICY);
&& (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
}
if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
REG_WRITE(ah, AR_DMISC(q),
REG_READ(ah, AR_DMISC(q)) |
AR_D_MISC_POST_FR_BKOFF_DIS);
}
if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
REGWRITE_BUFFER_FLUSH(ah);
if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
REG_WRITE(ah, AR_DMISC(q),
REG_READ(ah, AR_DMISC(q)) |
AR_D_MISC_FRAG_BKOFF_EN);
}
if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
switch (qi->tqi_type) {
case ATH9K_TX_QUEUE_BEACON:
ENABLE_REGWRITE_BUFFER(ah);
REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
| AR_Q_MISC_FSP_DBA_GATED
| AR_Q_MISC_BEACON_USE
| AR_Q_MISC_CBR_INCR_DIS1);
REG_SET_BIT(ah, AR_QMISC(q),
AR_Q_MISC_FSP_DBA_GATED
| AR_Q_MISC_BEACON_USE
| AR_Q_MISC_CBR_INCR_DIS1);
REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
| (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
REG_SET_BIT(ah, AR_DMISC(q),
(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
| AR_D_MISC_BEACON_USE
| AR_D_MISC_POST_FR_BKOFF_DIS);
| AR_D_MISC_BEACON_USE
| AR_D_MISC_POST_FR_BKOFF_DIS);
REGWRITE_BUFFER_FLUSH(ah);
@ -533,41 +495,38 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
case ATH9K_TX_QUEUE_CAB:
ENABLE_REGWRITE_BUFFER(ah);
REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
| AR_Q_MISC_FSP_DBA_GATED
| AR_Q_MISC_CBR_INCR_DIS1
| AR_Q_MISC_CBR_INCR_DIS0);
REG_SET_BIT(ah, AR_QMISC(q),
AR_Q_MISC_FSP_DBA_GATED
| AR_Q_MISC_CBR_INCR_DIS1
| AR_Q_MISC_CBR_INCR_DIS0);
value = (qi->tqi_readyTime -
(ah->config.sw_beacon_response_time -
ah->config.dma_beacon_response_time) -
ah->config.additional_swba_backoff) * 1024;
REG_WRITE(ah, AR_QRDYTIMECFG(q),
value | AR_Q_RDYTIMECFG_EN);
REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
| (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
REG_SET_BIT(ah, AR_DMISC(q),
(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
REGWRITE_BUFFER_FLUSH(ah);
break;
case ATH9K_TX_QUEUE_PSPOLL:
REG_WRITE(ah, AR_QMISC(q),
REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
break;
case ATH9K_TX_QUEUE_UAPSD:
REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
AR_D_MISC_POST_FR_BKOFF_DIS);
REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
break;
default:
break;
}
if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
REG_WRITE(ah, AR_DMISC(q),
REG_READ(ah, AR_DMISC(q)) |
SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
AR_D_MISC_ARB_LOCKOUT_CNTRL) |
AR_D_MISC_POST_FR_BKOFF_DIS);
REG_SET_BIT(ah, AR_DMISC(q),
SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
AR_D_MISC_ARB_LOCKOUT_CNTRL) |
AR_D_MISC_POST_FR_BKOFF_DIS);
}
if (AR_SREV_9300_20_OR_LATER(ah))
@ -754,7 +713,6 @@ EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
{
#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
#define AH_RX_TIME_QUANTUM 100 /* usec */
struct ath_common *common = ath9k_hw_common(ah);
int i;
@ -778,7 +736,6 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
return true;
}
#undef AH_RX_TIME_QUANTUM
#undef AH_RX_STOP_DMA_TIMEOUT
}
EXPORT_SYMBOL(ath9k_hw_stopdmarecv);

175
drivers/net/wireless/ath/ath9k/main.c
View File

@ -299,7 +299,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
if (sc->sc_flags & SC_OP_BEACONS)
ath_beacon_config(sc, NULL);
ath_set_beacon(sc);
ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
ath_start_ani(common);
@ -828,48 +828,6 @@ chip_reset:
#undef SCHED_INTR
}
static void ath9k_bss_assoc_info(struct ath_softc *sc,
struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct ieee80211_bss_conf *bss_conf)
{
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
if (bss_conf->assoc) {
ath_dbg(common, ATH_DBG_CONFIG,
"Bss Info ASSOC %d, bssid: %pM\n",
bss_conf->aid, common->curbssid);
/* New association, store aid */
common->curaid = bss_conf->aid;
ath9k_hw_write_associd(ah);
/*
* Request a re-configuration of Beacon related timers
* on the receipt of the first Beacon frame (i.e.,
* after time sync with the AP).
*/
sc->ps_flags |= PS_BEACON_SYNC;
/* Configure the beacon */
ath_beacon_config(sc, vif);
/* Reset rssi stats */
sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
sc->sc_flags |= SC_OP_ANI_RUN;
ath_start_ani(common);
} else {
ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
common->curaid = 0;
/* Stop ANI */
sc->sc_flags &= ~SC_OP_ANI_RUN;
del_timer_sync(&common->ani.timer);
}
}
void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
{
struct ath_hw *ah = sc->sc_ah;
@ -899,7 +857,7 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
goto out;
}
if (sc->sc_flags & SC_OP_BEACONS)
ath_beacon_config(sc, NULL); /* restart beacons */
ath_set_beacon(sc); /* restart beacons */
/* Re-Enable interrupts */
ath9k_hw_set_interrupts(ah, ah->imask);
@ -1006,7 +964,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
sc->config.txpowlimit, &sc->curtxpow);
if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
ath_beacon_config(sc, NULL); /* restart beacons */
ath_set_beacon(sc); /* restart beacons */
ath9k_hw_set_interrupts(ah, ah->imask);
@ -1415,9 +1373,6 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
if ((iter_data.naps + iter_data.nadhocs) > 0) {
sc->sc_flags |= SC_OP_ANI_RUN;
ath_start_ani(common);
} else {
sc->sc_flags &= ~SC_OP_ANI_RUN;
del_timer_sync(&common->ani.timer);
}
}
@ -1452,7 +1407,6 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
struct ath_softc *sc = hw->priv;
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath_vif *avp = (void *)vif->drv_priv;
int ret = 0;
ath9k_ps_wakeup(sc);
@ -1482,8 +1436,9 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
}
}
if ((vif->type == NL80211_IFTYPE_ADHOC) &&
sc->nvifs > 0) {
if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
((vif->type == NL80211_IFTYPE_ADHOC) &&
sc->nvifs > 0)) {
ath_err(common, "Cannot create ADHOC interface when other"
" interfaces already exist.\n");
ret = -EINVAL;
@ -1493,10 +1448,6 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
ath_dbg(common, ATH_DBG_CONFIG,
"Attach a VIF of type: %d\n", vif->type);
/* Set the VIF opmode */
avp->av_opmode = vif->type;
avp->av_bslot = -1;
sc->nvifs++;
ath9k_do_vif_add_setup(hw, vif);
@ -1855,6 +1806,20 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
if (ath9k_modparam_nohwcrypt)
return -ENOSPC;
if (vif->type == NL80211_IFTYPE_ADHOC &&
(key->cipher == WLAN_CIPHER_SUITE_TKIP ||
key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
/*
* For now, disable hw crypto for the RSN IBSS group keys. This
* could be optimized in the future to use a modified key cache
* design to support per-STA RX GTK, but until that gets
* implemented, use of software crypto for group addressed
* frames is a acceptable to allow RSN IBSS to be used.
*/
return -EOPNOTSUPP;
}
mutex_lock(&sc->mutex);
ath9k_ps_wakeup(sc);
ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
@ -1886,6 +1851,86 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
return ret;
}
static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
{
struct ath_softc *sc = data;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
struct ath_vif *avp = (void *)vif->drv_priv;
switch (sc->sc_ah->opmode) {
case NL80211_IFTYPE_ADHOC:
/* There can be only one vif available */
memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
common->curaid = bss_conf->aid;
ath9k_hw_write_associd(sc->sc_ah);
/* configure beacon */
if (bss_conf->enable_beacon)
ath_beacon_config(sc, vif);
break;
case NL80211_IFTYPE_STATION:
/*
* Skip iteration if primary station vif's bss info
* was not changed
*/
if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
break;
if (bss_conf->assoc) {
sc->sc_flags |= SC_OP_PRIM_STA_VIF;
avp->primary_sta_vif = true;
memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
common->curaid = bss_conf->aid;
ath9k_hw_write_associd(sc->sc_ah);
ath_dbg(common, ATH_DBG_CONFIG,
"Bss Info ASSOC %d, bssid: %pM\n",
bss_conf->aid, common->curbssid);
ath_beacon_config(sc, vif);
/* Reset rssi stats */
sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
sc->sc_flags |= SC_OP_ANI_RUN;
ath_start_ani(common);
}
break;
default:
break;
}
}
static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
{
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
struct ath_vif *avp = (void *)vif->drv_priv;
/* Reconfigure bss info */
if (avp->primary_sta_vif && !bss_conf->assoc) {
ath_dbg(common, ATH_DBG_CONFIG,
"Bss Info DISASSOC %d, bssid %pM\n",
common->curaid, common->curbssid);
sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
avp->primary_sta_vif = false;
memset(common->curbssid, 0, ETH_ALEN);
common->curaid = 0;
}
ieee80211_iterate_active_interfaces_atomic(
sc->hw, ath9k_bss_iter, sc);
/*
* None of station vifs are associated.
* Clear bssid & aid
*/
if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
ath9k_hw_write_associd(sc->sc_ah);
/* Stop ANI */
sc->sc_flags &= ~SC_OP_ANI_RUN;
del_timer_sync(&common->ani.timer);
}
}
static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
@ -1893,7 +1938,6 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
u32 changed)
{
struct ath_softc *sc = hw->priv;
struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath_vif *avp = (void *)vif->drv_priv;
@ -1904,20 +1948,13 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
mutex_lock(&sc->mutex);
if (changed & BSS_CHANGED_BSSID) {
/* Set BSSID */
memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
common->curaid = 0;
ath9k_hw_write_associd(ah);
ath9k_config_bss(sc, vif);
/* Set aggregation protection mode parameters */
sc->config.ath_aggr_prot = 0;
ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
common->curbssid, common->curaid);
/* need to reconfigure the beacon */
sc->sc_flags &= ~SC_OP_BEACONS ;
}
/* Enable transmission of beacons (AP, IBSS, MESH) */
@ -1958,7 +1995,6 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
}
if (changed & BSS_CHANGED_BEACON_INT) {
cur_conf->beacon_interval = bss_conf->beacon_int;
/*
* In case of AP mode, the HW TSF has to be reset
* when the beacon interval changes.
@ -1970,9 +2006,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
if (!error)
ath_beacon_config(sc, vif);
ath9k_set_beaconing_status(sc, true);
} else {
} else
ath_beacon_config(sc, vif);
}
}
if (changed & BSS_CHANGED_ERP_PREAMBLE) {
@ -1994,12 +2029,6 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
}
if (changed & BSS_CHANGED_ASSOC) {
ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
bss_conf->assoc);
ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
}
mutex_unlock(&sc->mutex);
ath9k_ps_restore(sc);
}

14
drivers/net/wireless/ath/ath9k/phy.h
View File

@ -38,25 +38,11 @@
#define AR_PHY_CLC_Q0 0x0000ffd0
#define AR_PHY_CLC_Q0_S 5
#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
int r; \
for (r = 0; r < ((iniarray)->ia_rows); r++) { \
REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
DO_DELAY(regWr); \
} \
} while (0)
#define ANTSWAP_AB 0x0001
#define REDUCE_CHAIN_0 0x00000050
#define REDUCE_CHAIN_1 0x00000051
#define AR_PHY_CHIP_ID 0x9818
#define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
int i; \
for (i = 0; i < (_iniarray)->ia_rows; i++) \
(_bank)[i] = INI_RA((_iniarray), i, _col);; \
} while (0)
#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20

2
drivers/net/wireless/ath/ath9k/recv.c
View File

@ -574,7 +574,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
sc->ps_flags &= ~PS_BEACON_SYNC;
ath_dbg(common, ATH_DBG_PS,
"Reconfigure Beacon timers based on timestamp from the AP\n");
ath_beacon_config(sc, NULL);
ath_set_beacon(sc);
}
if (ath_beacon_dtim_pending_cab(skb)) {

1
drivers/net/wireless/ath/ath9k/reg.h
View File

@ -1396,6 +1396,7 @@ enum {
#define AR_STA_ID1_PCF 0x00100000
#define AR_STA_ID1_USE_DEFANT 0x00200000
#define AR_STA_ID1_DEFANT_UPDATE 0x00400000
#define AR_STA_ID1_AR9100_BA_FIX 0x00400000
#define AR_STA_ID1_RTS_USE_DEF 0x00800000
#define AR_STA_ID1_ACKCTS_6MB 0x01000000
#define AR_STA_ID1_BASE_RATE_11B 0x02000000

29
drivers/net/wireless/ath/ath9k/xmit.c
View File

@ -1980,7 +1980,7 @@ static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
if (ieee80211_is_data(hdr->frame_control) &&
(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
ATH9K_TX_DELIM_UNDERRUN)) &&
ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
tx_info->status.rates[tx_rateindex].count =
hw->max_rate_tries;
}
@ -2144,33 +2144,6 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
} else {
txq->axq_tx_inprogress = true;
}
} else {
/* If the queue has pending buffers, then it
* should be doing tx work (and have axq_depth).
* Shouldn't get to this state I think..but
* we do.
*/
if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) &&
(txq->pending_frames > 0 ||
!list_empty(&txq->axq_acq) ||
txq->stopped)) {
ath_err(ath9k_hw_common(sc->sc_ah),
"txq: %p axq_qnum: %u,"
" mac80211_qnum: %i"
" axq_link: %p"
" pending frames: %i"
" axq_acq empty: %i"
" stopped: %i"
" axq_depth: 0 Attempting to"
" restart tx logic.\n",
txq, txq->axq_qnum,
txq->mac80211_qnum,
txq->axq_link,
txq->pending_frames,
list_empty(&txq->axq_acq),
txq->stopped);
ath_txq_schedule(sc, txq);
}
}
spin_unlock_bh(&txq->axq_lock);
}

32
drivers/net/wireless/ath/key.c
View File

@ -23,6 +23,14 @@
#define REG_READ (common->ops->read)
#define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg)
#define ENABLE_REGWRITE_BUFFER(_ah) \
if (common->ops->enable_write_buffer) \
common->ops->enable_write_buffer((_ah));
#define REGWRITE_BUFFER_FLUSH(_ah) \
if (common->ops->write_flush) \
common->ops->write_flush((_ah));
#define IEEE80211_WEP_NKID 4 /* number of key ids */
@ -42,6 +50,8 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry)
keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
ENABLE_REGWRITE_BUFFER(ah);
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
@ -66,6 +76,8 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry)
}
REGWRITE_BUFFER_FLUSH(ah);
return true;
}
EXPORT_SYMBOL(ath_hw_keyreset);
@ -104,9 +116,13 @@ static bool ath_hw_keysetmac(struct ath_common *common,
} else {
macLo = macHi = 0;
}
ENABLE_REGWRITE_BUFFER(ah);
REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
REGWRITE_BUFFER_FLUSH(ah);
return true;
}
@ -223,6 +239,8 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
mic4 = get_unaligned_le32(k->kv_txmic + 4);
ENABLE_REGWRITE_BUFFER(ah);
/* Write RX[31:0] and TX[31:16] */
REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
@ -236,6 +254,8 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
AR_KEYTABLE_TYPE_CLR);
REGWRITE_BUFFER_FLUSH(ah);
} else {
/*
* TKIP uses four key cache entries (two for group
@ -258,6 +278,8 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
mic0 = get_unaligned_le32(k->kv_mic + 0);
mic2 = get_unaligned_le32(k->kv_mic + 4);
ENABLE_REGWRITE_BUFFER(ah);
/* Write MIC key[31:0] */
REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
@ -270,8 +292,12 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
AR_KEYTABLE_TYPE_CLR);
REGWRITE_BUFFER_FLUSH(ah);
}
ENABLE_REGWRITE_BUFFER(ah);
/* MAC address registers are reserved for the MIC entry */
REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
@ -283,7 +309,11 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
*/
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
REGWRITE_BUFFER_FLUSH(ah);
} else {
ENABLE_REGWRITE_BUFFER(ah);
/* Write key[47:0] */
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
@ -296,6 +326,8 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
REGWRITE_BUFFER_FLUSH(ah);
/* Write MAC address for the entry */
(void) ath_hw_keysetmac(common, entry, mac);
}

2
drivers/net/wireless/iwlwifi/Makefile
View File

@ -2,7 +2,7 @@
obj-$(CONFIG_IWLAGN) += iwlagn.o
iwlagn-objs := iwl-agn.o iwl-agn-rs.o iwl-agn-led.o
iwlagn-objs += iwl-agn-ucode.o iwl-agn-tx.o
iwlagn-objs += iwl-agn-lib.o iwl-agn-calib.o
iwlagn-objs += iwl-agn-lib.o iwl-agn-calib.o iwl-io.o
iwlagn-objs += iwl-agn-tt.o iwl-agn-sta.o iwl-agn-eeprom.o
iwlagn-objs += iwl-core.o iwl-eeprom.o iwl-hcmd.o iwl-power.o

16
drivers/net/wireless/iwlwifi/iwl-1000.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -141,7 +141,6 @@ static int iwl1000_hw_set_hw_params(struct iwl_priv *priv)
priv->hw_params.max_data_size = IWLAGN_RTC_DATA_SIZE;
priv->hw_params.max_inst_size = IWLAGN_RTC_INST_SIZE;
priv->hw_params.max_bsm_size = 0;
priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
BIT(IEEE80211_BAND_5GHZ);
priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
@ -179,21 +178,16 @@ static struct iwl_lib_ops iwl1000_lib = {
.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
.txq_set_sched = iwlagn_txq_set_sched,
.txq_agg_enable = iwlagn_txq_agg_enable,
.txq_agg_disable = iwlagn_txq_agg_disable,
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
.txq_free_tfd = iwl_hw_txq_free_tfd,
.txq_init = iwl_hw_tx_queue_init,
.rx_handler_setup = iwlagn_rx_handler_setup,
.setup_deferred_work = iwlagn_setup_deferred_work,
.is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
.load_ucode = iwlagn_load_ucode,
.dump_nic_event_log = iwl_dump_nic_event_log,
.dump_nic_error_log = iwl_dump_nic_error_log,
.dump_csr = iwl_dump_csr,
.dump_fh = iwl_dump_fh,
.init_alive_start = iwlagn_init_alive_start,
.alive_notify = iwlagn_alive_notify,
.send_tx_power = iwlagn_send_tx_power,
.update_chain_flags = iwl_update_chain_flags,
.apm_ops = {
@ -215,13 +209,6 @@ static struct iwl_lib_ops iwl1000_lib = {
.calib_version = iwlagn_eeprom_calib_version,
.query_addr = iwlagn_eeprom_query_addr,
},
.isr_ops = {
.isr = iwl_isr_ict,
.free = iwl_free_isr_ict,
.alloc = iwl_alloc_isr_ict,
.reset = iwl_reset_ict,
.disable = iwl_disable_ict,
},
.temp_ops = {
.temperature = iwlagn_temperature,
},
@ -255,7 +242,6 @@ static struct iwl_base_params iwl1000_base_params = {
.eeprom_size = OTP_LOW_IMAGE_SIZE,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
.set_l0s = true,
.use_bsm = false,
.max_ll_items = OTP_MAX_LL_ITEMS_1000,
.shadow_ram_support = false,
.led_compensation = 51,

48
drivers/net/wireless/iwlwifi/iwl-2000.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -147,7 +147,6 @@ static int iwl2000_hw_set_hw_params(struct iwl_priv *priv)
priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
priv->hw_params.max_bsm_size = 0;
priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
BIT(IEEE80211_BAND_5GHZ);
priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
@ -259,8 +258,6 @@ static struct iwl_lib_ops iwl2000_lib = {
.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
.txq_set_sched = iwlagn_txq_set_sched,
.txq_agg_enable = iwlagn_txq_agg_enable,
.txq_agg_disable = iwlagn_txq_agg_disable,
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
.txq_free_tfd = iwl_hw_txq_free_tfd,
.txq_init = iwl_hw_tx_queue_init,
@ -268,13 +265,10 @@ static struct iwl_lib_ops iwl2000_lib = {
.setup_deferred_work = iwlagn_bt_setup_deferred_work,
.cancel_deferred_work = iwlagn_bt_cancel_deferred_work,
.is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
.load_ucode = iwlagn_load_ucode,
.dump_nic_event_log = iwl_dump_nic_event_log,
.dump_nic_error_log = iwl_dump_nic_error_log,
.dump_csr = iwl_dump_csr,
.dump_fh = iwl_dump_fh,
.init_alive_start = iwlagn_init_alive_start,
.alive_notify = iwlagn_alive_notify,
.send_tx_power = iwlagn_send_tx_power,
.update_chain_flags = iwl_update_chain_flags,
.set_channel_switch = iwl2030_hw_channel_switch,
@ -298,13 +292,6 @@ static struct iwl_lib_ops iwl2000_lib = {
.query_addr = iwlagn_eeprom_query_addr,
.update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower,
},
.isr_ops = {
.isr = iwl_isr_ict,
.free = iwl_free_isr_ict,
.alloc = iwl_alloc_isr_ict,
.reset = iwl_reset_ict,
.disable = iwl_disable_ict,
},
.temp_ops = {
.temperature = iwlagn_temperature,
},
@ -362,7 +349,6 @@ static struct iwl_base_params iwl2000_base_params = {
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.pll_cfg_val = 0,
.set_l0s = true,
.use_bsm = false,
.max_ll_items = OTP_MAX_LL_ITEMS_2x00,
.shadow_ram_support = true,
.led_compensation = 51,
@ -386,7 +372,6 @@ static struct iwl_base_params iwl2030_base_params = {
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.pll_cfg_val = 0,
.set_l0s = true,
.use_bsm = false,
.max_ll_items = OTP_MAX_LL_ITEMS_2x00,
.shadow_ram_support = true,
.led_compensation = 57,
@ -471,37 +456,6 @@ struct iwl_cfg iwl2030_2bg_cfg = {
IWL_DEVICE_2030,
};
#define IWL_DEVICE_6035 \
.fw_name_pre = IWL2030_FW_PRE, \
.ucode_api_max = IWL2030_UCODE_API_MAX, \
.ucode_api_min = IWL2030_UCODE_API_MIN, \
.eeprom_ver = EEPROM_6035_EEPROM_VERSION, \
.eeprom_calib_ver = EEPROM_6035_TX_POWER_VERSION, \
.ops = &iwl2030_ops, \
.mod_params = &iwlagn_mod_params, \
.base_params = &iwl2030_base_params, \
.bt_params = &iwl2030_bt_params, \
.need_dc_calib = true, \
.need_temp_offset_calib = true, \
.led_mode = IWL_LED_RF_STATE, \
.adv_pm = true \
struct iwl_cfg iwl6035_2agn_cfg = {
.name = "2000 Series 2x2 AGN/BT",
IWL_DEVICE_6035,
.ht_params = &iwl2000_ht_params,
};
struct iwl_cfg iwl6035_2abg_cfg = {
.name = "2000 Series 2x2 ABG/BT",
IWL_DEVICE_6035,
};
struct iwl_cfg iwl6035_2bg_cfg = {
.name = "2000 Series 2x2 BG/BT",
IWL_DEVICE_6035,
};
#define IWL_DEVICE_200 \
.fw_name_pre = IWL200_FW_PRE, \
.ucode_api_max = IWL200_UCODE_API_MAX, \

4
drivers/net/wireless/iwlwifi/iwl-5000-hw.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

29
drivers/net/wireless/iwlwifi/iwl-5000.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -185,7 +185,6 @@ static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
priv->hw_params.max_data_size = IWLAGN_RTC_DATA_SIZE;
priv->hw_params.max_inst_size = IWLAGN_RTC_INST_SIZE;
priv->hw_params.max_bsm_size = 0;
priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
BIT(IEEE80211_BAND_5GHZ);
priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
@ -231,7 +230,6 @@ static int iwl5150_hw_set_hw_params(struct iwl_priv *priv)
priv->hw_params.max_data_size = IWLAGN_RTC_DATA_SIZE;
priv->hw_params.max_inst_size = IWLAGN_RTC_INST_SIZE;
priv->hw_params.max_bsm_size = 0;
priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
BIT(IEEE80211_BAND_5GHZ);
priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
@ -348,8 +346,6 @@ static struct iwl_lib_ops iwl5000_lib = {
.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
.txq_set_sched = iwlagn_txq_set_sched,
.txq_agg_enable = iwlagn_txq_agg_enable,
.txq_agg_disable = iwlagn_txq_agg_disable,
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
.txq_free_tfd = iwl_hw_txq_free_tfd,
.txq_init = iwl_hw_tx_queue_init,
@ -360,9 +356,6 @@ static struct iwl_lib_ops iwl5000_lib = {
.dump_nic_error_log = iwl_dump_nic_error_log,
.dump_csr = iwl_dump_csr,
.dump_fh = iwl_dump_fh,
.load_ucode = iwlagn_load_ucode,
.init_alive_start = iwlagn_init_alive_start,
.alive_notify = iwlagn_alive_notify,
.send_tx_power = iwlagn_send_tx_power,
.update_chain_flags = iwl_update_chain_flags,
.set_channel_switch = iwl5000_hw_channel_switch,
@ -385,13 +378,6 @@ static struct iwl_lib_ops iwl5000_lib = {
.calib_version = iwlagn_eeprom_calib_version,
.query_addr = iwlagn_eeprom_query_addr,
},
.isr_ops = {
.isr = iwl_isr_ict,
.free = iwl_free_isr_ict,
.alloc = iwl_alloc_isr_ict,
.reset = iwl_reset_ict,
.disable = iwl_disable_ict,
},
.temp_ops = {
.temperature = iwlagn_temperature,
},
@ -416,8 +402,6 @@ static struct iwl_lib_ops iwl5150_lib = {
.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
.txq_set_sched = iwlagn_txq_set_sched,
.txq_agg_enable = iwlagn_txq_agg_enable,
.txq_agg_disable = iwlagn_txq_agg_disable,
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
.txq_free_tfd = iwl_hw_txq_free_tfd,
.txq_init = iwl_hw_tx_queue_init,
@ -427,9 +411,6 @@ static struct iwl_lib_ops iwl5150_lib = {
.dump_nic_event_log = iwl_dump_nic_event_log,
.dump_nic_error_log = iwl_dump_nic_error_log,
.dump_csr = iwl_dump_csr,
.load_ucode = iwlagn_load_ucode,
.init_alive_start = iwlagn_init_alive_start,
.alive_notify = iwlagn_alive_notify,
.send_tx_power = iwlagn_send_tx_power,
.update_chain_flags = iwl_update_chain_flags,
.set_channel_switch = iwl5000_hw_channel_switch,
@ -452,13 +433,6 @@ static struct iwl_lib_ops iwl5150_lib = {
.calib_version = iwlagn_eeprom_calib_version,
.query_addr = iwlagn_eeprom_query_addr,
},
.isr_ops = {
.isr = iwl_isr_ict,
.free = iwl_free_isr_ict,
.alloc = iwl_alloc_isr_ict,
.reset = iwl_reset_ict,
.disable = iwl_disable_ict,
},
.temp_ops = {
.temperature = iwl5150_temperature,
},
@ -500,7 +474,6 @@ static struct iwl_base_params iwl5000_base_params = {
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
.set_l0s = true,
.use_bsm = false,
.led_compensation = 51,
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,

4
drivers/net/wireless/iwlwifi/iwl-6000-hw.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

46
drivers/net/wireless/iwlwifi/iwl-6000.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -176,7 +176,6 @@ static int iwl6000_hw_set_hw_params(struct iwl_priv *priv)
priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
priv->hw_params.max_bsm_size = 0;
priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
BIT(IEEE80211_BAND_5GHZ);
priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
@ -288,21 +287,16 @@ static struct iwl_lib_ops iwl6000_lib = {
.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
.txq_set_sched = iwlagn_txq_set_sched,
.txq_agg_enable = iwlagn_txq_agg_enable,
.txq_agg_disable = iwlagn_txq_agg_disable,
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
.txq_free_tfd = iwl_hw_txq_free_tfd,
.txq_init = iwl_hw_tx_queue_init,
.rx_handler_setup = iwlagn_rx_handler_setup,
.setup_deferred_work = iwlagn_setup_deferred_work,
.is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
.load_ucode = iwlagn_load_ucode,
.dump_nic_event_log = iwl_dump_nic_event_log,
.dump_nic_error_log = iwl_dump_nic_error_log,
.dump_csr = iwl_dump_csr,
.dump_fh = iwl_dump_fh,
.init_alive_start = iwlagn_init_alive_start,
.alive_notify = iwlagn_alive_notify,
.send_tx_power = iwlagn_send_tx_power,
.update_chain_flags = iwl_update_chain_flags,
.set_channel_switch = iwl6000_hw_channel_switch,
@ -326,13 +320,6 @@ static struct iwl_lib_ops iwl6000_lib = {
.query_addr = iwlagn_eeprom_query_addr,
.update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower,
},
.isr_ops = {
.isr = iwl_isr_ict,
.free = iwl_free_isr_ict,
.alloc = iwl_alloc_isr_ict,
.reset = iwl_reset_ict,
.disable = iwl_disable_ict,
},
.temp_ops = {
.temperature = iwlagn_temperature,
},
@ -357,8 +344,6 @@ static struct iwl_lib_ops iwl6030_lib = {
.txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
.txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
.txq_set_sched = iwlagn_txq_set_sched,
.txq_agg_enable = iwlagn_txq_agg_enable,
.txq_agg_disable = iwlagn_txq_agg_disable,
.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
.txq_free_tfd = iwl_hw_txq_free_tfd,
.txq_init = iwl_hw_tx_queue_init,
@ -366,13 +351,10 @@ static struct iwl_lib_ops iwl6030_lib = {
.setup_deferred_work = iwlagn_bt_setup_deferred_work,
.cancel_deferred_work = iwlagn_bt_cancel_deferred_work,
.is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
.load_ucode = iwlagn_load_ucode,
.dump_nic_event_log = iwl_dump_nic_event_log,
.dump_nic_error_log = iwl_dump_nic_error_log,
.dump_csr = iwl_dump_csr,
.dump_fh = iwl_dump_fh,
.init_alive_start = iwlagn_init_alive_start,
.alive_notify = iwlagn_alive_notify,
.send_tx_power = iwlagn_send_tx_power,
.update_chain_flags = iwl_update_chain_flags,
.set_channel_switch = iwl6000_hw_channel_switch,
@ -396,13 +378,6 @@ static struct iwl_lib_ops iwl6030_lib = {
.query_addr = iwlagn_eeprom_query_addr,
.update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower,
},
.isr_ops = {
.isr = iwl_isr_ict,
.free = iwl_free_isr_ict,
.alloc = iwl_alloc_isr_ict,
.reset = iwl_reset_ict,
.disable = iwl_disable_ict,
},
.temp_ops = {
.temperature = iwlagn_temperature,
},
@ -470,7 +445,6 @@ static struct iwl_base_params iwl6000_base_params = {
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.pll_cfg_val = 0,
.set_l0s = true,
.use_bsm = false,
.max_ll_items = OTP_MAX_LL_ITEMS_6x00,
.shadow_ram_support = true,
.led_compensation = 51,
@ -493,7 +467,6 @@ static struct iwl_base_params iwl6050_base_params = {
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.pll_cfg_val = 0,
.set_l0s = true,
.use_bsm = false,
.max_ll_items = OTP_MAX_LL_ITEMS_6x50,
.shadow_ram_support = true,
.led_compensation = 51,
@ -515,7 +488,6 @@ static struct iwl_base_params iwl6000_g2_base_params = {
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.pll_cfg_val = 0,
.set_l0s = true,
.use_bsm = false,
.max_ll_items = OTP_MAX_LL_ITEMS_6x00,
.shadow_ram_support = true,
.led_compensation = 57,
@ -613,6 +585,22 @@ struct iwl_cfg iwl6030_2bg_cfg = {
IWL_DEVICE_6030,
};
struct iwl_cfg iwl6035_2agn_cfg = {
.name = "6035 Series 2x2 AGN/BT",
IWL_DEVICE_6030,
.ht_params = &iwl6000_ht_params,
};
struct iwl_cfg iwl6035_2abg_cfg = {
.name = "6035 Series 2x2 ABG/BT",
IWL_DEVICE_6030,
};
struct iwl_cfg iwl6035_2bg_cfg = {
.name = "6035 Series 2x2 BG/BT",
IWL_DEVICE_6030,
};
struct iwl_cfg iwl1030_bgn_cfg = {
.name = "Intel(R) Centrino(R) Wireless-N 1030 BGN",
IWL_DEVICE_6030,

4
drivers/net/wireless/iwlwifi/iwl-agn-calib.c
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

4
drivers/net/wireless/iwlwifi/iwl-agn-calib.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

52
drivers/net/wireless/iwlwifi/iwl-agn-debugfs.c
View File

@ -1,30 +1,30 @@
/******************************************************************************
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
* USA
*
* The full GNU General Public License is included in this distribution
* in the file called LICENSE.GPL.
*
* Contact Information:
* Intel Linux Wireless <ilw@linux.intel.com>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*****************************************************************************/
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
* USA
*
* The full GNU General Public License is included in this distribution
* in the file called LICENSE.GPL.
*
* Contact Information:
* Intel Linux Wireless <ilw@linux.intel.com>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*****************************************************************************/
#include "iwl-agn.h"
#include "iwl-agn-debugfs.h"

2
drivers/net/wireless/iwlwifi/iwl-agn-debugfs.h
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as

6
drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -103,7 +103,7 @@ int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv)
CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
EEPROM_SEM_TIMEOUT);
if (ret >= 0) {
IWL_DEBUG_IO(priv,
IWL_DEBUG_EEPROM(priv,
"Acquired semaphore after %d tries.\n",
count+1);
return ret;

2
drivers/net/wireless/iwlwifi/iwl-agn-hcmd.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as

4
drivers/net/wireless/iwlwifi/iwl-agn-hw.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

4
drivers/net/wireless/iwlwifi/iwl-agn-ict.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -59,8 +59,6 @@ void iwl_free_isr_ict(struct iwl_priv *priv)
int iwl_alloc_isr_ict(struct iwl_priv *priv)
{
if (priv->cfg->base_params->use_isr_legacy)
return 0;
/* allocate shrared data table */
priv->_agn.ict_tbl_vir =
dma_alloc_coherent(&priv->pci_dev->dev,

2
drivers/net/wireless/iwlwifi/iwl-agn-led.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/iwl-agn-led.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

6
drivers/net/wireless/iwlwifi/iwl-agn-lib.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -652,8 +652,7 @@ int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
if (!priv->cfg->base_params->use_isr_legacy)
rb_timeout = RX_RB_TIMEOUT;
rb_timeout = RX_RB_TIMEOUT;
if (priv->cfg->mod_params->amsdu_size_8K)
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
@ -913,7 +912,6 @@ void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
list_add_tail(&rxb->list, &rxq->rx_free);
rxq->free_count++;
priv->alloc_rxb_page++;
spin_unlock_irqrestore(&rxq->lock, flags);
}

29
drivers/net/wireless/iwlwifi/iwl-agn-rs.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -115,13 +115,18 @@ const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
/* FIXME:RS: ^^ should be INV (legacy) */
};
static inline u8 rs_extract_rate(u32 rate_n_flags)
{
return (u8)(rate_n_flags & RATE_MCS_RATE_MSK);
}
static int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
{
int idx = 0;
/* HT rate format */
if (rate_n_flags & RATE_MCS_HT_MSK) {
idx = (rate_n_flags & 0xff);
idx = rs_extract_rate(rate_n_flags);
if (idx >= IWL_RATE_MIMO3_6M_PLCP)
idx = idx - IWL_RATE_MIMO3_6M_PLCP;
@ -138,7 +143,8 @@ static int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
/* legacy rate format, search for match in table */
} else {
for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
if (iwl_rates[idx].plcp ==
rs_extract_rate(rate_n_flags))
return idx;
}
@ -239,11 +245,6 @@ static const struct iwl_rate_mcs_info iwl_rate_mcs[IWL_RATE_COUNT] = {
#define MCS_INDEX_PER_STREAM (8)
static inline u8 rs_extract_rate(u32 rate_n_flags)
{
return (u8)(rate_n_flags & 0xFF);
}
static void rs_rate_scale_clear_window(struct iwl_rate_scale_data *window)
{
window->data = 0;
@ -2770,16 +2771,13 @@ static void rs_get_rate(void *priv_r, struct ieee80211_sta *sta, void *priv_sta,
static void *rs_alloc_sta(void *priv_rate, struct ieee80211_sta *sta,
gfp_t gfp)
{
struct iwl_lq_sta *lq_sta;
struct iwl_station_priv *sta_priv = (struct iwl_station_priv *) sta->drv_priv;
struct iwl_priv *priv;
priv = (struct iwl_priv *)priv_rate;
IWL_DEBUG_RATE(priv, "create station rate scale window\n");
lq_sta = &sta_priv->lq_sta;
return lq_sta;
return &sta_priv->lq_sta;
}
/*
@ -2912,7 +2910,8 @@ static void rs_fill_link_cmd(struct iwl_priv *priv,
ant_toggle_cnt = 1;
repeat_rate = IWL_NUMBER_TRY;
} else {
repeat_rate = IWL_HT_NUMBER_TRY;
repeat_rate = min(IWL_HT_NUMBER_TRY,
LINK_QUAL_AGG_DISABLE_START_DEF - 1);
}
lq_cmd->general_params.mimo_delimiter =
@ -3257,7 +3256,6 @@ static ssize_t rs_sta_dbgfs_rate_scale_data_read(struct file *file,
{
char buff[120];
int desc = 0;
ssize_t ret;
struct iwl_lq_sta *lq_sta = file->private_data;
struct iwl_priv *priv;
@ -3274,8 +3272,7 @@ static ssize_t rs_sta_dbgfs_rate_scale_data_read(struct file *file,
"Bit Rate= %d Mb/s\n",
iwl_rates[lq_sta->last_txrate_idx].ieee >> 1);
ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc);
return ret;
return simple_read_from_buffer(user_buf, count, ppos, buff, desc);
}
static const struct file_operations rs_sta_dbgfs_rate_scale_data_ops = {

30
drivers/net/wireless/iwlwifi/iwl-agn-rs.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -41,20 +41,6 @@ struct iwl_rate_info {
u8 next_rs_tgg; /* next rate used in TGG rs algo */
};
struct iwl3945_rate_info {
u8 plcp; /* uCode API: IWL_RATE_6M_PLCP, etc. */
u8 ieee; /* MAC header: IWL_RATE_6M_IEEE, etc. */
u8 prev_ieee; /* previous rate in IEEE speeds */
u8 next_ieee; /* next rate in IEEE speeds */
u8 prev_rs; /* previous rate used in rs algo */
u8 next_rs; /* next rate used in rs algo */
u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
u8 next_rs_tgg; /* next rate used in TGG rs algo */
u8 table_rs_index; /* index in rate scale table cmd */
u8 prev_table_rs; /* prev in rate table cmd */
};
/*
* These serve as indexes into
* struct iwl_rate_info iwl_rates[IWL_RATE_COUNT];
@ -75,7 +61,6 @@ enum {
IWL_RATE_60M_INDEX,
IWL_RATE_COUNT, /*FIXME:RS:change to IWL_RATE_INDEX_COUNT,*/
IWL_RATE_COUNT_LEGACY = IWL_RATE_COUNT - 1, /* Excluding 60M */
IWL_RATE_COUNT_3945 = IWL_RATE_COUNT - 1,
IWL_RATE_INVM_INDEX = IWL_RATE_COUNT,
IWL_RATE_INVALID = IWL_RATE_COUNT,
};
@ -213,7 +198,6 @@ enum {
IWL_CCK_BASIC_RATES_MASK)
#define IWL_RATES_MASK ((1 << IWL_RATE_COUNT) - 1)
#define IWL_RATES_MASK_3945 ((1 << IWL_RATE_COUNT_3945) - 1)
#define IWL_INVALID_VALUE -1
@ -453,19 +437,9 @@ static inline u8 first_antenna(u8 mask)
}
/**
* iwl3945_rate_scale_init - Initialize the rate scale table based on assoc info
*
* The specific throughput table used is based on the type of network
* the associated with, including A, B, G, and G w/ TGG protection
*/
extern void iwl3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
/* Initialize station's rate scaling information after adding station */
extern void iwl_rs_rate_init(struct iwl_priv *priv,
struct ieee80211_sta *sta, u8 sta_id);
extern void iwl3945_rs_rate_init(struct iwl_priv *priv,
struct ieee80211_sta *sta, u8 sta_id);
/**
* iwl_rate_control_register - Register the rate control algorithm callbacks
@ -478,7 +452,6 @@ extern void iwl3945_rs_rate_init(struct iwl_priv *priv,
*
*/
extern int iwlagn_rate_control_register(void);
extern int iwl3945_rate_control_register(void);
/**
* iwl_rate_control_unregister - Unregister the rate control callbacks
@ -487,6 +460,5 @@ extern int iwl3945_rate_control_register(void);
* the driver is unloaded.
*/
extern void iwlagn_rate_control_unregister(void);
extern void iwl3945_rate_control_unregister(void);
#endif /* __iwl_agn__rs__ */

2
drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

4
drivers/net/wireless/iwlwifi/iwl-agn-sta.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.
@ -474,7 +474,7 @@ int iwl_remove_dynamic_key(struct iwl_priv *priv,
memset(&priv->stations[sta_id].keyinfo, 0,
sizeof(struct iwl_hw_key));
memset(&priv->stations[sta_id].sta.key, 0,
sizeof(struct iwl4965_keyinfo));
sizeof(struct iwl_keyinfo));
priv->stations[sta_id].sta.key.key_flags =
STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
priv->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET;

2
drivers/net/wireless/iwlwifi/iwl-agn-tt.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

2
drivers/net/wireless/iwlwifi/iwl-agn-tt.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

142
drivers/net/wireless/iwlwifi/iwl-agn-tx.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -222,13 +222,8 @@ void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
}
int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
int tx_fifo, int sta_id, int tid, u16 ssn_idx)
static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id, int tid)
{
unsigned long flags;
u16 ra_tid;
int ret;
if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
(IWLAGN_FIRST_AMPDU_QUEUE +
priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
@ -240,12 +235,33 @@ int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
return -EINVAL;
}
ra_tid = BUILD_RAxTID(sta_id, tid);
/* Modify device's station table to Tx this TID */
ret = iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
if (ret)
return ret;
return iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
}
void iwlagn_txq_agg_queue_setup(struct iwl_priv *priv,
struct ieee80211_sta *sta,
int tid, int frame_limit)
{
int sta_id, tx_fifo, txq_id, ssn_idx;
u16 ra_tid;
unsigned long flags;
struct iwl_tid_data *tid_data;
sta_id = iwl_sta_id(sta);
if (WARN_ON(sta_id == IWL_INVALID_STATION))
return;
if (WARN_ON(tid >= MAX_TID_COUNT))
return;
spin_lock_irqsave(&priv->sta_lock, flags);
tid_data = &priv->stations[sta_id].tid[tid];
ssn_idx = SEQ_TO_SN(tid_data->seq_number);
txq_id = tid_data->agg.txq_id;
tx_fifo = tid_data->agg.tx_fifo;
spin_unlock_irqrestore(&priv->sta_lock, flags);
ra_tid = BUILD_RAxTID(sta_id, tid);
spin_lock_irqsave(&priv->lock, flags);
@ -271,10 +287,10 @@ int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
iwl_write_targ_mem(priv, priv->scd_base_addr +
IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
sizeof(u32),
((SCD_WIN_SIZE <<
((frame_limit <<
IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
((SCD_FRAME_LIMIT <<
((frame_limit <<
IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
@ -284,12 +300,10 @@ int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
u16 ssn_idx, u8 tx_fifo)
static int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
u16 ssn_idx, u8 tx_fifo)
{
if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
(IWLAGN_FIRST_AMPDU_QUEUE +
@ -1034,11 +1048,11 @@ int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
tid_data = &priv->stations[sta_id].tid[tid];
*ssn = SEQ_TO_SN(tid_data->seq_number);
tid_data->agg.txq_id = txq_id;
tid_data->agg.tx_fifo = tx_fifo;
iwl_set_swq_id(&priv->txq[txq_id], get_ac_from_tid(tid), txq_id);
spin_unlock_irqrestore(&priv->sta_lock, flags);
ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
sta_id, tid, *ssn);
ret = iwlagn_txq_agg_enable(priv, txq_id, sta_id, tid);
if (ret)
return ret;
@ -1125,8 +1139,7 @@ int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
* to deactivate the uCode queue, just return "success" to allow
* mac80211 to clean up it own data.
*/
priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
tx_fifo_id);
iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo_id);
spin_unlock_irqrestore(&priv->lock, flags);
ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
@ -1155,8 +1168,7 @@ int iwlagn_txq_check_empty(struct iwl_priv *priv,
u16 ssn = SEQ_TO_SN(tid_data->seq_number);
int tx_fifo = get_fifo_from_tid(ctx, tid);
IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
ssn, tx_fifo);
iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo);
tid_data->agg.state = IWL_AGG_OFF;
ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
}
@ -1251,11 +1263,11 @@ static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
struct iwl_compressed_ba_resp *ba_resp)
{
int i, sh, ack;
int sh;
u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
int successes = 0;
struct ieee80211_tx_info *info;
u64 bitmap, sent_bitmap;
if (unlikely(!agg->wait_for_ba)) {
if (unlikely(ba_resp->bitmap))
@ -1269,70 +1281,42 @@ static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
/* Calculate shift to align block-ack bits with our Tx window bits */
sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
if (sh < 0) /* tbw something is wrong with indices */
if (sh < 0)
sh += 0x100;
if (agg->frame_count > (64 - sh)) {
IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
return -1;
}
if (!priv->cfg->base_params->no_agg_framecnt_info && ba_resp->txed) {
/*
* Check for success or failure according to the
* transmitted bitmap and block-ack bitmap
*/
bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
sent_bitmap = bitmap & agg->bitmap;
/* Sanity check values reported by uCode */
if (ba_resp->txed_2_done > ba_resp->txed) {
IWL_DEBUG_TX_REPLY(priv,
"bogus sent(%d) and ack(%d) count\n",
ba_resp->txed, ba_resp->txed_2_done);
/*
* sent and ack information provided by uCode
* use it instead of figure out ourself
* set txed_2_done = txed,
* so it won't impact rate scale
*/
if (ba_resp->txed_2_done > ba_resp->txed) {
IWL_DEBUG_TX_REPLY(priv,
"bogus sent(%d) and ack(%d) count\n",
ba_resp->txed, ba_resp->txed_2_done);
/*
* set txed_2_done = txed,
* so it won't impact rate scale
*/
ba_resp->txed = ba_resp->txed_2_done;
}
IWL_DEBUG_HT(priv, "agg frames sent:%d, acked:%d\n",
ba_resp->txed, ba_resp->txed_2_done);
} else {
u64 bitmap, sent_bitmap;
ba_resp->txed = ba_resp->txed_2_done;
}
IWL_DEBUG_HT(priv, "agg frames sent:%d, acked:%d\n",
ba_resp->txed, ba_resp->txed_2_done);
/* don't use 64-bit values for now */
bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
/* check for success or failure according to the
* transmitted bitmap and block-ack bitmap */
sent_bitmap = bitmap & agg->bitmap;
/* For each frame attempted in aggregation,
* update driver's record of tx frame's status. */
i = 0;
while (sent_bitmap) {
ack = sent_bitmap & 1ULL;
successes += ack;
IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
ack ? "ACK" : "NACK", i,
(agg->start_idx + i) & 0xff,
agg->start_idx + i);
sent_bitmap >>= 1;
++i;
}
IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n",
(unsigned long long)bitmap);
/* Find the first ACKed frame to store the TX status */
while (sent_bitmap && !(sent_bitmap & 1)) {
agg->start_idx = (agg->start_idx + 1) & 0xff;
sent_bitmap >>= 1;
}
info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb);
memset(&info->status, 0, sizeof(info->status));
info->flags |= IEEE80211_TX_STAT_ACK;
info->flags |= IEEE80211_TX_STAT_AMPDU;
if (!priv->cfg->base_params->no_agg_framecnt_info && ba_resp->txed) {
info->status.ampdu_ack_len = ba_resp->txed_2_done;
info->status.ampdu_len = ba_resp->txed;
} else {
info->status.ampdu_ack_len = successes;
info->status.ampdu_len = agg->frame_count;
}
info->status.ampdu_ack_len = ba_resp->txed_2_done;
info->status.ampdu_len = ba_resp->txed;
iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
return 0;

122
drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -311,14 +311,14 @@ void iwlagn_init_alive_start(struct iwl_priv *priv)
/* initialize uCode was loaded... verify inst image.
* This is a paranoid check, because we would not have gotten the
* "initialize" alive if code weren't properly loaded. */
if (iwl_verify_ucode(priv)) {
if (iwl_verify_ucode(priv, &priv->ucode_init)) {
/* Runtime instruction load was bad;
* take it all the way back down so we can try again */
IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
goto restart;
}
ret = priv->cfg->ops->lib->alive_notify(priv);
ret = iwlagn_alive_notify(priv);
if (ret) {
IWL_WARN(priv,
"Could not complete ALIVE transition: %d\n", ret);
@ -432,6 +432,7 @@ int iwlagn_alive_notify(struct iwl_priv *priv)
unsigned long flags;
int i, chan;
u32 reg_val;
int ret;
spin_lock_irqsave(&priv->lock, flags);
@ -527,12 +528,15 @@ int iwlagn_alive_notify(struct iwl_priv *priv)
iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
iwlagn_send_wimax_coex(priv);
ret = iwlagn_send_wimax_coex(priv);
if (ret)
return ret;
iwlagn_set_Xtal_calib(priv);
iwl_send_calib_results(priv);
ret = iwlagn_set_Xtal_calib(priv);
if (ret)
return ret;
return 0;
return iwl_send_calib_results(priv);
}
@ -541,11 +545,12 @@ int iwlagn_alive_notify(struct iwl_priv *priv)
* using sample data 100 bytes apart. If these sample points are good,
* it's a pretty good bet that everything between them is good, too.
*/
static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
static int iwlcore_verify_inst_sparse(struct iwl_priv *priv,
struct fw_desc *fw_desc)
{
__le32 *image = (__le32 *)fw_desc->v_addr;
u32 len = fw_desc->len;
u32 val;
int ret = 0;
u32 errcnt = 0;
u32 i;
IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
@ -556,104 +561,55 @@ static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
* if IWL_DL_IO is set */
iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
i + IWLAGN_RTC_INST_LOWER_BOUND);
val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
if (val != le32_to_cpu(*image)) {
ret = -EIO;
errcnt++;
if (errcnt >= 3)
break;
}
val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
if (val != le32_to_cpu(*image))
return -EIO;
}
return ret;
return 0;
}
/**
* iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
* looking at all data.
*/
static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
u32 len)
static void iwl_print_mismatch_inst(struct iwl_priv *priv,
struct fw_desc *fw_desc)
{
__le32 *image = (__le32 *)fw_desc->v_addr;
u32 len = fw_desc->len;
u32 val;
u32 save_len = len;
int ret = 0;
u32 errcnt;
u32 offs;
int errors = 0;
IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
IWLAGN_RTC_INST_LOWER_BOUND);
errcnt = 0;
for (; len > 0; len -= sizeof(u32), image++) {
for (offs = 0;
offs < len && errors < 20;
offs += sizeof(u32), image++) {
/* read data comes through single port, auto-incr addr */
/* NOTE: Use the debugless read so we don't flood kernel log
* if IWL_DL_IO is set */
val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
if (val != le32_to_cpu(*image)) {
IWL_ERR(priv, "uCode INST section is invalid at "
"offset 0x%x, is 0x%x, s/b 0x%x\n",
save_len - len, val, le32_to_cpu(*image));
ret = -EIO;
errcnt++;
if (errcnt >= 20)
break;
IWL_ERR(priv, "uCode INST section at "
"offset 0x%x, is 0x%x, s/b 0x%x\n",
offs, val, le32_to_cpu(*image));
errors++;
}
}
if (!errcnt)
IWL_DEBUG_INFO(priv,
"ucode image in INSTRUCTION memory is good\n");
return ret;
}
/**
* iwl_verify_ucode - determine which instruction image is in SRAM,
* and verify its contents
*/
int iwl_verify_ucode(struct iwl_priv *priv)
int iwl_verify_ucode(struct iwl_priv *priv, struct fw_desc *fw_desc)
{
__le32 *image;
u32 len;
int ret;
/* Try bootstrap */
image = (__le32 *)priv->ucode_boot.v_addr;
len = priv->ucode_boot.len;
ret = iwlcore_verify_inst_sparse(priv, image, len);
if (!ret) {
IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
if (!iwlcore_verify_inst_sparse(priv, fw_desc)) {
IWL_DEBUG_INFO(priv, "uCode is good in inst SRAM\n");
return 0;
}
/* Try initialize */
image = (__le32 *)priv->ucode_init.v_addr;
len = priv->ucode_init.len;
ret = iwlcore_verify_inst_sparse(priv, image, len);
if (!ret) {
IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
return 0;
}
IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
/* Try runtime/protocol */
image = (__le32 *)priv->ucode_code.v_addr;
len = priv->ucode_code.len;
ret = iwlcore_verify_inst_sparse(priv, image, len);
if (!ret) {
IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
return 0;
}
IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
/* Since nothing seems to match, show first several data entries in
* instruction SRAM, so maybe visual inspection will give a clue.
* Selection of bootstrap image (vs. other images) is arbitrary. */
image = (__le32 *)priv->ucode_boot.v_addr;
len = priv->ucode_boot.len;
ret = iwl_verify_inst_full(priv, image, len);
return ret;
iwl_print_mismatch_inst(priv, fw_desc);
return -EIO;
}

531
drivers/net/wireless/iwlwifi/iwl-agn.c
View File

File diff suppressed because it is too large Load Diff

45
drivers/net/wireless/iwlwifi/iwl-agn.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -66,7 +66,6 @@
#include "iwl-dev.h"
/* configuration for the _agn devices */
extern struct iwl_cfg iwl4965_agn_cfg;
extern struct iwl_cfg iwl5300_agn_cfg;
extern struct iwl_cfg iwl5100_agn_cfg;
extern struct iwl_cfg iwl5350_agn_cfg;
@ -114,7 +113,6 @@ extern struct iwl_hcmd_ops iwlagn_bt_hcmd;
extern struct iwl_hcmd_utils_ops iwlagn_hcmd_utils;
extern struct ieee80211_ops iwlagn_hw_ops;
extern struct ieee80211_ops iwl4965_hw_ops;
int iwl_reset_ict(struct iwl_priv *priv);
void iwl_disable_ict(struct iwl_priv *priv);
@ -133,10 +131,6 @@ void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
u16 byte_cnt);
void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
struct iwl_tx_queue *txq);
int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
int tx_fifo, int sta_id, int tid, u16 ssn_idx);
int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
u16 ssn_idx, u8 tx_fifo);
void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask);
void iwl_free_tfds_in_queue(struct iwl_priv *priv,
int sta_id, int tid, int freed);
@ -158,7 +152,7 @@ void iwlagn_rx_calib_complete(struct iwl_priv *priv,
struct iwl_rx_mem_buffer *rxb);
void iwlagn_init_alive_start(struct iwl_priv *priv);
int iwlagn_alive_notify(struct iwl_priv *priv);
int iwl_verify_ucode(struct iwl_priv *priv);
int iwl_verify_ucode(struct iwl_priv *priv, struct fw_desc *fw_desc);
void iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type);
void iwlagn_send_prio_tbl(struct iwl_priv *priv);
@ -206,6 +200,9 @@ int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, u16 tid, u16 *ssn);
int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, u16 tid);
void iwlagn_txq_agg_queue_setup(struct iwl_priv *priv,
struct ieee80211_sta *sta,
int tid, int frame_limit);
int iwlagn_txq_check_empty(struct iwl_priv *priv,
int sta_id, u8 tid, int txq_id);
void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
@ -311,7 +308,7 @@ static inline u32 iwl_ant_idx_to_flags(u8 ant_idx)
static inline u8 iwl_hw_get_rate(__le32 rate_n_flags)
{
return le32_to_cpu(rate_n_flags) & 0xFF;
return le32_to_cpu(rate_n_flags) & RATE_MCS_RATE_MSK;
}
static inline __le32 iwl_hw_set_rate_n_flags(u8 rate, u32 flags)
@ -340,32 +337,4 @@ void __releases(wait_entry)
iwlagn_remove_notification(struct iwl_priv *priv,
struct iwl_notification_wait *wait_entry);
/* mac80211 handlers (for 4965) */
void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
int iwlagn_mac_start(struct ieee80211_hw *hw);
void iwlagn_mac_stop(struct ieee80211_hw *hw);
void iwlagn_configure_filter(struct ieee80211_hw *hw,
unsigned int changed_flags,
unsigned int *total_flags,
u64 multicast);
int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
struct ieee80211_vif *vif, struct ieee80211_sta *sta,
struct ieee80211_key_conf *key);
void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct ieee80211_key_conf *keyconf,
struct ieee80211_sta *sta,
u32 iv32, u16 *phase1key);
int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
enum ieee80211_ampdu_mlme_action action,
struct ieee80211_sta *sta, u16 tid, u16 *ssn,
u8 buf_size);
int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct ieee80211_sta *sta);
void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
struct ieee80211_channel_switch *ch_switch);
void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop);
#endif /* __iwl_agn_h__ */

647
drivers/net/wireless/iwlwifi/iwl-commands.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -103,9 +103,7 @@ enum {
REPLY_WEPKEY = 0x20,
/* RX, TX, LEDs */
REPLY_3945_RX = 0x1b, /* 3945 only */
REPLY_TX = 0x1c,
REPLY_RATE_SCALE = 0x47, /* 3945 only */
REPLY_LEDS_CMD = 0x48,
REPLY_TX_LINK_QUALITY_CMD = 0x4e, /* for 4965 and up */
@ -229,7 +227,7 @@ struct iwl_cmd_header {
* There is one exception: uCode sets bit 15 when it originates
* the response/notification, i.e. when the response/notification
* is not a direct response to a command sent by the driver. For
* example, uCode issues REPLY_3945_RX when it sends a received frame
* example, uCode issues REPLY_RX when it sends a received frame
* to the driver; it is not a direct response to any driver command.
*
* The Linux driver uses the following format:
@ -248,36 +246,6 @@ struct iwl_cmd_header {
} __packed;
/**
* struct iwl3945_tx_power
*
* Used in REPLY_TX_PWR_TABLE_CMD, REPLY_SCAN_CMD, REPLY_CHANNEL_SWITCH
*
* Each entry contains two values:
* 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
* linear value that multiplies the output of the digital signal processor,
* before being sent to the analog radio.
* 2) Radio gain. This sets the analog gain of the radio Tx path.
* It is a coarser setting, and behaves in a logarithmic (dB) fashion.
*
* Driver obtains values from struct iwl3945_tx_power power_gain_table[][].
*/
struct iwl3945_tx_power {
u8 tx_gain; /* gain for analog radio */
u8 dsp_atten; /* gain for DSP */
} __packed;
/**
* struct iwl3945_power_per_rate
*
* Used in REPLY_TX_PWR_TABLE_CMD, REPLY_CHANNEL_SWITCH
*/
struct iwl3945_power_per_rate {
u8 rate; /* plcp */
struct iwl3945_tx_power tpc;
u8 reserved;
} __packed;
/**
* iwlagn rate_n_flags bit fields
*
@ -324,6 +292,8 @@ struct iwl3945_power_per_rate {
#define RATE_MCS_SPATIAL_MSK 0x18
#define RATE_MCS_HT_DUP_POS 5
#define RATE_MCS_HT_DUP_MSK 0x20
/* Both legacy and HT use bits 7:0 as the CCK/OFDM rate or HT MCS */
#define RATE_MCS_RATE_MSK 0xff
/* Bit 8: (1) HT format, (0) legacy format in bits 7:0 */
#define RATE_MCS_FLAGS_POS 8
@ -374,30 +344,6 @@ struct iwl3945_power_per_rate {
#define IWL_PWR_NUM_HT_OFDM_ENTRIES 24
#define IWL_PWR_CCK_ENTRIES 2
/**
* union iwl4965_tx_power_dual_stream
*
* Host format used for REPLY_TX_PWR_TABLE_CMD, REPLY_CHANNEL_SWITCH
* Use __le32 version (struct tx_power_dual_stream) when building command.
*
* Driver provides radio gain and DSP attenuation settings to device in pairs,
* one value for each transmitter chain. The first value is for transmitter A,
* second for transmitter B.
*
* For SISO bit rates, both values in a pair should be identical.
* For MIMO rates, one value may be different from the other,
* in order to balance the Tx output between the two transmitters.
*
* See more details in doc for TXPOWER in iwl-4965-hw.h.
*/
union iwl4965_tx_power_dual_stream {
struct {
u8 radio_tx_gain[2];
u8 dsp_predis_atten[2];
} s;
u32 dw;
};
/**
* struct tx_power_dual_stream
*
@ -409,15 +355,6 @@ struct tx_power_dual_stream {
__le32 dw;
} __packed;
/**
* struct iwl4965_tx_power_db
*
* Entire table within REPLY_TX_PWR_TABLE_CMD, REPLY_CHANNEL_SWITCH
*/
struct iwl4965_tx_power_db {
struct tx_power_dual_stream power_tbl[POWER_TABLE_NUM_ENTRIES];
} __packed;
/**
* Command REPLY_TX_POWER_DBM_CMD = 0x98
* struct iwlagn_tx_power_dbm_cmd
@ -451,54 +388,6 @@ struct iwl_tx_ant_config_cmd {
#define UCODE_VALID_OK cpu_to_le32(0x1)
#define INITIALIZE_SUBTYPE (9)
/*
* ("Initialize") REPLY_ALIVE = 0x1 (response only, not a command)
*
* uCode issues this "initialize alive" notification once the initialization
* uCode image has completed its work, and is ready to load the runtime image.
* This is the *first* "alive" notification that the driver will receive after
* rebooting uCode; the "initialize" alive is indicated by subtype field == 9.
*
* See comments documenting "BSM" (bootstrap state machine).
*
* For 4965, this notification contains important calibration data for
* calculating txpower settings:
*
* 1) Power supply voltage indication. The voltage sensor outputs higher
* values for lower voltage, and vice verse.
*
* 2) Temperature measurement parameters, for each of two channel widths
* (20 MHz and 40 MHz) supported by the radios. Temperature sensing
* is done via one of the receiver chains, and channel width influences
* the results.
*
* 3) Tx gain compensation to balance 4965's 2 Tx chains for MIMO operation,
* for each of 5 frequency ranges.
*/
struct iwl_init_alive_resp {
u8 ucode_minor;
u8 ucode_major;
__le16 reserved1;
u8 sw_rev[8];
u8 ver_type;
u8 ver_subtype; /* "9" for initialize alive */
__le16 reserved2;
__le32 log_event_table_ptr;
__le32 error_event_table_ptr;
__le32 timestamp;
__le32 is_valid;
/* calibration values from "initialize" uCode */
__le32 voltage; /* signed, higher value is lower voltage */
__le32 therm_r1[2]; /* signed, 1st for normal, 2nd for HT40 */
__le32 therm_r2[2]; /* signed */
__le32 therm_r3[2]; /* signed */
__le32 therm_r4[2]; /* signed */
__le32 tx_atten[5][2]; /* signed MIMO gain comp, 5 freq groups,
* 2 Tx chains */
} __packed;
/**
* REPLY_ALIVE = 0x1 (response only, not a command)
*
@ -722,46 +611,6 @@ enum {
* regardless of whether RXON_FILTER_ASSOC_MSK is set.
*/
struct iwl3945_rxon_cmd {
u8 node_addr[6];
__le16 reserved1;
u8 bssid_addr[6];
__le16 reserved2;
u8 wlap_bssid_addr[6];
__le16 reserved3;
u8 dev_type;
u8 air_propagation;
__le16 reserved4;
u8 ofdm_basic_rates;
u8 cck_basic_rates;
__le16 assoc_id;
__le32 flags;
__le32 filter_flags;
__le16 channel;
__le16 reserved5;
} __packed;
struct iwl4965_rxon_cmd {
u8 node_addr[6];
__le16 reserved1;
u8 bssid_addr[6];
__le16 reserved2;
u8 wlap_bssid_addr[6];
__le16 reserved3;
u8 dev_type;
u8 air_propagation;
__le16 rx_chain;
u8 ofdm_basic_rates;
u8 cck_basic_rates;
__le16 assoc_id;
__le32 flags;
__le32 filter_flags;
__le16 channel;
u8 ofdm_ht_single_stream_basic_rates;
u8 ofdm_ht_dual_stream_basic_rates;
} __packed;
/* 5000 HW just extend this command */
struct iwl_rxon_cmd {
u8 node_addr[6];
__le16 reserved1;
@ -789,25 +638,6 @@ struct iwl_rxon_cmd {
/*
* REPLY_RXON_ASSOC = 0x11 (command, has simple generic response)
*/
struct iwl3945_rxon_assoc_cmd {
__le32 flags;
__le32 filter_flags;
u8 ofdm_basic_rates;
u8 cck_basic_rates;
__le16 reserved;
} __packed;
struct iwl4965_rxon_assoc_cmd {
__le32 flags;
__le32 filter_flags;
u8 ofdm_basic_rates;
u8 cck_basic_rates;
u8 ofdm_ht_single_stream_basic_rates;
u8 ofdm_ht_dual_stream_basic_rates;
__le16 rx_chain_select_flags;
__le16 reserved;
} __packed;
struct iwl5000_rxon_assoc_cmd {
__le32 flags;
__le32 filter_flags;
@ -843,26 +673,6 @@ struct iwl_rxon_time_cmd {
/*
* REPLY_CHANNEL_SWITCH = 0x72 (command, has simple generic response)
*/
struct iwl3945_channel_switch_cmd {
u8 band;
u8 expect_beacon;
__le16 channel;
__le32 rxon_flags;
__le32 rxon_filter_flags;
__le32 switch_time;
struct iwl3945_power_per_rate power[IWL_MAX_RATES];
} __packed;
struct iwl4965_channel_switch_cmd {
u8 band;
u8 expect_beacon;
__le16 channel;
__le32 rxon_flags;
__le32 rxon_filter_flags;
__le32 switch_time;
struct iwl4965_tx_power_db tx_power;
} __packed;
/**
* struct iwl5000_channel_switch_cmd
* @band: 0- 5.2GHz, 1- 2.4GHz
@ -976,15 +786,10 @@ struct iwl_qosparam_cmd {
#define IWL_AP_ID 0
#define IWL_AP_ID_PAN 1
#define IWL_STA_ID 2
#define IWL3945_BROADCAST_ID 24
#define IWL3945_STATION_COUNT 25
#define IWL4965_BROADCAST_ID 31
#define IWL4965_STATION_COUNT 32
#define IWLAGN_PAN_BCAST_ID 14
#define IWLAGN_BROADCAST_ID 15
#define IWLAGN_STATION_COUNT 16
#define IWL_STATION_COUNT 32 /* MAX(3945,4965)*/
#define IWL_INVALID_STATION 255
#define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
@ -1032,16 +837,6 @@ struct iwl_qosparam_cmd {
* combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
struct iwl4965_keyinfo {
__le16 key_flags;
u8 tkip_rx_tsc_byte2; /* TSC[2] for key mix ph1 detection */
u8 reserved1;
__le16 tkip_rx_ttak[5]; /* 10-byte unicast TKIP TTAK */
u8 key_offset;
u8 reserved2;
u8 key[16]; /* 16-byte unicast decryption key */
} __packed;
/* agn */
struct iwl_keyinfo {
__le16 key_flags;
@ -1083,7 +878,6 @@ struct sta_id_modify {
* with info on security keys, aggregation parameters, and Tx rates for
* initial Tx attempt and any retries (agn devices uses
* REPLY_TX_LINK_QUALITY_CMD,
* 3945 uses REPLY_RATE_SCALE to set up rate tables).
*
* REPLY_ADD_STA sets up the table entry for one station, either creating
* a new entry, or modifying a pre-existing one.
@ -1103,72 +897,6 @@ struct sta_id_modify {
* entries for all STAs in network, starting with index IWL_STA_ID.
*/
struct iwl3945_addsta_cmd {
u8 mode; /* 1: modify existing, 0: add new station */
u8 reserved[3];
struct sta_id_modify sta;
struct iwl4965_keyinfo key;
__le32 station_flags; /* STA_FLG_* */
__le32 station_flags_msk; /* STA_FLG_* */
/* bit field to disable (1) or enable (0) Tx for Traffic ID (TID)
* corresponding to bit (e.g. bit 5 controls TID 5).
* Set modify_mask bit STA_MODIFY_TID_DISABLE_TX to use this field. */
__le16 tid_disable_tx;
__le16 rate_n_flags;
/* TID for which to add block-ack support.
* Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
u8 add_immediate_ba_tid;
/* TID for which to remove block-ack support.
* Set modify_mask bit STA_MODIFY_DELBA_TID_MSK to use this field. */
u8 remove_immediate_ba_tid;
/* Starting Sequence Number for added block-ack support.
* Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
__le16 add_immediate_ba_ssn;
} __packed;
struct iwl4965_addsta_cmd {
u8 mode; /* 1: modify existing, 0: add new station */
u8 reserved[3];
struct sta_id_modify sta;
struct iwl4965_keyinfo key;
__le32 station_flags; /* STA_FLG_* */
__le32 station_flags_msk; /* STA_FLG_* */
/* bit field to disable (1) or enable (0) Tx for Traffic ID (TID)
* corresponding to bit (e.g. bit 5 controls TID 5).
* Set modify_mask bit STA_MODIFY_TID_DISABLE_TX to use this field. */
__le16 tid_disable_tx;
__le16 reserved1;
/* TID for which to add block-ack support.
* Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
u8 add_immediate_ba_tid;
/* TID for which to remove block-ack support.
* Set modify_mask bit STA_MODIFY_DELBA_TID_MSK to use this field. */
u8 remove_immediate_ba_tid;
/* Starting Sequence Number for added block-ack support.
* Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
__le16 add_immediate_ba_ssn;
/*
* Number of packets OK to transmit to station even though
* it is asleep -- used to synchronise PS-poll and u-APSD
* responses while ucode keeps track of STA sleep state.
*/
__le16 sleep_tx_count;
__le16 reserved2;
} __packed;
/* agn */
struct iwl_addsta_cmd {
u8 mode; /* 1: modify existing, 0: add new station */
u8 reserved[3];
@ -1337,62 +1065,6 @@ struct iwl_wep_cmd {
#define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800)
struct iwl3945_rx_frame_stats {
u8 phy_count;
u8 id;
u8 rssi;
u8 agc;
__le16 sig_avg;
__le16 noise_diff;
u8 payload[0];
} __packed;
struct iwl3945_rx_frame_hdr {
__le16 channel;
__le16 phy_flags;
u8 reserved1;
u8 rate;
__le16 len;
u8 payload[0];
} __packed;
struct iwl3945_rx_frame_end {
__le32 status;
__le64 timestamp;
__le32 beacon_timestamp;
} __packed;
/*
* REPLY_3945_RX = 0x1b (response only, not a command)
*
* NOTE: DO NOT dereference from casts to this structure
* It is provided only for calculating minimum data set size.
* The actual offsets of the hdr and end are dynamic based on
* stats.phy_count
*/
struct iwl3945_rx_frame {
struct iwl3945_rx_frame_stats stats;
struct iwl3945_rx_frame_hdr hdr;
struct iwl3945_rx_frame_end end;
} __packed;
#define IWL39_RX_FRAME_SIZE (4 + sizeof(struct iwl3945_rx_frame))
/* Fixed (non-configurable) rx data from phy */
#define IWL49_RX_RES_PHY_CNT 14
#define IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET (4)
#define IWL49_RX_PHY_FLAGS_ANTENNAE_MASK (0x70)
#define IWL49_AGC_DB_MASK (0x3f80) /* MASK(7,13) */
#define IWL49_AGC_DB_POS (7)
struct iwl4965_rx_non_cfg_phy {
__le16 ant_selection; /* ant A bit 4, ant B bit 5, ant C bit 6 */
__le16 agc_info; /* agc code 0:6, agc dB 7:13, reserved 14:15 */
u8 rssi_info[6]; /* we use even entries, 0/2/4 for A/B/C rssi */
u8 pad[0];
} __packed;
#define IWLAGN_RX_RES_PHY_CNT 8
#define IWLAGN_RX_RES_AGC_IDX 1
#define IWLAGN_RX_RES_RSSI_AB_IDX 2
@ -1576,80 +1248,6 @@ struct iwl_rx_mpdu_res_start {
* REPLY_TX = 0x1c (command)
*/
struct iwl3945_tx_cmd {
/*
* MPDU byte count:
* MAC header (24/26/30/32 bytes) + 2 bytes pad if 26/30 header size,
* + 8 byte IV for CCM or TKIP (not used for WEP)
* + Data payload
* + 8-byte MIC (not used for CCM/WEP)
* NOTE: Does not include Tx command bytes, post-MAC pad bytes,
* MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.i
* Range: 14-2342 bytes.
*/
__le16 len;
/*
* MPDU or MSDU byte count for next frame.
* Used for fragmentation and bursting, but not 11n aggregation.
* Same as "len", but for next frame. Set to 0 if not applicable.
*/
__le16 next_frame_len;
__le32 tx_flags; /* TX_CMD_FLG_* */
u8 rate;
/* Index of recipient station in uCode's station table */
u8 sta_id;
u8 tid_tspec;
u8 sec_ctl;
u8 key[16];
union {
u8 byte[8];
__le16 word[4];
__le32 dw[2];
} tkip_mic;
__le32 next_frame_info;
union {
__le32 life_time;
__le32 attempt;
} stop_time;
u8 supp_rates[2];
u8 rts_retry_limit; /*byte 50 */
u8 data_retry_limit; /*byte 51 */
union {
__le16 pm_frame_timeout;
__le16 attempt_duration;
} timeout;
/*
* Duration of EDCA burst Tx Opportunity, in 32-usec units.
* Set this if txop time is not specified by HCCA protocol (e.g. by AP).
*/
__le16 driver_txop;
/*
* MAC header goes here, followed by 2 bytes padding if MAC header
* length is 26 or 30 bytes, followed by payload data
*/
u8 payload[0];
struct ieee80211_hdr hdr[0];
} __packed;
/*
* REPLY_TX = 0x1c (response)
*/
struct iwl3945_tx_resp {
u8 failure_rts;
u8 failure_frame;
u8 bt_kill_count;
u8 rate;
__le32 wireless_media_time;
__le32 status; /* TX status */
} __packed;
/*
* 4965 uCode updates these Tx attempt count values in host DRAM.
* Used for managing Tx retries when expecting block-acks.
@ -1740,54 +1338,6 @@ struct iwl_tx_cmd {
struct ieee80211_hdr hdr[0];
} __packed;
/* TX command response is sent after *3945* transmission attempts.
*
* NOTES:
*
* TX_STATUS_FAIL_NEXT_FRAG
*
* If the fragment flag in the MAC header for the frame being transmitted
* is set and there is insufficient time to transmit the next frame, the
* TX status will be returned with 'TX_STATUS_FAIL_NEXT_FRAG'.
*
* TX_STATUS_FIFO_UNDERRUN
*
* Indicates the host did not provide bytes to the FIFO fast enough while
* a TX was in progress.
*
* TX_STATUS_FAIL_MGMNT_ABORT
*
* This status is only possible if the ABORT ON MGMT RX parameter was
* set to true with the TX command.
*
* If the MSB of the status parameter is set then an abort sequence is
* required. This sequence consists of the host activating the TX Abort
* control line, and then waiting for the TX Abort command response. This
* indicates that a the device is no longer in a transmit state, and that the
* command FIFO has been cleared. The host must then deactivate the TX Abort
* control line. Receiving is still allowed in this case.
*/
enum {
TX_3945_STATUS_SUCCESS = 0x01,
TX_3945_STATUS_DIRECT_DONE = 0x02,
TX_3945_STATUS_FAIL_SHORT_LIMIT = 0x82,
TX_3945_STATUS_FAIL_LONG_LIMIT = 0x83,
TX_3945_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
TX_3945_STATUS_FAIL_MGMNT_ABORT = 0x85,
TX_3945_STATUS_FAIL_NEXT_FRAG = 0x86,
TX_3945_STATUS_FAIL_LIFE_EXPIRE = 0x87,
TX_3945_STATUS_FAIL_DEST_PS = 0x88,
TX_3945_STATUS_FAIL_ABORTED = 0x89,
TX_3945_STATUS_FAIL_BT_RETRY = 0x8a,
TX_3945_STATUS_FAIL_STA_INVALID = 0x8b,
TX_3945_STATUS_FAIL_FRAG_DROPPED = 0x8c,
TX_3945_STATUS_FAIL_TID_DISABLE = 0x8d,
TX_3945_STATUS_FAIL_FRAME_FLUSHED = 0x8e,
TX_3945_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
TX_3945_STATUS_FAIL_TX_LOCKED = 0x90,
TX_3945_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
};
/*
* TX command response is sent after *agn* transmission attempts.
*
@ -1905,43 +1455,6 @@ struct agg_tx_status {
__le16 sequence;
} __packed;
struct iwl4965_tx_resp {
u8 frame_count; /* 1 no aggregation, >1 aggregation */
u8 bt_kill_count; /* # blocked by bluetooth (unused for agg) */
u8 failure_rts; /* # failures due to unsuccessful RTS */
u8 failure_frame; /* # failures due to no ACK (unused for agg) */
/* For non-agg: Rate at which frame was successful.
* For agg: Rate at which all frames were transmitted. */
__le32 rate_n_flags; /* RATE_MCS_* */
/* For non-agg: RTS + CTS + frame tx attempts time + ACK.
* For agg: RTS + CTS + aggregation tx time + block-ack time. */
__le16 wireless_media_time; /* uSecs */
__le16 reserved;
__le32 pa_power1; /* RF power amplifier measurement (not used) */
__le32 pa_power2;
/*
* For non-agg: frame status TX_STATUS_*
* For agg: status of 1st frame, AGG_TX_STATE_*; other frame status
* fields follow this one, up to frame_count.
* Bit fields:
* 11- 0: AGG_TX_STATE_* status code
* 15-12: Retry count for 1st frame in aggregation (retries
* occur if tx failed for this frame when it was a
* member of a previous aggregation block). If rate
* scaling is used, retry count indicates the rate
* table entry used for all frames in the new agg.
* 31-16: Sequence # for this frame's Tx cmd (not SSN!)
*/
union {
__le32 status;
struct agg_tx_status agg_status[0]; /* for each agg frame */
} u;
} __packed;
/*
* definitions for initial rate index field
* bits [3:0] initial rate index
@ -2030,52 +1543,8 @@ struct iwl_compressed_ba_resp {
/*
* REPLY_TX_PWR_TABLE_CMD = 0x97 (command, has simple generic response)
*
* See details under "TXPOWER" in iwl-4965-hw.h.
*/
struct iwl3945_txpowertable_cmd {
u8 band; /* 0: 5 GHz, 1: 2.4 GHz */
u8 reserved;
__le16 channel;
struct iwl3945_power_per_rate power[IWL_MAX_RATES];
} __packed;
struct iwl4965_txpowertable_cmd {
u8 band; /* 0: 5 GHz, 1: 2.4 GHz */
u8 reserved;
__le16 channel;
struct iwl4965_tx_power_db tx_power;
} __packed;
/**
* struct iwl3945_rate_scaling_cmd - Rate Scaling Command & Response
*
* REPLY_RATE_SCALE = 0x47 (command, has simple generic response)
*
* NOTE: The table of rates passed to the uCode via the
* RATE_SCALE command sets up the corresponding order of
* rates used for all related commands, including rate
* masks, etc.
*
* For example, if you set 9MB (PLCP 0x0f) as the first
* rate in the rate table, the bit mask for that rate
* when passed through ofdm_basic_rates on the REPLY_RXON
* command would be bit 0 (1 << 0)
*/
struct iwl3945_rate_scaling_info {
__le16 rate_n_flags;
u8 try_cnt;
u8 next_rate_index;
} __packed;
struct iwl3945_rate_scaling_cmd {
u8 table_id;
u8 reserved[3];
struct iwl3945_rate_scaling_info table[IWL_MAX_RATES];
} __packed;
/*RS_NEW_API: only TLC_RTS remains and moved to bit 0 */
#define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0)
@ -2130,7 +1599,7 @@ struct iwl_link_qual_general_params {
#define LINK_QUAL_AGG_DISABLE_START_MAX (255)
#define LINK_QUAL_AGG_DISABLE_START_MIN (0)
#define LINK_QUAL_AGG_FRAME_LIMIT_DEF (31)
#define LINK_QUAL_AGG_FRAME_LIMIT_DEF (63)
#define LINK_QUAL_AGG_FRAME_LIMIT_MAX (63)
#define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0)
@ -2696,14 +2165,6 @@ struct iwl_spectrum_notification {
#define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8))
#define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9))
struct iwl3945_powertable_cmd {
__le16 flags;
u8 reserved[2];
__le32 rx_data_timeout;
__le32 tx_data_timeout;
__le32 sleep_interval[IWL_POWER_VEC_SIZE];
} __packed;
struct iwl_powertable_cmd {
__le16 flags;
u8 keep_alive_seconds; /* 3945 reserved */
@ -2806,25 +2267,6 @@ struct iwl_ct_kill_throttling_config {
* active_dwell < max_out_time
*/
/* FIXME: rename to AP1, remove tpc */
struct iwl3945_scan_channel {
/*
* type is defined as:
* 0:0 1 = active, 0 = passive
* 1:4 SSID direct bit map; if a bit is set, then corresponding
* SSID IE is transmitted in probe request.
* 5:7 reserved
*/
u8 type;
u8 channel; /* band is selected by iwl3945_scan_cmd "flags" field */
struct iwl3945_tx_power tpc;
__le16 active_dwell; /* in 1024-uSec TU (time units), typ 5-50 */
__le16 passive_dwell; /* in 1024-uSec TU (time units), typ 20-500 */
} __packed;
/* set number of direct probes u8 type */
#define IWL39_SCAN_PROBE_MASK(n) ((BIT(n) | (BIT(n) - BIT(1))))
struct iwl_scan_channel {
/*
* type is defined as:
@ -2920,50 +2362,6 @@ struct iwl_ssid_ie {
* struct iwl_scan_channel.
*/
struct iwl3945_scan_cmd {
__le16 len;
u8 reserved0;
u8 channel_count; /* # channels in channel list */
__le16 quiet_time; /* dwell only this # millisecs on quiet channel
* (only for active scan) */
__le16 quiet_plcp_th; /* quiet chnl is < this # pkts (typ. 1) */
__le16 good_CRC_th; /* passive -> active promotion threshold */
__le16 reserved1;
__le32 max_out_time; /* max usec to be away from associated (service)
* channel */
__le32 suspend_time; /* pause scan this long (in "extended beacon
* format") when returning to service channel:
* 3945; 31:24 # beacons, 19:0 additional usec,
* 4965; 31:22 # beacons, 21:0 additional usec.
*/
__le32 flags; /* RXON_FLG_* */
__le32 filter_flags; /* RXON_FILTER_* */
/* For active scans (set to all-0s for passive scans).
* Does not include payload. Must specify Tx rate; no rate scaling. */
struct iwl3945_tx_cmd tx_cmd;
/* For directed active scans (set to all-0s otherwise) */
struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX_3945];
/*
* Probe request frame, followed by channel list.
*
* Size of probe request frame is specified by byte count in tx_cmd.
* Channel list follows immediately after probe request frame.
* Number of channels in list is specified by channel_count.
* Each channel in list is of type:
*
* struct iwl3945_scan_channel channels[0];
*
* NOTE: Only one band of channels can be scanned per pass. You
* must not mix 2.4GHz channels and 5.2GHz channels, and you must wait
* for one scan to complete (i.e. receive SCAN_COMPLETE_NOTIFICATION)
* before requesting another scan.
*/
u8 data[0];
} __packed;
enum iwl_scan_flags {
/* BIT(0) currently unused */
IWL_SCAN_FLAGS_ACTION_FRAME_TX = BIT(1),
@ -3090,20 +2488,6 @@ enum iwl_ibss_manager {
* BEACON_NOTIFICATION = 0x90 (notification only, not a command)
*/
struct iwl3945_beacon_notif {
struct iwl3945_tx_resp beacon_notify_hdr;
__le32 low_tsf;
__le32 high_tsf;
__le32 ibss_mgr_status;
} __packed;
struct iwl4965_beacon_notif {
struct iwl4965_tx_resp beacon_notify_hdr;
__le32 low_tsf;
__le32 high_tsf;
__le32 ibss_mgr_status;
} __packed;
struct iwlagn_beacon_notif {
struct iwlagn_tx_resp beacon_notify_hdr;
__le32 low_tsf;
@ -3115,14 +2499,6 @@ struct iwlagn_beacon_notif {
* REPLY_TX_BEACON = 0x91 (command, has simple generic response)
*/
struct iwl3945_tx_beacon_cmd {
struct iwl3945_tx_cmd tx;
__le16 tim_idx;
u8 tim_size;
u8 reserved1;
struct ieee80211_hdr frame[0]; /* beacon frame */
} __packed;
struct iwl_tx_beacon_cmd {
struct iwl_tx_cmd tx;
__le16 tim_idx;
@ -3471,13 +2847,6 @@ struct iwl_statistics_cmd {
#define STATISTICS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
#define STATISTICS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
struct iwl3945_notif_statistics {
__le32 flag;
struct iwl39_statistics_rx rx;
struct iwl39_statistics_tx tx;
struct iwl39_statistics_general general;
} __packed;
struct iwl_notif_statistics {
__le32 flag;
struct statistics_rx rx;
@ -4451,10 +3820,6 @@ struct iwl_rx_packet {
__le32 len_n_flags;
struct iwl_cmd_header hdr;
union {
struct iwl3945_rx_frame rx_frame;
struct iwl3945_tx_resp tx_resp;
struct iwl3945_beacon_notif beacon_status;
struct iwl_alive_resp alive_frame;
struct iwl_spectrum_notification spectrum_notif;
struct iwl_csa_notification csa_notif;

114
drivers/net/wireless/iwlwifi/iwl-core.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -890,10 +890,8 @@ void iwl_print_rx_config_cmd(struct iwl_priv *priv,
IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
}
#endif
/**
* iwl_irq_handle_error - called for HW or SW error interrupt from card
*/
void iwl_irq_handle_error(struct iwl_priv *priv)
void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand)
{
unsigned int reload_msec;
unsigned long reload_jiffies;
@ -904,18 +902,62 @@ void iwl_irq_handle_error(struct iwl_priv *priv)
/* Cancel currently queued command. */
clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
/* Keep the restart process from trying to send host
* commands by clearing the ready bit */
clear_bit(STATUS_READY, &priv->status);
wake_up_interruptible(&priv->wait_command_queue);
if (!ondemand) {
/*
* If firmware keep reloading, then it indicate something
* serious wrong and firmware having problem to recover
* from it. Instead of keep trying which will fill the syslog
* and hang the system, let's just stop it
*/
reload_jiffies = jiffies;
reload_msec = jiffies_to_msecs((long) reload_jiffies -
(long) priv->reload_jiffies);
priv->reload_jiffies = reload_jiffies;
if (reload_msec <= IWL_MIN_RELOAD_DURATION) {
priv->reload_count++;
if (priv->reload_count >= IWL_MAX_CONTINUE_RELOAD_CNT) {
IWL_ERR(priv, "BUG_ON, Stop restarting\n");
return;
}
} else
priv->reload_count = 0;
}
if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
if (priv->cfg->mod_params->restart_fw) {
IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
"Restarting adapter due to uCode error.\n");
queue_work(priv->workqueue, &priv->restart);
} else
IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
"Detected FW error, but not restarting\n");
}
}
/**
* iwl_irq_handle_error - called for HW or SW error interrupt from card
*/
void iwl_irq_handle_error(struct iwl_priv *priv)
{
/* W/A for WiFi/WiMAX coex and WiMAX own the RF */
if (priv->cfg->internal_wimax_coex &&
(!(iwl_read_prph(priv, APMG_CLK_CTRL_REG) &
APMS_CLK_VAL_MRB_FUNC_MODE) ||
(iwl_read_prph(priv, APMG_PS_CTRL_REG) &
APMG_PS_CTRL_VAL_RESET_REQ))) {
wake_up_interruptible(&priv->wait_command_queue);
/*
*Keep the restart process from trying to send host
* commands by clearing the INIT status bit
* Keep the restart process from trying to send host
* commands by clearing the ready bit.
*/
clear_bit(STATUS_READY, &priv->status);
clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
wake_up_interruptible(&priv->wait_command_queue);
IWL_ERR(priv, "RF is used by WiMAX\n");
return;
}
@ -935,38 +977,7 @@ void iwl_irq_handle_error(struct iwl_priv *priv)
&priv->contexts[IWL_RXON_CTX_BSS]);
#endif
wake_up_interruptible(&priv->wait_command_queue);
/* Keep the restart process from trying to send host
* commands by clearing the INIT status bit */
clear_bit(STATUS_READY, &priv->status);
/*
* If firmware keep reloading, then it indicate something
* serious wrong and firmware having problem to recover
* from it. Instead of keep trying which will fill the syslog
* and hang the system, let's just stop it
*/
reload_jiffies = jiffies;
reload_msec = jiffies_to_msecs((long) reload_jiffies -
(long) priv->reload_jiffies);
priv->reload_jiffies = reload_jiffies;
if (reload_msec <= IWL_MIN_RELOAD_DURATION) {
priv->reload_count++;
if (priv->reload_count >= IWL_MAX_CONTINUE_RELOAD_CNT) {
IWL_ERR(priv, "BUG_ON, Stop restarting\n");
return;
}
} else
priv->reload_count = 0;
if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
"Restarting adapter due to uCode error.\n");
if (priv->cfg->mod_params->restart_fw)
queue_work(priv->workqueue, &priv->restart);
}
iwlagn_fw_error(priv, false);
}
static int iwl_apm_stop_master(struct iwl_priv *priv)
@ -1094,21 +1105,13 @@ int iwl_apm_init(struct iwl_priv *priv)
}
/*
* Enable DMA and BSM (if used) clocks, wait for them to stabilize.
* BSM (Boostrap State Machine) is only in 3945 and 4965;
* later devices (i.e. 5000 and later) have non-volatile SRAM,
* and don't need BSM to restore data after power-saving sleep.
* Enable DMA clock and wait for it to stabilize.
*
* Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
* do not disable clocks. This preserves any hardware bits already
* set by default in "CLK_CTRL_REG" after reset.
*/
if (priv->cfg->base_params->use_bsm)
iwl_write_prph(priv, APMG_CLK_EN_REG,
APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
else
iwl_write_prph(priv, APMG_CLK_EN_REG,
APMG_CLK_VAL_DMA_CLK_RQT);
iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
udelay(20);
/* Disable L1-Active */
@ -1430,7 +1433,6 @@ void iwl_mac_remove_interface(struct ieee80211_hw *hw,
iwl_teardown_interface(priv, vif, false);
memset(priv->bssid, 0, ETH_ALEN);
mutex_unlock(&priv->mutex);
IWL_DEBUG_MAC80211(priv, "leave\n");
@ -1756,15 +1758,7 @@ int iwl_force_reset(struct iwl_priv *priv, int mode, bool external)
break;
}
IWL_ERR(priv, "On demand firmware reload\n");
/* Set the FW error flag -- cleared on iwl_down */
set_bit(STATUS_FW_ERROR, &priv->status);
wake_up_interruptible(&priv->wait_command_queue);
/*
* Keep the restart process from trying to send host
* commands by clearing the INIT status bit
*/
clear_bit(STATUS_READY, &priv->status);
queue_work(priv->workqueue, &priv->restart);
iwlagn_fw_error(priv, true);
break;
}
return 0;

40
drivers/net/wireless/iwlwifi/iwl-core.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -73,7 +73,7 @@ struct iwl_cmd;
#define IWLWIFI_VERSION "in-tree:"
#define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation"
#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
#define DRV_AUTHOR "<ilw@linux.intel.com>"
#define IWL_PCI_DEVICE(dev, subdev, cfg) \
@ -122,14 +122,6 @@ struct iwl_apm_ops {
void (*config)(struct iwl_priv *priv);
};
struct iwl_isr_ops {
irqreturn_t (*isr) (int irq, void *data);
void (*free)(struct iwl_priv *priv);
int (*alloc)(struct iwl_priv *priv);
int (*reset)(struct iwl_priv *priv);
void (*disable)(struct iwl_priv *priv);
};
struct iwl_debugfs_ops {
ssize_t (*rx_stats_read)(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos);
@ -171,25 +163,15 @@ struct iwl_lib_ops {
struct iwl_tx_queue *txq);
int (*txq_init)(struct iwl_priv *priv,
struct iwl_tx_queue *txq);
/* aggregations */
int (*txq_agg_enable)(struct iwl_priv *priv, int txq_id, int tx_fifo,
int sta_id, int tid, u16 ssn_idx);
int (*txq_agg_disable)(struct iwl_priv *priv, u16 txq_id, u16 ssn_idx,
u8 tx_fifo);
/* setup Rx handler */
void (*rx_handler_setup)(struct iwl_priv *priv);
/* setup deferred work */
void (*setup_deferred_work)(struct iwl_priv *priv);
/* cancel deferred work */
void (*cancel_deferred_work)(struct iwl_priv *priv);
/* alive notification after init uCode load */
void (*init_alive_start)(struct iwl_priv *priv);
/* alive notification */
int (*alive_notify)(struct iwl_priv *priv);
/* check validity of rtc data address */
int (*is_valid_rtc_data_addr)(u32 addr);
/* 1st ucode load */
int (*load_ucode)(struct iwl_priv *priv);
int (*dump_nic_event_log)(struct iwl_priv *priv,
bool full_log, char **buf, bool display);
void (*dump_nic_error_log)(struct iwl_priv *priv);
@ -204,9 +186,6 @@ struct iwl_lib_ops {
int (*send_tx_power) (struct iwl_priv *priv);
void (*update_chain_flags)(struct iwl_priv *priv);
/* isr */
struct iwl_isr_ops isr_ops;
/* eeprom operations (as defined in iwl-eeprom.h) */
struct iwl_eeprom_ops eeprom_ops;
@ -252,7 +231,6 @@ struct iwl_ops {
struct iwl_mod_params {
int sw_crypto; /* def: 0 = using hardware encryption */
int disable_hw_scan; /* def: 0 = use h/w scan */
int num_of_queues; /* def: HW dependent */
int disable_11n; /* def: 0 = 11n capabilities enabled */
int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */
@ -286,8 +264,6 @@ struct iwl_mod_params {
* @chain_noise_calib_by_driver: driver has the capability to perform
* chain noise calibration operation
* @shadow_reg_enable: HW shadhow register bit
* @no_agg_framecnt_info: uCode do not provide aggregation frame count
* information
*/
struct iwl_base_params {
int eeprom_size;
@ -296,9 +272,7 @@ struct iwl_base_params {
/* for iwl_apm_init() */
u32 pll_cfg_val;
bool set_l0s;
bool use_bsm;
bool use_isr_legacy;
const u16 max_ll_items;
const bool shadow_ram_support;
u16 led_compensation;
@ -317,7 +291,6 @@ struct iwl_base_params {
const bool sensitivity_calib_by_driver;
const bool chain_noise_calib_by_driver;
const bool shadow_reg_enable;
const bool no_agg_framecnt_info;
};
/*
* @advanced_bt_coexist: support advanced bt coexist
@ -738,10 +711,13 @@ static inline bool iwl_advanced_bt_coexist(struct iwl_priv *priv)
static inline bool iwl_bt_statistics(struct iwl_priv *priv)
{
return priv->cfg->bt_params && priv->cfg->bt_params->bt_statistics;
return priv->bt_statistics;
}
extern bool bt_coex_active;
extern bool bt_siso_mode;
void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand);
#endif /* __iwl_core_h__ */

43
drivers/net/wireless/iwlwifi/iwl-csr.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -155,18 +155,10 @@
#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
/* Bits for CSR_HW_IF_CONFIG_REG */
#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010)
#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100)
#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200)
#define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
#define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
@ -186,7 +178,7 @@
#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
@ -202,29 +194,17 @@
/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
#define CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */
#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
#define CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */
#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
#define CSR39_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
CSR39_FH_INT_BIT_RX_CHNL2 | \
CSR_FH_INT_BIT_RX_CHNL1 | \
CSR_FH_INT_BIT_RX_CHNL0)
#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
CSR_FH_INT_BIT_RX_CHNL1 | \
CSR_FH_INT_BIT_RX_CHNL0)
#define CSR39_FH_INT_TX_MASK (CSR39_FH_INT_BIT_TX_CHNL6 | \
CSR_FH_INT_BIT_TX_CHNL1 | \
CSR_FH_INT_BIT_TX_CHNL0)
#define CSR49_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
CSR_FH_INT_BIT_RX_CHNL1 | \
CSR_FH_INT_BIT_RX_CHNL0)
#define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
CSR_FH_INT_BIT_TX_CHNL0)
#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
CSR_FH_INT_BIT_TX_CHNL0)
/* GPIO */
#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
@ -268,7 +248,7 @@
* Indicates MAC (ucode processor, etc.) is powered up and can run.
* Internal resources are accessible.
* NOTE: This does not indicate that the processor is actually running.
* NOTE: This does not indicate that 4965 or 3945 has completed
* NOTE: This does not indicate that device has completed
* init or post-power-down restore of internal SRAM memory.
* Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
* SRAM is restored and uCode is in normal operation mode.
@ -291,8 +271,6 @@
/* HW REV */
#define CSR_HW_REV_TYPE_MSK (0x00001F0)
#define CSR_HW_REV_TYPE_3945 (0x00000D0)
#define CSR_HW_REV_TYPE_4965 (0x0000000)
#define CSR_HW_REV_TYPE_5300 (0x0000020)
#define CSR_HW_REV_TYPE_5350 (0x0000030)
#define CSR_HW_REV_TYPE_5100 (0x0000050)
@ -363,7 +341,7 @@
* 0: MAC_SLEEP
* uCode sets this when preparing a power-saving power-down.
* uCode resets this when power-up is complete and SRAM is sane.
* NOTE: 3945/4965 saves internal SRAM data to host when powering down,
* NOTE: device saves internal SRAM data to host when powering down,
* and must restore this data after powering back up.
* MAC_SLEEP is the best indication that restore is complete.
* Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
@ -394,7 +372,6 @@
#define CSR_LED_REG_TRUN_OFF (0x38)
/* ANA_PLL */
#define CSR39_ANA_PLL_CFG_VAL (0x01000000)
#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
/* HPET MEM debug */

4
drivers/net/wireless/iwlwifi/iwl-debug.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project.
*
@ -146,7 +146,6 @@ static inline void iwl_dbgfs_unregister(struct iwl_priv *priv)
#define IWL_DL_RX (1 << 24)
#define IWL_DL_ISR (1 << 25)
#define IWL_DL_HT (1 << 26)
#define IWL_DL_IO (1 << 27)
/* 0xF0000000 - 0x10000000 */
#define IWL_DL_11H (1 << 28)
#define IWL_DL_STATS (1 << 29)
@ -174,7 +173,6 @@ static inline void iwl_dbgfs_unregister(struct iwl_priv *priv)
IWL_DEBUG_LIMIT(p, IWL_DL_DROP, f, ## a)
#define IWL_DEBUG_AP(p, f, a...) IWL_DEBUG(p, IWL_DL_AP, f, ## a)
#define IWL_DEBUG_TXPOWER(p, f, a...) IWL_DEBUG(p, IWL_DL_TXPOWER, f, ## a)
#define IWL_DEBUG_IO(p, f, a...) IWL_DEBUG(p, IWL_DL_IO, f, ## a)
#define IWL_DEBUG_RATE(p, f, a...) IWL_DEBUG(p, IWL_DL_RATE, f, ## a)
#define IWL_DEBUG_RATE_LIMIT(p, f, a...) \
IWL_DEBUG_LIMIT(p, IWL_DL_RATE, f, ## a)

9
drivers/net/wireless/iwlwifi/iwl-debugfs.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -1572,12 +1572,10 @@ static ssize_t iwl_dbgfs_bt_traffic_read(struct file *file,
int pos = 0;
char buf[200];
const size_t bufsz = sizeof(buf);
ssize_t ret;
if (!priv->bt_enable_flag) {
pos += scnprintf(buf + pos, bufsz - pos, "BT coex disabled\n");
ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
return ret;
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
}
pos += scnprintf(buf + pos, bufsz - pos, "BT enable flag: 0x%x\n",
priv->bt_enable_flag);
@ -1608,8 +1606,7 @@ static ssize_t iwl_dbgfs_bt_traffic_read(struct file *file,
break;
}
ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
return ret;
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
}
static ssize_t iwl_dbgfs_protection_mode_read(struct file *file,

266
drivers/net/wireless/iwlwifi/iwl-dev.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -26,7 +26,6 @@
/*
* Please use this file (iwl-dev.h) for driver implementation definitions.
* Please use iwl-commands.h for uCode API definitions.
* Please use iwl-4965-hw.h for hardware-related definitions.
*/
#ifndef __iwl_dev_h__
@ -179,53 +178,12 @@ struct iwl_tx_queue {
#define IWL_NUM_SCAN_RATES (2)
struct iwl4965_channel_tgd_info {
u8 type;
s8 max_power;
};
struct iwl4965_channel_tgh_info {
s64 last_radar_time;
};
#define IWL4965_MAX_RATE (33)
struct iwl3945_clip_group {
/* maximum power level to prevent clipping for each rate, derived by
* us from this band's saturation power in EEPROM */
const s8 clip_powers[IWL_MAX_RATES];
};
/* current Tx power values to use, one for each rate for each channel.
* requested power is limited by:
* -- regulatory EEPROM limits for this channel
* -- hardware capabilities (clip-powers)
* -- spectrum management
* -- user preference (e.g. iwconfig)
* when requested power is set, base power index must also be set. */
struct iwl3945_channel_power_info {
struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
s8 power_table_index; /* actual (compenst'd) index into gain table */
s8 base_power_index; /* gain index for power at factory temp. */
s8 requested_power; /* power (dBm) requested for this chnl/rate */
};
/* current scan Tx power values to use, one for each scan rate for each
* channel. */
struct iwl3945_scan_power_info {
struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
s8 power_table_index; /* actual (compenst'd) index into gain table */
s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
};
/*
* One for each channel, holds all channel setup data
* Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
* with one another!
*/
struct iwl_channel_info {
struct iwl4965_channel_tgd_info tgd;
struct iwl4965_channel_tgh_info tgh;
struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
* HT40 channel */
@ -245,14 +203,6 @@ struct iwl_channel_info {
s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
u8 ht40_flags; /* flags copied from EEPROM */
u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
/* Radio/DSP gain settings for each "normal" data Tx rate.
* These include, in addition to RF and DSP gain, a few fields for
* remembering/modifying gain settings (indexes). */
struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
/* Radio/DSP gain settings for each scan rate, for directed scans. */
struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
};
#define IWL_TX_FIFO_BK 0 /* shared */
@ -309,6 +259,7 @@ enum {
CMD_SIZE_HUGE = (1 << 0),
CMD_ASYNC = (1 << 1),
CMD_WANT_SKB = (1 << 2),
CMD_MAPPED = (1 << 3),
};
#define DEF_CMD_PAYLOAD_SIZE 320
@ -416,6 +367,7 @@ struct iwl_ht_agg {
#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
#define IWL_EMPTYING_HW_QUEUE_DELBA 3
u8 state;
u8 tx_fifo;
};
@ -499,9 +451,6 @@ struct iwl_station_priv_common {
* When mac80211 creates a station it reserves some space (hw->sta_data_size)
* in the structure for use by driver. This structure is places in that
* space.
*
* The common struct MUST be first because it is shared between
* 3945 and agn!
*/
struct iwl_station_priv {
struct iwl_station_priv_common common;
@ -586,6 +535,22 @@ enum iwl_ucode_tlv_type {
IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
/* 16 and 17 reserved for future use */
IWL_UCODE_TLV_FLAGS = 18,
};
/**
* enum iwl_ucode_tlv_flag - ucode API flags
* @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
* was a separate TLV but moved here to save space.
* @IWL_UCODE_TLV_FLAGS_BTSTATS: This uCode image uses BT statistics, which
* may be true even if the device doesn't have BT.
* @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
*/
enum iwl_ucode_tlv_flag {
IWL_UCODE_TLV_FLAGS_PAN = BIT(0),
IWL_UCODE_TLV_FLAGS_BTSTATS = BIT(1),
IWL_UCODE_TLV_FLAGS_MFP = BIT(2),
};
struct iwl_ucode_tlv {
@ -619,14 +584,6 @@ struct iwl_tlv_ucode_header {
u8 data[0];
};
struct iwl4965_ibss_seq {
u8 mac[ETH_ALEN];
u16 seq_num;
u16 frag_num;
unsigned long packet_time;
struct list_head list;
};
struct iwl_sensitivity_ranges {
u16 min_nrg_cck;
u16 max_nrg_cck;
@ -700,7 +657,6 @@ struct iwl_hw_params {
u8 max_beacon_itrvl; /* in 1024 ms */
u32 max_inst_size;
u32 max_data_size;
u32 max_bsm_size;
u32 ct_kill_threshold; /* value in hw-dependent units */
u32 ct_kill_exit_threshold; /* value in hw-dependent units */
/* for 1000, 6000 series and up */
@ -722,8 +678,6 @@ struct iwl_hw_params {
* Naming convention --
* iwl_ <-- Is part of iwlwifi
* iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
* iwl4965_bg_ <-- Called from work queue context
* iwl4965_mac_ <-- mac80211 callback
*
****************************************************************************/
extern void iwl_update_chain_flags(struct iwl_priv *priv);
@ -772,7 +726,6 @@ struct iwl_dma_ptr {
/* Sensitivity and chain noise calibration */
#define INITIALIZATION_VALUE 0xFFFF
#define IWL4965_CAL_NUM_BEACONS 20
#define IWL_CAL_NUM_BEACONS 16
#define MAXIMUM_ALLOWED_PATHLOSS 15
@ -806,24 +759,19 @@ struct iwl_dma_ptr {
#define NRG_NUM_PREV_STAT_L 20
#define NUM_RX_CHAINS 3
enum iwl4965_false_alarm_state {
enum iwlagn_false_alarm_state {
IWL_FA_TOO_MANY = 0,
IWL_FA_TOO_FEW = 1,
IWL_FA_GOOD_RANGE = 2,
};
enum iwl4965_chain_noise_state {
enum iwlagn_chain_noise_state {
IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
IWL_CHAIN_NOISE_ACCUMULATE,
IWL_CHAIN_NOISE_CALIBRATED,
IWL_CHAIN_NOISE_DONE,
};
enum iwl4965_calib_enabled_state {
IWL_CALIB_DISABLED = 0, /* must be 0 */
IWL_CALIB_ENABLED = 1,
};
/*
* enum iwl_calib
@ -1130,12 +1078,6 @@ struct iwl_force_reset {
};
/* extend beacon time format bit shifting */
/*
* for _3945 devices
* bits 31:24 - extended
* bits 23:0 - interval
*/
#define IWL3945_EXT_BEACON_TIME_POS 24
/*
* for _agn devices
* bits 31:22 - extended
@ -1249,7 +1191,6 @@ struct iwl_priv {
int frames_count;
enum ieee80211_band band;
int alloc_rxb_page;
void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
struct iwl_rx_mem_buffer *rxb);
@ -1305,16 +1246,12 @@ struct iwl_priv {
spinlock_t hcmd_lock; /* protect hcmd */
spinlock_t reg_lock; /* protect hw register access */
struct mutex mutex;
struct mutex sync_cmd_mutex; /* enable serialization of sync commands */
/* basic pci-network driver stuff */
struct pci_dev *pci_dev;
/* pci hardware address support */
void __iomem *hw_base;
u32 hw_rev;
u32 hw_wa_rev;
u8 rev_id;
/* microcode/device supports multiple contexts */
u8 valid_contexts;
@ -1334,10 +1271,8 @@ struct iwl_priv {
iwl_ucode.ver */
struct fw_desc ucode_code; /* runtime inst */
struct fw_desc ucode_data; /* runtime data original */
struct fw_desc ucode_data_backup; /* runtime data save/restore */
struct fw_desc ucode_init; /* initialization inst */
struct fw_desc ucode_init_data; /* initialization data */
struct fw_desc ucode_boot; /* bootstrap inst */
enum ucode_type ucode_type;
u8 ucode_write_complete; /* the image write is complete */
char firmware_name[25];
@ -1346,10 +1281,10 @@ struct iwl_priv {
struct iwl_switch_rxon switch_rxon;
/* 1st responses from initialize and runtime uCode images.
* _agn's initialize alive response contains some calibration data. */
struct iwl_init_alive_resp card_alive_init;
struct iwl_alive_resp card_alive;
struct {
u32 error_event_table;
u32 log_event_table;
} device_pointers;
u16 active_rate;
@ -1390,15 +1325,12 @@ struct iwl_priv {
struct iwl_power_mgr power_data;
struct iwl_tt_mgmt thermal_throttle;
/* context information */
u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
/* station table variables */
/* Note: if lock and sta_lock are needed, lock must be acquired first */
spinlock_t sta_lock;
int num_stations;
struct iwl_station_entry stations[IWL_STATION_COUNT];
struct iwl_station_entry stations[IWLAGN_STATION_COUNT];
unsigned long ucode_key_table;
/* queue refcounts */
@ -1422,101 +1354,66 @@ struct iwl_priv {
/* Last Rx'd beacon timestamp */
u64 timestamp;
union {
#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
struct {
void *shared_virt;
dma_addr_t shared_phys;
struct {
/* INT ICT Table */
__le32 *ict_tbl;
void *ict_tbl_vir;
dma_addr_t ict_tbl_dma;
dma_addr_t aligned_ict_tbl_dma;
int ict_index;
u32 inta;
bool use_ict;
/*
* reporting the number of tids has AGG on. 0 means
* no AGGREGATION
*/
u8 agg_tids_count;
struct delayed_work thermal_periodic;
struct delayed_work rfkill_poll;
struct iwl_rx_phy_res last_phy_res;
bool last_phy_res_valid;
struct iwl3945_notif_statistics statistics;
struct completion firmware_loading_complete;
u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
/*
* chain noise reset and gain commands are the
* two extra calibration commands follows the standard
* phy calibration commands
*/
u8 phy_calib_chain_noise_reset_cmd;
u8 phy_calib_chain_noise_gain_cmd;
struct iwl_notif_statistics statistics;
struct iwl_bt_notif_statistics statistics_bt;
/* counts reply_tx error */
struct reply_tx_error_statistics reply_tx_stats;
struct reply_agg_tx_error_statistics reply_agg_tx_stats;
#ifdef CONFIG_IWLWIFI_DEBUGFS
struct iwl3945_notif_statistics accum_statistics;
struct iwl3945_notif_statistics delta_statistics;
struct iwl3945_notif_statistics max_delta;
struct iwl_notif_statistics accum_statistics;
struct iwl_notif_statistics delta_statistics;
struct iwl_notif_statistics max_delta;
struct iwl_bt_notif_statistics accum_statistics_bt;
struct iwl_bt_notif_statistics delta_statistics_bt;
struct iwl_bt_notif_statistics max_delta_bt;
#endif
/* notification wait support */
struct list_head notif_waits;
spinlock_t notif_wait_lock;
wait_queue_head_t notif_waitq;
u32 sta_supp_rates;
int last_rx_rssi; /* From Rx packet statistics */
/* remain-on-channel offload support */
struct ieee80211_channel *hw_roc_channel;
struct delayed_work hw_roc_work;
enum nl80211_channel_type hw_roc_chantype;
int hw_roc_duration;
bool hw_roc_setup;
/* Rx'd packet timing information */
u32 last_beacon_time;
u64 last_tsf;
/*
* each calibration channel group in the
* EEPROM has a derived clip setting for
* each rate.
*/
const struct iwl3945_clip_group clip_groups[5];
} _3945;
#endif
#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
struct {
/* INT ICT Table */
__le32 *ict_tbl;
void *ict_tbl_vir;
dma_addr_t ict_tbl_dma;
dma_addr_t aligned_ict_tbl_dma;
int ict_index;
u32 inta;
bool use_ict;
/*
* reporting the number of tids has AGG on. 0 means
* no AGGREGATION
*/
u8 agg_tids_count;
struct iwl_rx_phy_res last_phy_res;
bool last_phy_res_valid;
struct completion firmware_loading_complete;
u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
/*
* chain noise reset and gain commands are the
* two extra calibration commands follows the standard
* phy calibration commands
*/
u8 phy_calib_chain_noise_reset_cmd;
u8 phy_calib_chain_noise_gain_cmd;
struct iwl_notif_statistics statistics;
struct iwl_bt_notif_statistics statistics_bt;
/* counts reply_tx error */
struct reply_tx_error_statistics reply_tx_stats;
struct reply_agg_tx_error_statistics reply_agg_tx_stats;
#ifdef CONFIG_IWLWIFI_DEBUGFS
struct iwl_notif_statistics accum_statistics;
struct iwl_notif_statistics delta_statistics;
struct iwl_notif_statistics max_delta;
struct iwl_bt_notif_statistics accum_statistics_bt;
struct iwl_bt_notif_statistics delta_statistics_bt;
struct iwl_bt_notif_statistics max_delta_bt;
#endif
/* notification wait support */
struct list_head notif_waits;
spinlock_t notif_wait_lock;
wait_queue_head_t notif_waitq;
/* remain-on-channel offload support */
struct ieee80211_channel *hw_roc_channel;
struct delayed_work hw_roc_work;
enum nl80211_channel_type hw_roc_chantype;
int hw_roc_duration;
struct sk_buff *offchan_tx_skb;
int offchan_tx_timeout;
struct ieee80211_channel *offchan_tx_chan;
} _agn;
#endif
};
struct sk_buff *offchan_tx_skb;
int offchan_tx_timeout;
struct ieee80211_channel *offchan_tx_chan;
} _agn;
/* bt coex */
u8 bt_enable_flag;
@ -1525,6 +1422,7 @@ struct iwl_priv {
bool bt_ch_announce;
bool bt_full_concurrent;
bool bt_ant_couple_ok;
bool bt_statistics;
__le32 kill_ack_mask;
__le32 kill_cts_mask;
__le16 bt_valid;
@ -1710,12 +1608,10 @@ static inline int is_channel_ibss(const struct iwl_channel_info *ch)
static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
{
__free_pages(page, priv->hw_params.rx_page_order);
priv->alloc_rxb_page--;
}
static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
{
free_pages(page, priv->hw_params.rx_page_order);
priv->alloc_rxb_page--;
}
#endif /* __iwl_dev_h__ */

2
drivers/net/wireless/iwlwifi/iwl-devtrace.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2009 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2009 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/iwl-devtrace.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2009 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2009 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

50
drivers/net/wireless/iwlwifi/iwl-eeprom.c
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -188,18 +188,16 @@ static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
CSR_OTP_GP_REG_OTP_ACCESS_MODE);
}
static int iwlcore_get_nvm_type(struct iwl_priv *priv)
static int iwlcore_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
{
u32 otpgp;
int nvm_type;
/* OTP only valid for CP/PP and after */
switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
switch (hw_rev & CSR_HW_REV_TYPE_MSK) {
case CSR_HW_REV_TYPE_NONE:
IWL_ERR(priv, "Unknown hardware type\n");
return -ENOENT;
case CSR_HW_REV_TYPE_3945:
case CSR_HW_REV_TYPE_4965:
case CSR_HW_REV_TYPE_5300:
case CSR_HW_REV_TYPE_5350:
case CSR_HW_REV_TYPE_5100:
@ -228,15 +226,15 @@ static int iwl_init_otp_access(struct iwl_priv *priv)
int ret;
/* Enable 40MHz radio clock */
_iwl_write32(priv, CSR_GP_CNTRL,
_iwl_read32(priv, CSR_GP_CNTRL) |
CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
iwl_write32(priv, CSR_GP_CNTRL,
iwl_read32(priv, CSR_GP_CNTRL) |
CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
/* wait for clock to be ready */
ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
25000);
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
25000);
if (ret < 0)
IWL_ERR(priv, "Time out access OTP\n");
else {
@ -263,17 +261,17 @@ static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_dat
u32 r;
u32 otpgp;
_iwl_write32(priv, CSR_EEPROM_REG,
CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
iwl_write32(priv, CSR_EEPROM_REG,
CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
CSR_EEPROM_REG_READ_VALID_MSK,
CSR_EEPROM_REG_READ_VALID_MSK,
IWL_EEPROM_ACCESS_TIMEOUT);
CSR_EEPROM_REG_READ_VALID_MSK,
CSR_EEPROM_REG_READ_VALID_MSK,
IWL_EEPROM_ACCESS_TIMEOUT);
if (ret < 0) {
IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
return ret;
}
r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
r = iwl_read32(priv, CSR_EEPROM_REG);
/* check for ECC errors: */
otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
@ -396,7 +394,7 @@ u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
*
* NOTE: This routine uses the non-debug IO access functions.
*/
int iwl_eeprom_init(struct iwl_priv *priv)
int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
{
__le16 *e;
u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
@ -406,7 +404,7 @@ int iwl_eeprom_init(struct iwl_priv *priv)
u16 validblockaddr = 0;
u16 cache_addr = 0;
priv->nvm_device_type = iwlcore_get_nvm_type(priv);
priv->nvm_device_type = iwlcore_get_nvm_type(priv, hw_rev);
if (priv->nvm_device_type == -ENOENT)
return -ENOENT;
/* allocate eeprom */
@ -444,9 +442,9 @@ int iwl_eeprom_init(struct iwl_priv *priv)
ret = -ENOENT;
goto done;
}
_iwl_write32(priv, CSR_EEPROM_GP,
iwl_read32(priv, CSR_EEPROM_GP) &
~CSR_EEPROM_GP_IF_OWNER_MSK);
iwl_write32(priv, CSR_EEPROM_GP,
iwl_read32(priv, CSR_EEPROM_GP) &
~CSR_EEPROM_GP_IF_OWNER_MSK);
iwl_set_bit(priv, CSR_OTP_GP_REG,
CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
@ -473,8 +471,8 @@ int iwl_eeprom_init(struct iwl_priv *priv)
for (addr = 0; addr < sz; addr += sizeof(u16)) {
u32 r;
_iwl_write32(priv, CSR_EEPROM_REG,
CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
iwl_write32(priv, CSR_EEPROM_REG,
CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
CSR_EEPROM_REG_READ_VALID_MSK,
@ -484,7 +482,7 @@ int iwl_eeprom_init(struct iwl_priv *priv)
IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
goto done;
}
r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
r = iwl_read32(priv, CSR_EEPROM_REG);
e[addr / 2] = cpu_to_le16(r >> 16);
}
}

191
drivers/net/wireless/iwlwifi/iwl-eeprom.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -110,10 +110,6 @@ enum {
};
/* SKU Capabilities */
/* 3945 only */
#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
/* 5000 and up */
#define EEPROM_SKU_CAP_BAND_POS (4)
#define EEPROM_SKU_CAP_BAND_SELECTION \
@ -168,28 +164,6 @@ struct iwl_eeprom_enhanced_txpwr {
s8 mimo3_max;
} __packed;
/* 3945 Specific */
#define EEPROM_3945_EEPROM_VERSION (0x2f)
/* 4965 has two radio transmitters (and 3 radio receivers) */
#define EEPROM_TX_POWER_TX_CHAINS (2)
/* 4965 has room for up to 8 sets of txpower calibration data */
#define EEPROM_TX_POWER_BANDS (8)
/* 4965 factory calibration measures txpower gain settings for
* each of 3 target output levels */
#define EEPROM_TX_POWER_MEASUREMENTS (3)
/* 4965 Specific */
/* 4965 driver does not work with txpower calibration version < 5 */
#define EEPROM_4965_TX_POWER_VERSION (5)
#define EEPROM_4965_EEPROM_VERSION (0x2f)
#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
/* 5000 Specific */
#define EEPROM_5000_TX_POWER_VERSION (4)
#define EEPROM_5000_EEPROM_VERSION (0x11A)
@ -282,90 +256,6 @@ struct iwl_eeprom_enhanced_txpwr {
/* 2.4 GHz */
extern const u8 iwl_eeprom_band_1[14];
/*
* factory calibration data for one txpower level, on one channel,
* measured on one of the 2 tx chains (radio transmitter and associated
* antenna). EEPROM contains:
*
* 1) Temperature (degrees Celsius) of device when measurement was made.
*
* 2) Gain table index used to achieve the target measurement power.
* This refers to the "well-known" gain tables (see iwl-4965-hw.h).
*
* 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
*
* 4) RF power amplifier detector level measurement (not used).
*/
struct iwl_eeprom_calib_measure {
u8 temperature; /* Device temperature (Celsius) */
u8 gain_idx; /* Index into gain table */
u8 actual_pow; /* Measured RF output power, half-dBm */
s8 pa_det; /* Power amp detector level (not used) */
} __packed;
/*
* measurement set for one channel. EEPROM contains:
*
* 1) Channel number measured
*
* 2) Measurements for each of 3 power levels for each of 2 radio transmitters
* (a.k.a. "tx chains") (6 measurements altogether)
*/
struct iwl_eeprom_calib_ch_info {
u8 ch_num;
struct iwl_eeprom_calib_measure
measurements[EEPROM_TX_POWER_TX_CHAINS]
[EEPROM_TX_POWER_MEASUREMENTS];
} __packed;
/*
* txpower subband info.
*
* For each frequency subband, EEPROM contains the following:
*
* 1) First and last channels within range of the subband. "0" values
* indicate that this sample set is not being used.
*
* 2) Sample measurement sets for 2 channels close to the range endpoints.
*/
struct iwl_eeprom_calib_subband_info {
u8 ch_from; /* channel number of lowest channel in subband */
u8 ch_to; /* channel number of highest channel in subband */
struct iwl_eeprom_calib_ch_info ch1;
struct iwl_eeprom_calib_ch_info ch2;
} __packed;
/*
* txpower calibration info. EEPROM contains:
*
* 1) Factory-measured saturation power levels (maximum levels at which
* tx power amplifier can output a signal without too much distortion).
* There is one level for 2.4 GHz band and one for 5 GHz band. These
* values apply to all channels within each of the bands.
*
* 2) Factory-measured power supply voltage level. This is assumed to be
* constant (i.e. same value applies to all channels/bands) while the
* factory measurements are being made.
*
* 3) Up to 8 sets of factory-measured txpower calibration values.
* These are for different frequency ranges, since txpower gain
* characteristics of the analog radio circuitry vary with frequency.
*
* Not all sets need to be filled with data;
* struct iwl_eeprom_calib_subband_info contains range of channels
* (0 if unused) for each set of data.
*/
struct iwl_eeprom_calib_info {
u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
u8 saturation_power52; /* half-dBm */
__le16 voltage; /* signed */
struct iwl_eeprom_calib_subband_info
band_info[EEPROM_TX_POWER_BANDS];
} __packed;
#define ADDRESS_MSK 0x0000FFFF
#define INDIRECT_TYPE_MSK 0x000F0000
#define INDIRECT_HOST 0x00010000
@ -398,83 +288,8 @@ struct iwl_eeprom_calib_info {
#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
/* Radio Config for 5000 and up */
#define EEPROM_RF_CONFIG_TYPE_R3x3 0x0
#define EEPROM_RF_CONFIG_TYPE_R2x2 0x1
#define EEPROM_RF_CONFIG_TYPE_R1x2 0x2
#define EEPROM_RF_CONFIG_TYPE_MAX 0x3
/*
* Per-channel regulatory data.
*
* Each channel that *might* be supported by iwl has a fixed location
* in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
* txpower (MSB).
*
* Entries immediately below are for 20 MHz channel width. HT40 (40 MHz)
* channels (only for 4965, not supported by 3945) appear later in the EEPROM.
*
* 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
*/
#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
/*
* 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
* 5.0 GHz channels 7, 8, 11, 12, 16
* (4915-5080MHz) (none of these is ever supported)
*/
#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
/*
* 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
* (5170-5320MHz)
*/
#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
/*
* 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
* (5500-5700MHz)
*/
#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
/*
* 5.7 GHz channels 145, 149, 153, 157, 161, 165
* (5725-5825MHz)
*/
#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
/*
* 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
*
* The channel listed is the center of the lower 20 MHz half of the channel.
* The overall center frequency is actually 2 channels (10 MHz) above that,
* and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
* from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
* and the overall HT40 channel width centers on channel 3.
*
* NOTE: The RXON command uses 20 MHz channel numbers to specify the
* control channel to which to tune. RXON also specifies whether the
* control channel is the upper or lower half of a HT40 channel.
*
* NOTE: 4965 does not support HT40 channels on 2.4 GHz.
*/
#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */
/*
* 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
* 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
*/
#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */
#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
struct iwl_eeprom_ops {
@ -487,7 +302,7 @@ struct iwl_eeprom_ops {
};
int iwl_eeprom_init(struct iwl_priv *priv);
int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev);
void iwl_eeprom_free(struct iwl_priv *priv);
int iwl_eeprom_check_version(struct iwl_priv *priv);
int iwl_eeprom_check_sku(struct iwl_priv *priv);

4
drivers/net/wireless/iwlwifi/iwl-fh.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

17
drivers/net/wireless/iwlwifi/iwl-hcmd.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -51,9 +51,7 @@ const char *get_cmd_string(u8 cmd)
IWL_CMD(REPLY_REMOVE_ALL_STA);
IWL_CMD(REPLY_TXFIFO_FLUSH);
IWL_CMD(REPLY_WEPKEY);
IWL_CMD(REPLY_3945_RX);
IWL_CMD(REPLY_TX);
IWL_CMD(REPLY_RATE_SCALE);
IWL_CMD(REPLY_LEDS_CMD);
IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
IWL_CMD(COEX_PRIORITY_TABLE_CMD);
@ -171,14 +169,13 @@ int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
int cmd_idx;
int ret;
BUG_ON(cmd->flags & CMD_ASYNC);
lockdep_assert_held(&priv->mutex);
/* A synchronous command can not have a callback set. */
BUG_ON(cmd->callback);
BUG_ON((cmd->flags & CMD_ASYNC) || cmd->callback);
IWL_DEBUG_INFO(priv, "Attempting to send sync command %s\n",
get_cmd_string(cmd->id));
mutex_lock(&priv->sync_cmd_mutex);
set_bit(STATUS_HCMD_ACTIVE, &priv->status);
IWL_DEBUG_INFO(priv, "Setting HCMD_ACTIVE for command %s\n",
@ -189,7 +186,7 @@ int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
ret = cmd_idx;
IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
get_cmd_string(cmd->id), ret);
goto out;
return ret;
}
ret = wait_event_interruptible_timeout(priv->wait_command_queue,
@ -229,8 +226,7 @@ int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
goto cancel;
}
ret = 0;
goto out;
return 0;
cancel:
if (cmd->flags & CMD_WANT_SKB) {
@ -248,8 +244,7 @@ fail:
iwl_free_pages(priv, cmd->reply_page);
cmd->reply_page = 0;
}
out:
mutex_unlock(&priv->sync_cmd_mutex);
return ret;
}

2
drivers/net/wireless/iwlwifi/iwl-helpers.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

274
drivers/net/wireless/iwlwifi/iwl-io.c Normal file
View File

@ -0,0 +1,274 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* Intel Linux Wireless <ilw@linux.intel.com>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*
*****************************************************************************/
#include "iwl-io.h"
#define IWL_POLL_INTERVAL 10 /* microseconds */
static inline void __iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
iwl_write32(priv, reg, iwl_read32(priv, reg) | mask);
}
static inline void __iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
iwl_write32(priv, reg, iwl_read32(priv, reg) & ~mask);
}
void iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&priv->reg_lock, flags);
__iwl_set_bit(priv, reg, mask);
spin_unlock_irqrestore(&priv->reg_lock, flags);
}
void iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&priv->reg_lock, flags);
__iwl_clear_bit(priv, reg, mask);
spin_unlock_irqrestore(&priv->reg_lock, flags);
}
int iwl_poll_bit(struct iwl_priv *priv, u32 addr,
u32 bits, u32 mask, int timeout)
{
int t = 0;
do {
if ((iwl_read32(priv, addr) & mask) == (bits & mask))
return t;
udelay(IWL_POLL_INTERVAL);
t += IWL_POLL_INTERVAL;
} while (t < timeout);
return -ETIMEDOUT;
}
int iwl_grab_nic_access(struct iwl_priv *priv)
{
int ret;
u32 val;
lockdep_assert_held(&priv->reg_lock);
/* this bit wakes up the NIC */
__iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
/*
* These bits say the device is running, and should keep running for
* at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
* but they do not indicate that embedded SRAM is restored yet;
* 3945 and 4965 have volatile SRAM, and must save/restore contents
* to/from host DRAM when sleeping/waking for power-saving.
* Each direction takes approximately 1/4 millisecond; with this
* overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
* series of register accesses are expected (e.g. reading Event Log),
* to keep device from sleeping.
*
* CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
* SRAM is okay/restored. We don't check that here because this call
* is just for hardware register access; but GP1 MAC_SLEEP check is a
* good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
*
* 5000 series and later (including 1000 series) have non-volatile SRAM,
* and do not save/restore SRAM when power cycling.
*/
ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
(CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
if (ret < 0) {
val = iwl_read32(priv, CSR_GP_CNTRL);
IWL_ERR(priv,
"MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
return -EIO;
}
return 0;
}
void iwl_release_nic_access(struct iwl_priv *priv)
{
lockdep_assert_held(&priv->reg_lock);
__iwl_clear_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
}
u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg)
{
u32 value;
unsigned long flags;
spin_lock_irqsave(&priv->reg_lock, flags);
iwl_grab_nic_access(priv);
value = iwl_read32(priv, reg);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, flags);
return value;
}
void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value)
{
unsigned long flags;
spin_lock_irqsave(&priv->reg_lock, flags);
if (!iwl_grab_nic_access(priv)) {
iwl_write32(priv, reg, value);
iwl_release_nic_access(priv);
}
spin_unlock_irqrestore(&priv->reg_lock, flags);
}
int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask,
int timeout)
{
int t = 0;
do {
if ((iwl_read_direct32(priv, addr) & mask) == mask)
return t;
udelay(IWL_POLL_INTERVAL);
t += IWL_POLL_INTERVAL;
} while (t < timeout);
return -ETIMEDOUT;
}
static inline u32 __iwl_read_prph(struct iwl_priv *priv, u32 reg)
{
iwl_write32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
rmb();
return iwl_read32(priv, HBUS_TARG_PRPH_RDAT);
}
static inline void __iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
{
iwl_write32(priv, HBUS_TARG_PRPH_WADDR,
((addr & 0x0000FFFF) | (3 << 24)));
wmb();
iwl_write32(priv, HBUS_TARG_PRPH_WDAT, val);
}
u32 iwl_read_prph(struct iwl_priv *priv, u32 reg)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&priv->reg_lock, flags);
iwl_grab_nic_access(priv);
val = __iwl_read_prph(priv, reg);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, flags);
return val;
}
void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
{
unsigned long flags;
spin_lock_irqsave(&priv->reg_lock, flags);
if (!iwl_grab_nic_access(priv)) {
__iwl_write_prph(priv, addr, val);
iwl_release_nic_access(priv);
}
spin_unlock_irqrestore(&priv->reg_lock, flags);
}
void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&priv->reg_lock, flags);
iwl_grab_nic_access(priv);
__iwl_write_prph(priv, reg, __iwl_read_prph(priv, reg) | mask);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, flags);
}
void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg,
u32 bits, u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&priv->reg_lock, flags);
iwl_grab_nic_access(priv);
__iwl_write_prph(priv, reg,
(__iwl_read_prph(priv, reg) & mask) | bits);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, flags);
}
void iwl_clear_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&priv->reg_lock, flags);
iwl_grab_nic_access(priv);
val = __iwl_read_prph(priv, reg);
__iwl_write_prph(priv, reg, (val & ~mask));
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, flags);
}
u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
{
unsigned long flags;
u32 value;
spin_lock_irqsave(&priv->reg_lock, flags);
iwl_grab_nic_access(priv);
iwl_write32(priv, HBUS_TARG_MEM_RADDR, addr);
rmb();
value = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, flags);
return value;
}
void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
{
unsigned long flags;
spin_lock_irqsave(&priv->reg_lock, flags);
if (!iwl_grab_nic_access(priv)) {
iwl_write32(priv, HBUS_TARG_MEM_WADDR, addr);
wmb();
iwl_write32(priv, HBUS_TARG_MEM_WDAT, val);
iwl_release_nic_access(priv);
}
spin_unlock_irqrestore(&priv->reg_lock, flags);
}

503
drivers/net/wireless/iwlwifi/iwl-io.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project.
*
@ -35,494 +35,47 @@
#include "iwl-debug.h"
#include "iwl-devtrace.h"
/*
* IO, register, and NIC memory access functions
*
* NOTE on naming convention and macro usage for these
*
* A single _ prefix before a an access function means that no state
* check or debug information is printed when that function is called.
*
* A double __ prefix before an access function means that state is checked
* and the current line number and caller function name are printed in addition
* to any other debug output.
*
* The non-prefixed name is the #define that maps the caller into a
* #define that provides the caller's name and __LINE__ to the double
* prefix version.
*
* If you wish to call the function without any debug or state checking,
* you should use the single _ prefix version (as is used by dependent IO
* routines, for example _iwl_read_direct32 calls the non-check version of
* _iwl_read32.)
*
* These declarations are *extremely* useful in quickly isolating code deltas
* which result in misconfiguration of the hardware I/O. In combination with
* git-bisect and the IO debug level you can quickly determine the specific
* commit which breaks the IO sequence to the hardware.
*
*/
static inline void _iwl_write8(struct iwl_priv *priv, u32 ofs, u8 val)
static inline void iwl_write8(struct iwl_priv *priv, u32 ofs, u8 val)
{
trace_iwlwifi_dev_iowrite8(priv, ofs, val);
iowrite8(val, priv->hw_base + ofs);
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl_write8(const char *f, u32 l, struct iwl_priv *priv,
u32 ofs, u8 val)
{
IWL_DEBUG_IO(priv, "write8(0x%08X, 0x%02X) - %s %d\n", ofs, val, f, l);
_iwl_write8(priv, ofs, val);
}
#define iwl_write8(priv, ofs, val) \
__iwl_write8(__FILE__, __LINE__, priv, ofs, val)
#else
#define iwl_write8(priv, ofs, val) _iwl_write8(priv, ofs, val)
#endif
static inline void _iwl_write32(struct iwl_priv *priv, u32 ofs, u32 val)
static inline void iwl_write32(struct iwl_priv *priv, u32 ofs, u32 val)
{
trace_iwlwifi_dev_iowrite32(priv, ofs, val);
iowrite32(val, priv->hw_base + ofs);
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl_write32(const char *f, u32 l, struct iwl_priv *priv,
u32 ofs, u32 val)
{
IWL_DEBUG_IO(priv, "write32(0x%08X, 0x%08X) - %s %d\n", ofs, val, f, l);
_iwl_write32(priv, ofs, val);
}
#define iwl_write32(priv, ofs, val) \
__iwl_write32(__FILE__, __LINE__, priv, ofs, val)
#else
#define iwl_write32(priv, ofs, val) _iwl_write32(priv, ofs, val)
#endif
static inline u32 _iwl_read32(struct iwl_priv *priv, u32 ofs)
static inline u32 iwl_read32(struct iwl_priv *priv, u32 ofs)
{
u32 val = ioread32(priv->hw_base + ofs);
trace_iwlwifi_dev_ioread32(priv, ofs, val);
return val;
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline u32 __iwl_read32(char *f, u32 l, struct iwl_priv *priv, u32 ofs)
{
IWL_DEBUG_IO(priv, "read_direct32(0x%08X) - %s %d\n", ofs, f, l);
return _iwl_read32(priv, ofs);
}
#define iwl_read32(priv, ofs) __iwl_read32(__FILE__, __LINE__, priv, ofs)
#else
#define iwl_read32(p, o) _iwl_read32(p, o)
#endif
#define IWL_POLL_INTERVAL 10 /* microseconds */
static inline int _iwl_poll_bit(struct iwl_priv *priv, u32 addr,
u32 bits, u32 mask, int timeout)
{
int t = 0;
do {
if ((_iwl_read32(priv, addr) & mask) == (bits & mask))
return t;
udelay(IWL_POLL_INTERVAL);
t += IWL_POLL_INTERVAL;
} while (t < timeout);
return -ETIMEDOUT;
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline int __iwl_poll_bit(const char *f, u32 l,
struct iwl_priv *priv, u32 addr,
u32 bits, u32 mask, int timeout)
{
int ret = _iwl_poll_bit(priv, addr, bits, mask, timeout);
IWL_DEBUG_IO(priv, "poll_bit(0x%08X, 0x%08X, 0x%08X) - %s- %s %d\n",
addr, bits, mask,
unlikely(ret == -ETIMEDOUT) ? "timeout" : "", f, l);
return ret;
}
#define iwl_poll_bit(priv, addr, bits, mask, timeout) \
__iwl_poll_bit(__FILE__, __LINE__, priv, addr, bits, mask, timeout)
#else
#define iwl_poll_bit(p, a, b, m, t) _iwl_poll_bit(p, a, b, m, t)
#endif
static inline void _iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
_iwl_write32(priv, reg, _iwl_read32(priv, reg) | mask);
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl_set_bit(const char *f, u32 l,
struct iwl_priv *priv, u32 reg, u32 mask)
{
u32 val = _iwl_read32(priv, reg) | mask;
IWL_DEBUG_IO(priv, "set_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
_iwl_write32(priv, reg, val);
}
static inline void iwl_set_bit(struct iwl_priv *p, u32 r, u32 m)
{
unsigned long reg_flags;
spin_lock_irqsave(&p->reg_lock, reg_flags);
__iwl_set_bit(__FILE__, __LINE__, p, r, m);
spin_unlock_irqrestore(&p->reg_lock, reg_flags);
}
#else
static inline void iwl_set_bit(struct iwl_priv *p, u32 r, u32 m)
{
unsigned long reg_flags;
spin_lock_irqsave(&p->reg_lock, reg_flags);
_iwl_set_bit(p, r, m);
spin_unlock_irqrestore(&p->reg_lock, reg_flags);
}
#endif
static inline void _iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
_iwl_write32(priv, reg, _iwl_read32(priv, reg) & ~mask);
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl_clear_bit(const char *f, u32 l,
struct iwl_priv *priv, u32 reg, u32 mask)
{
u32 val = _iwl_read32(priv, reg) & ~mask;
IWL_DEBUG_IO(priv, "clear_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
_iwl_write32(priv, reg, val);
}
static inline void iwl_clear_bit(struct iwl_priv *p, u32 r, u32 m)
{
unsigned long reg_flags;
spin_lock_irqsave(&p->reg_lock, reg_flags);
__iwl_clear_bit(__FILE__, __LINE__, p, r, m);
spin_unlock_irqrestore(&p->reg_lock, reg_flags);
}
#else
static inline void iwl_clear_bit(struct iwl_priv *p, u32 r, u32 m)
{
unsigned long reg_flags;
spin_lock_irqsave(&p->reg_lock, reg_flags);
_iwl_clear_bit(p, r, m);
spin_unlock_irqrestore(&p->reg_lock, reg_flags);
}
#endif
static inline int _iwl_grab_nic_access(struct iwl_priv *priv)
{
int ret;
u32 val;
/* this bit wakes up the NIC */
_iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
/*
* These bits say the device is running, and should keep running for
* at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
* but they do not indicate that embedded SRAM is restored yet;
* 3945 and 4965 have volatile SRAM, and must save/restore contents
* to/from host DRAM when sleeping/waking for power-saving.
* Each direction takes approximately 1/4 millisecond; with this
* overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
* series of register accesses are expected (e.g. reading Event Log),
* to keep device from sleeping.
*
* CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
* SRAM is okay/restored. We don't check that here because this call
* is just for hardware register access; but GP1 MAC_SLEEP check is a
* good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
*
* 5000 series and later (including 1000 series) have non-volatile SRAM,
* and do not save/restore SRAM when power cycling.
*/
ret = _iwl_poll_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
(CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
if (ret < 0) {
val = _iwl_read32(priv, CSR_GP_CNTRL);
IWL_ERR(priv, "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
_iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
return -EIO;
}
return 0;
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline int __iwl_grab_nic_access(const char *f, u32 l,
struct iwl_priv *priv)
{
IWL_DEBUG_IO(priv, "grabbing nic access - %s %d\n", f, l);
return _iwl_grab_nic_access(priv);
}
#define iwl_grab_nic_access(priv) \
__iwl_grab_nic_access(__FILE__, __LINE__, priv)
#else
#define iwl_grab_nic_access(priv) \
_iwl_grab_nic_access(priv)
#endif
static inline void _iwl_release_nic_access(struct iwl_priv *priv)
{
_iwl_clear_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl_release_nic_access(const char *f, u32 l,
struct iwl_priv *priv)
{
IWL_DEBUG_IO(priv, "releasing nic access - %s %d\n", f, l);
_iwl_release_nic_access(priv);
}
#define iwl_release_nic_access(priv) \
__iwl_release_nic_access(__FILE__, __LINE__, priv)
#else
#define iwl_release_nic_access(priv) \
_iwl_release_nic_access(priv)
#endif
static inline u32 _iwl_read_direct32(struct iwl_priv *priv, u32 reg)
{
return _iwl_read32(priv, reg);
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline u32 __iwl_read_direct32(const char *f, u32 l,
struct iwl_priv *priv, u32 reg)
{
u32 value = _iwl_read_direct32(priv, reg);
IWL_DEBUG_IO(priv, "read_direct32(0x%4X) = 0x%08x - %s %d\n", reg, value,
f, l);
return value;
}
static inline u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg)
{
u32 value;
unsigned long reg_flags;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
iwl_grab_nic_access(priv);
value = __iwl_read_direct32(__FILE__, __LINE__, priv, reg);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
return value;
}
#else
static inline u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg)
{
u32 value;
unsigned long reg_flags;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
iwl_grab_nic_access(priv);
value = _iwl_read_direct32(priv, reg);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
return value;
}
#endif
static inline void _iwl_write_direct32(struct iwl_priv *priv,
u32 reg, u32 value)
{
_iwl_write32(priv, reg, value);
}
static inline void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value)
{
unsigned long reg_flags;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
if (!iwl_grab_nic_access(priv)) {
_iwl_write_direct32(priv, reg, value);
iwl_release_nic_access(priv);
}
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
}
static inline void iwl_write_reg_buf(struct iwl_priv *priv,
u32 reg, u32 len, u32 *values)
{
u32 count = sizeof(u32);
if ((priv != NULL) && (values != NULL)) {
for (; 0 < len; len -= count, reg += count, values++)
iwl_write_direct32(priv, reg, *values);
}
}
static inline int _iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr,
u32 mask, int timeout)
{
int t = 0;
do {
if ((iwl_read_direct32(priv, addr) & mask) == mask)
return t;
udelay(IWL_POLL_INTERVAL);
t += IWL_POLL_INTERVAL;
} while (t < timeout);
return -ETIMEDOUT;
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline int __iwl_poll_direct_bit(const char *f, u32 l,
struct iwl_priv *priv,
u32 addr, u32 mask, int timeout)
{
int ret = _iwl_poll_direct_bit(priv, addr, mask, timeout);
if (unlikely(ret == -ETIMEDOUT))
IWL_DEBUG_IO(priv, "poll_direct_bit(0x%08X, 0x%08X) - "
"timedout - %s %d\n", addr, mask, f, l);
else
IWL_DEBUG_IO(priv, "poll_direct_bit(0x%08X, 0x%08X) = 0x%08X "
"- %s %d\n", addr, mask, ret, f, l);
return ret;
}
#define iwl_poll_direct_bit(priv, addr, mask, timeout) \
__iwl_poll_direct_bit(__FILE__, __LINE__, priv, addr, mask, timeout)
#else
#define iwl_poll_direct_bit _iwl_poll_direct_bit
#endif
static inline u32 _iwl_read_prph(struct iwl_priv *priv, u32 reg)
{
_iwl_write_direct32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
rmb();
return _iwl_read_direct32(priv, HBUS_TARG_PRPH_RDAT);
}
static inline u32 iwl_read_prph(struct iwl_priv *priv, u32 reg)
{
unsigned long reg_flags;
u32 val;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
iwl_grab_nic_access(priv);
val = _iwl_read_prph(priv, reg);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
return val;
}
static inline void _iwl_write_prph(struct iwl_priv *priv,
u32 addr, u32 val)
{
_iwl_write_direct32(priv, HBUS_TARG_PRPH_WADDR,
((addr & 0x0000FFFF) | (3 << 24)));
wmb();
_iwl_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val);
}
static inline void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
{
unsigned long reg_flags;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
if (!iwl_grab_nic_access(priv)) {
_iwl_write_prph(priv, addr, val);
iwl_release_nic_access(priv);
}
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
}
#define _iwl_set_bits_prph(priv, reg, mask) \
_iwl_write_prph(priv, reg, (_iwl_read_prph(priv, reg) | mask))
static inline void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
{
unsigned long reg_flags;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
iwl_grab_nic_access(priv);
_iwl_set_bits_prph(priv, reg, mask);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
}
#define _iwl_set_bits_mask_prph(priv, reg, bits, mask) \
_iwl_write_prph(priv, reg, ((_iwl_read_prph(priv, reg) & mask) | bits))
static inline void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg,
u32 bits, u32 mask)
{
unsigned long reg_flags;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
iwl_grab_nic_access(priv);
_iwl_set_bits_mask_prph(priv, reg, bits, mask);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
}
static inline void iwl_clear_bits_prph(struct iwl_priv
*priv, u32 reg, u32 mask)
{
unsigned long reg_flags;
u32 val;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
iwl_grab_nic_access(priv);
val = _iwl_read_prph(priv, reg);
_iwl_write_prph(priv, reg, (val & ~mask));
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
}
static inline u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
{
unsigned long reg_flags;
u32 value;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
iwl_grab_nic_access(priv);
_iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr);
rmb();
value = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
return value;
}
static inline void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
{
unsigned long reg_flags;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
if (!iwl_grab_nic_access(priv)) {
_iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
wmb();
_iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, val);
iwl_release_nic_access(priv);
}
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
}
static inline void iwl_write_targ_mem_buf(struct iwl_priv *priv, u32 addr,
u32 len, u32 *values)
{
unsigned long reg_flags;
spin_lock_irqsave(&priv->reg_lock, reg_flags);
if (!iwl_grab_nic_access(priv)) {
_iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
wmb();
for (; 0 < len; len -= sizeof(u32), values++)
_iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values);
iwl_release_nic_access(priv);
}
spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
}
void iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask);
void iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask);
int iwl_poll_bit(struct iwl_priv *priv, u32 addr,
u32 bits, u32 mask, int timeout);
int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask,
int timeout);
int iwl_grab_nic_access(struct iwl_priv *priv);
void iwl_release_nic_access(struct iwl_priv *priv);
u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg);
void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value);
u32 iwl_read_prph(struct iwl_priv *priv, u32 reg);
void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val);
void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask);
void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg,
u32 bits, u32 mask);
void iwl_clear_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask);
u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr);
void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val);
#endif

2
drivers/net/wireless/iwlwifi/iwl-led.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/iwl-led.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/iwl-power.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

2
drivers/net/wireless/iwlwifi/iwl-power.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

342
drivers/net/wireless/iwlwifi/iwl-prph.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -91,159 +91,12 @@
#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */
#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
/**
* BSM (Bootstrap State Machine)
*
* The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
* in special SRAM that does not power down when the embedded control
* processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
*
* When powering back up after sleeps (or during initial uCode load), the BSM
* internally loads the short bootstrap program from the special SRAM into the
* embedded processor's instruction SRAM, and starts the processor so it runs
* the bootstrap program.
*
* This bootstrap program loads (via PCI busmaster DMA) instructions and data
* images for a uCode program from host DRAM locations. The host driver
* indicates DRAM locations and sizes for instruction and data images via the
* four BSM_DRAM_* registers. Once the bootstrap program loads the new program,
* the new program starts automatically.
*
* The uCode used for open-source drivers includes two programs:
*
* 1) Initialization -- performs hardware calibration and sets up some
* internal data, then notifies host via "initialize alive" notification
* (struct iwl_init_alive_resp) that it has completed all of its work.
* After signal from host, it then loads and starts the runtime program.
* The initialization program must be used when initially setting up the
* NIC after loading the driver.
*
* 2) Runtime/Protocol -- performs all normal runtime operations. This
* notifies host via "alive" notification (struct iwl_alive_resp) that it
* is ready to be used.
*
* When initializing the NIC, the host driver does the following procedure:
*
* 1) Load bootstrap program (instructions only, no data image for bootstrap)
* into bootstrap memory. Use dword writes starting at BSM_SRAM_LOWER_BOUND
*
* 2) Point (via BSM_DRAM_*) to the "initialize" uCode data and instruction
* images in host DRAM.
*
* 3) Set up BSM to copy from BSM SRAM into uCode instruction SRAM when asked:
* BSM_WR_MEM_SRC_REG = 0
* BSM_WR_MEM_DST_REG = RTC_INST_LOWER_BOUND
* BSM_WR_MEM_DWCOUNT_REG = # dwords in bootstrap instruction image
*
* 4) Load bootstrap into instruction SRAM:
* BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START
*
* 5) Wait for load completion:
* Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0
*
* 6) Enable future boot loads whenever NIC's power management triggers it:
* BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START_EN
*
* 7) Start the NIC by removing all reset bits:
* CSR_RESET = 0
*
* The bootstrap uCode (already in instruction SRAM) loads initialization
* uCode. Initialization uCode performs data initialization, sends
* "initialize alive" notification to host, and waits for a signal from
* host to load runtime code.
*
* 4) Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction
* images in host DRAM. The last register loaded must be the instruction
* byte count register ("1" in MSbit tells initialization uCode to load
* the runtime uCode):
* BSM_DRAM_INST_BYTECOUNT_REG = byte count | BSM_DRAM_INST_LOAD
*
* 5) Wait for "alive" notification, then issue normal runtime commands.
*
* Data caching during power-downs:
*
* Just before the embedded controller powers down (e.g for automatic
* power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA)
* a current snapshot of the embedded processor's data SRAM into host DRAM.
* This caches the data while the embedded processor's memory is powered down.
* Location and size are controlled by BSM_DRAM_DATA_* registers.
*
* NOTE: Instruction SRAM does not need to be saved, since that doesn't
* change during operation; the original image (from uCode distribution
* file) can be used for reload.
*
* When powering back up, the BSM loads the bootstrap program. Bootstrap looks
* at the BSM_DRAM_* registers, which now point to the runtime instruction
* image and the cached (modified) runtime data (*not* the initialization
* uCode). Bootstrap reloads these runtime images into SRAM, and restarts the
* uCode from where it left off before the power-down.
*
* NOTE: Initialization uCode does *not* run as part of the save/restore
* procedure.
*
* This save/restore method is mostly for autonomous power management during
* normal operation (result of POWER_TABLE_CMD). Platform suspend/resume and
* RFKILL should use complete restarts (with total re-initialization) of uCode,
* allowing total shutdown (including BSM memory).
*
* Note that, during normal operation, the host DRAM that held the initial
* startup data for the runtime code is now being used as a backup data cache
* for modified data! If you need to completely re-initialize the NIC, make
* sure that you use the runtime data image from the uCode distribution file,
* not the modified/saved runtime data. You may want to store a separate
* "clean" runtime data image in DRAM to avoid disk reads of distribution file.
*/
/* BSM bit fields */
#define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */
#define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup*/
#define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */
/* BSM addresses */
#define BSM_BASE (PRPH_BASE + 0x3400)
#define BSM_END (PRPH_BASE + 0x3800)
#define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */
#define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */
#define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */
#define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */
#define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */
/*
* Pointers and size regs for bootstrap load and data SRAM save/restore.
* NOTE: 3945 pointers use bits 31:0 of DRAM address.
* 4965 pointers use bits 35:4 of DRAM address.
*/
#define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090)
#define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094)
#define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098)
#define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C)
/*
* BSM special memory, stays powered on during power-save sleeps.
* Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1)
*/
#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
#define BSM_SRAM_SIZE (1024) /* bytes */
/* 3945 Tx scheduler registers */
#define ALM_SCD_BASE (PRPH_BASE + 0x2E00)
#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)
#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)
#define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010)
#define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014)
#define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020)
#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
/**
* Tx Scheduler
*
@ -330,201 +183,10 @@
* Max Tx window size is the max number of contiguous TFDs that the scheduler
* can keep track of at one time when creating block-ack chains of frames.
* Note that "64" matches the number of ack bits in a block-ack packet.
* Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize
* IWL49_SCD_CONTEXT_QUEUE_OFFSET(x) values.
*/
#define SCD_WIN_SIZE 64
#define SCD_FRAME_LIMIT 64
/* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */
#define IWL49_SCD_START_OFFSET 0xa02c00
/*
* 4965 tells driver SRAM address for internal scheduler structs via this reg.
* Value is valid only after "Alive" response from uCode.
*/
#define IWL49_SCD_SRAM_BASE_ADDR (IWL49_SCD_START_OFFSET + 0x0)
/*
* Driver may need to update queue-empty bits after changing queue's
* write and read pointers (indexes) during (re-)initialization (i.e. when
* scheduler is not tracking what's happening).
* Bit fields:
* 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit
* 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty
* NOTE: This register is not used by Linux driver.
*/
#define IWL49_SCD_EMPTY_BITS (IWL49_SCD_START_OFFSET + 0x4)
/*
* Physical base address of array of byte count (BC) circular buffers (CBs).
* Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode.
* This register points to BC CB for queue 0, must be on 1024-byte boundary.
* Others are spaced by 1024 bytes.
* Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad.
* (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff).
* Bit fields:
* 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned.
*/
#define IWL49_SCD_DRAM_BASE_ADDR (IWL49_SCD_START_OFFSET + 0x10)
/*
* Enables any/all Tx DMA/FIFO channels.
* Scheduler generates requests for only the active channels.
* Set this to 0xff to enable all 8 channels (normal usage).
* Bit fields:
* 7- 0: Enable (1), disable (0), one bit for each channel 0-7
*/
#define IWL49_SCD_TXFACT (IWL49_SCD_START_OFFSET + 0x1c)
/*
* Queue (x) Write Pointers (indexes, really!), one for each Tx queue.
* Initialized and updated by driver as new TFDs are added to queue.
* NOTE: If using Block Ack, index must correspond to frame's
* Start Sequence Number; index = (SSN & 0xff)
* NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses?
*/
#define IWL49_SCD_QUEUE_WRPTR(x) (IWL49_SCD_START_OFFSET + 0x24 + (x) * 4)
/*
* Queue (x) Read Pointers (indexes, really!), one for each Tx queue.
* For FIFO mode, index indicates next frame to transmit.
* For Scheduler-ACK mode, index indicates first frame in Tx window.
* Initialized by driver, updated by scheduler.
*/
#define IWL49_SCD_QUEUE_RDPTR(x) (IWL49_SCD_START_OFFSET + 0x64 + (x) * 4)
/*
* Select which queues work in chain mode (1) vs. not (0).
* Use chain mode to build chains of aggregated frames.
* Bit fields:
* 31-16: Reserved
* 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time
* NOTE: If driver sets up queue for chain mode, it should be also set up
* Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x).
*/
#define IWL49_SCD_QUEUECHAIN_SEL (IWL49_SCD_START_OFFSET + 0xd0)
/*
* Select which queues interrupt driver when scheduler increments
* a queue's read pointer (index).
* Bit fields:
* 31-16: Reserved
* 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled
* NOTE: This functionality is apparently a no-op; driver relies on interrupts
* from Rx queue to read Tx command responses and update Tx queues.
*/
#define IWL49_SCD_INTERRUPT_MASK (IWL49_SCD_START_OFFSET + 0xe4)
/*
* Queue search status registers. One for each queue.
* Sets up queue mode and assigns queue to Tx DMA channel.
* Bit fields:
* 19-10: Write mask/enable bits for bits 0-9
* 9: Driver should init to "0"
* 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).
* Driver should init to "1" for aggregation mode, or "0" otherwise.
* 7-6: Driver should init to "0"
* 5: Window Size Left; indicates whether scheduler can request
* another TFD, based on window size, etc. Driver should init
* this bit to "1" for aggregation mode, or "0" for non-agg.
* 4-1: Tx FIFO to use (range 0-7).
* 0: Queue is active (1), not active (0).
* Other bits should be written as "0"
*
* NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled
* via SCD_QUEUECHAIN_SEL.
*/
#define IWL49_SCD_QUEUE_STATUS_BITS(x)\
(IWL49_SCD_START_OFFSET + 0x104 + (x) * 4)
/* Bit field positions */
#define IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
#define IWL49_SCD_QUEUE_STTS_REG_POS_TXF (1)
#define IWL49_SCD_QUEUE_STTS_REG_POS_WSL (5)
#define IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)
/* Write masks */
#define IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)
#define IWL49_SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
/**
* 4965 internal SRAM structures for scheduler, shared with driver ...
*
* Driver should clear and initialize the following areas after receiving
* "Alive" response from 4965 uCode, i.e. after initial
* uCode load, or after a uCode load done for error recovery:
*
* SCD_CONTEXT_DATA_OFFSET (size 128 bytes)
* SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes)
* SCD_TRANSLATE_TBL_OFFSET (size 32 bytes)
*
* Driver accesses SRAM via HBUS_TARG_MEM_* registers.
* Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR.
* All OFFSET values must be added to this base address.
*/
/*
* Queue context. One 8-byte entry for each of 16 queues.
*
* Driver should clear this entire area (size 0x80) to 0 after receiving
* "Alive" notification from uCode. Additionally, driver should init
* each queue's entry as follows:
*
* LS Dword bit fields:
* 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64.
*
* MS Dword bit fields:
* 16-22: Frame limit. Driver should init to 10 (0xa).
*
* Driver should init all other bits to 0.
*
* Init must be done after driver receives "Alive" response from 4965 uCode,
* and when setting up queue for aggregation.
*/
#define IWL49_SCD_CONTEXT_DATA_OFFSET 0x380
#define IWL49_SCD_CONTEXT_QUEUE_OFFSET(x) \
(IWL49_SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
#define IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
#define IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
#define IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
#define IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
/*
* Tx Status Bitmap
*
* Driver should clear this entire area (size 0x100) to 0 after receiving
* "Alive" notification from uCode. Area is used only by device itself;
* no other support (besides clearing) is required from driver.
*/
#define IWL49_SCD_TX_STTS_BITMAP_OFFSET 0x400
/*
* RAxTID to queue translation mapping.
*
* When queue is in Scheduler-ACK mode, frames placed in a that queue must be
* for only one combination of receiver address (RA) and traffic ID (TID), i.e.
* one QOS priority level destined for one station (for this wireless link,
* not final destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit
* mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK
* mode, the device ignores the mapping value.
*
* Bit fields, for each 16-bit map:
* 15-9: Reserved, set to 0
* 8-4: Index into device's station table for recipient station
* 3-0: Traffic ID (tid), range 0-15
*
* Driver should clear this entire area (size 32 bytes) to 0 after receiving
* "Alive" notification from uCode. To update a 16-bit map value, driver
* must read a dword-aligned value from device SRAM, replace the 16-bit map
* value of interest, and write the dword value back into device SRAM.
*/
#define IWL49_SCD_TRANSLATE_TBL_OFFSET 0x500
/* Find translation table dword to read/write for given queue */
#define IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
((IWL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
#define IWL_SCD_TXFIFO_POS_TID (0)
#define IWL_SCD_TXFIFO_POS_RA (4)
#define IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)

13
drivers/net/wireless/iwlwifi/iwl-rx.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.
@ -239,16 +239,16 @@ static void iwl_rx_reply_alive(struct iwl_priv *priv,
palive->is_valid, palive->ver_type,
palive->ver_subtype);
priv->device_pointers.log_event_table =
le32_to_cpu(palive->log_event_table_ptr);
priv->device_pointers.error_event_table =
le32_to_cpu(palive->error_event_table_ptr);
if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
memcpy(&priv->card_alive_init,
&pkt->u.alive_frame,
sizeof(struct iwl_init_alive_resp));
pwork = &priv->init_alive_start;
} else {
IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
memcpy(&priv->card_alive, &pkt->u.alive_frame,
sizeof(struct iwl_alive_resp));
pwork = &priv->alive_start;
}
@ -898,7 +898,6 @@ static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
ieee80211_rx(priv->hw, skb);
priv->alloc_rxb_page--;
rxb->page = NULL;
}

2
drivers/net/wireless/iwlwifi/iwl-scan.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/iwl-spectrum.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ieee80211 subsystem header files.
*

9
drivers/net/wireless/iwlwifi/iwl-sta.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.
@ -233,7 +233,6 @@ u8 iwl_prep_station(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
struct iwl_station_entry *station;
int i;
u8 sta_id = IWL_INVALID_STATION;
u16 rate;
if (is_ap)
sta_id = ctx->ap_sta_id;
@ -306,12 +305,6 @@ u8 iwl_prep_station(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
*/
iwl_set_ht_add_station(priv, sta_id, sta, ctx);
/* 3945 only */
rate = (priv->band == IEEE80211_BAND_5GHZ) ?
IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP;
/* Turn on both antennas for the station... */
station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
return sta_id;
}

Some files were not shown because too many files have changed in this diff Show More