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PCI: tegra: Program UPHY electrical settings for Tegra210 

UPHY electrical programming guidelines are documented in Tegra210 TRM.
Program these electrical settings for proper eye diagram in Gen1 and Gen2
link speeds.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Manikanta Maddireddy 2019-06-18 23:31:47 +05:30 committed by Lorenzo Pieralisi
parent c635a815c8
commit 2513a4ee47
1 changed files with 107 additions and 0 deletions
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107
drivers/pci/controller/pci-tegra.c
View File

@ -177,6 +177,32 @@
#define AFI_PEXBIAS_CTRL_0 0x168
#define RP_ECTL_2_R1 0x00000e84
#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff
#define RP_ECTL_4_R1 0x00000e8c
#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK (0xffff << 16)
#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT 16
#define RP_ECTL_5_R1 0x00000e90
#define RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK 0xffffffff
#define RP_ECTL_6_R1 0x00000e94
#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK 0xffffffff
#define RP_ECTL_2_R2 0x00000ea4
#define RP_ECTL_2_R2_RX_CTLE_1C_MASK 0xffff
#define RP_ECTL_4_R2 0x00000eac
#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK (0xffff << 16)
#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT 16
#define RP_ECTL_5_R2 0x00000eb0
#define RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK 0xffffffff
#define RP_ECTL_6_R2 0x00000eb4
#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff
#define RP_VEND_XP 0x00000f00
#define RP_VEND_XP_DL_UP (1 << 30)
@ -266,6 +292,19 @@ struct tegra_pcie_soc {
bool has_gen2;
bool force_pca_enable;
bool program_uphy;
struct {
struct {
u32 rp_ectl_2_r1;
u32 rp_ectl_4_r1;
u32 rp_ectl_5_r1;
u32 rp_ectl_6_r1;
u32 rp_ectl_2_r2;
u32 rp_ectl_4_r2;
u32 rp_ectl_5_r2;
u32 rp_ectl_6_r2;
} regs;
bool enable;
} ectl;
};
static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@ -492,6 +531,54 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
writel(value, port->base + RP_VEND_CTL1);
}
static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
{
const struct tegra_pcie_soc *soc = port->pcie->soc;
u32 value;
value = readl(port->base + RP_ECTL_2_R1);
value &= ~RP_ECTL_2_R1_RX_CTLE_1C_MASK;
value |= soc->ectl.regs.rp_ectl_2_r1;
writel(value, port->base + RP_ECTL_2_R1);
value = readl(port->base + RP_ECTL_4_R1);
value &= ~RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK;
value |= soc->ectl.regs.rp_ectl_4_r1 <<
RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT;
writel(value, port->base + RP_ECTL_4_R1);
value = readl(port->base + RP_ECTL_5_R1);
value &= ~RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK;
value |= soc->ectl.regs.rp_ectl_5_r1;
writel(value, port->base + RP_ECTL_5_R1);
value = readl(port->base + RP_ECTL_6_R1);
value &= ~RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK;
value |= soc->ectl.regs.rp_ectl_6_r1;
writel(value, port->base + RP_ECTL_6_R1);
value = readl(port->base + RP_ECTL_2_R2);
value &= ~RP_ECTL_2_R2_RX_CTLE_1C_MASK;
value |= soc->ectl.regs.rp_ectl_2_r2;
writel(value, port->base + RP_ECTL_2_R2);
value = readl(port->base + RP_ECTL_4_R2);
value &= ~RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK;
value |= soc->ectl.regs.rp_ectl_4_r2 <<
RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT;
writel(value, port->base + RP_ECTL_4_R2);
value = readl(port->base + RP_ECTL_5_R2);
value &= ~RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK;
value |= soc->ectl.regs.rp_ectl_5_r2;
writel(value, port->base + RP_ECTL_5_R2);
value = readl(port->base + RP_ECTL_6_R2);
value &= ~RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK;
value |= soc->ectl.regs.rp_ectl_6_r2;
writel(value, port->base + RP_ECTL_6_R2);
}
static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
{
unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
@ -518,6 +605,9 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
}
tegra_pcie_enable_rp_features(port);
if (soc->ectl.enable)
tegra_pcie_program_ectl_settings(port);
}
static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
@ -2242,6 +2332,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.has_gen2 = false,
.force_pca_enable = false,
.program_uphy = true,
.ectl.enable = false,
};
static const struct tegra_pcie_port_soc tegra30_pcie_ports[] = {
@ -2265,6 +2356,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
.has_gen2 = false,
.force_pca_enable = false,
.program_uphy = true,
.ectl.enable = false,
};
static const struct tegra_pcie_soc tegra124_pcie = {
@ -2281,6 +2373,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
.has_gen2 = true,
.force_pca_enable = false,
.program_uphy = true,
.ectl.enable = false,
};
static const struct tegra_pcie_soc tegra210_pcie = {
@ -2297,6 +2390,19 @@ static const struct tegra_pcie_soc tegra210_pcie = {
.has_gen2 = true,
.force_pca_enable = true,
.program_uphy = true,
.ectl = {
.regs = {
.rp_ectl_2_r1 = 0x0000000f,
.rp_ectl_4_r1 = 0x00000067,
.rp_ectl_5_r1 = 0x55010000,
.rp_ectl_6_r1 = 0x00000001,
.rp_ectl_2_r2 = 0x0000008f,
.rp_ectl_4_r2 = 0x000000c7,
.rp_ectl_5_r2 = 0x55010000,
.rp_ectl_6_r2 = 0x00000001,
},
.enable = true,
},
};
static const struct tegra_pcie_port_soc tegra186_pcie_ports[] = {
@ -2320,6 +2426,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
.has_gen2 = true,
.force_pca_enable = false,
.program_uphy = false,
.ectl.enable = false,
};
static const struct of_device_id tegra_pcie_of_match[] = {