Blackfin arch: Allow ins functions to have a low latency version
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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@ -622,6 +622,33 @@ config CPLB_SWITCH_TAB_L1
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If enabled, the CPLB Switch Tables are linked
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If enabled, the CPLB Switch Tables are linked
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into L1 data memory. (less latency)
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into L1 data memory. (less latency)
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comment "Speed Optimizations"
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config BFIN_INS_LOWOVERHEAD
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bool "ins[bwl] low overhead, higher interrupt latency"
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default y
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help
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Reads on the Blackfin are speculative. In Blackfin terms, this means
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they can be interrupted at any time (even after they have been issued
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on to the external bus), and re-issued after the interrupt occurs.
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For memory - this is not a big deal, since memory does not change if
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it sees a read.
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If a FIFO is sitting on the end of the read, it will see two reads,
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when the core only sees one since the FIFO receives both the read
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which is cancelled (and not delivered to the core) and the one which
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is re-issued (which is delivered to the core).
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To solve this, interrupts are turned off before reads occur to
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I/O space. This option controls which the overhead/latency of
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controlling interrupts during this time
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"n" turns interrupts off every read
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(higher overhead, but lower interrupt latency)
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"y" turns interrupts off every loop
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(low overhead, but longer interrupt latency)
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default behavior is to leave this set to on (type "Y"). If you are experiencing
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interrupt latency issues, it is safe and OK to turn this off.
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endmenu
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endmenu
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@ -33,7 +33,28 @@
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.align 2
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.align 2
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/*
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* Reads on the Blackfin are speculative. In Blackfin terms, this means they
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* can be interrupted at any time (even after they have been issued on to the
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* external bus), and re-issued after the interrupt occurs.
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*
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* If a FIFO is sitting on the end of the read, it will see two reads,
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* when the core only sees one. The FIFO receives the read which is cancelled,
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* and not delivered to the core.
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*
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* To solve this, interrupts are turned off before reads occur to I/O space.
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* There are 3 versions of all these functions
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* - turns interrupts off every read (higher overhead, but lower latency)
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* - turns interrupts off every loop (low overhead, but longer latency)
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* - DMA version, which do not suffer from this issue. DMA versions have
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* different name (prefixed by dma_ ), and are located in
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* ../kernel/bfin_dma_5xx.c
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* Using the dma related functions are recommended for transfering large
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* buffers in/out of FIFOs.
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*/
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ENTRY(_insl)
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ENTRY(_insl)
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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P0 = R0; /* P0 = port */
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P0 = R0; /* P0 = port */
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cli R3;
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cli R3;
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P1 = R1; /* P1 = address */
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P1 = R1; /* P1 = address */
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@ -46,9 +67,26 @@ ENTRY(_insl)
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.Llong_loop_e: NOP;
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.Llong_loop_e: NOP;
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sti R3;
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sti R3;
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RTS;
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RTS;
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#else
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
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.Llong_loop_s:
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CLI R3;
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NOP; NOP; NOP;
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R0 = [P0];
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[P1++] = R0;
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.Llong_loop_e:
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STI R3;
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RTS;
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#endif
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ENDPROC(_insl)
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ENDPROC(_insl)
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ENTRY(_insw)
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ENTRY(_insw)
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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P0 = R0; /* P0 = port */
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P0 = R0; /* P0 = port */
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cli R3;
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cli R3;
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P1 = R1; /* P1 = address */
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P1 = R1; /* P1 = address */
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@ -61,9 +99,26 @@ ENTRY(_insw)
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.Lword_loop_e: NOP;
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.Lword_loop_e: NOP;
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sti R3;
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sti R3;
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RTS;
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RTS;
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#else
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
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.Lword_loop_s:
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CLI R3;
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NOP; NOP; NOP;
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R0 = W[P0];
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W[P1++] = R0;
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.Lword_loop_e:
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STI R3;
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RTS;
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#endif
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ENDPROC(_insw)
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ENDPROC(_insw)
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ENTRY(_insw_8)
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ENTRY(_insw_8)
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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P0 = R0; /* P0 = port */
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P0 = R0; /* P0 = port */
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cli R3;
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cli R3;
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P1 = R1; /* P1 = address */
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P1 = R1; /* P1 = address */
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@ -78,9 +133,29 @@ ENTRY(_insw_8)
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.Lword8_loop_e: NOP;
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.Lword8_loop_e: NOP;
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sti R3;
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sti R3;
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RTS;
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RTS;
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#else
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
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.Lword8_loop_s:
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CLI R3;
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NOP; NOP; NOP;
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R0 = W[P0];
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B[P1++] = R0;
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R0 = R0 >> 8;
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B[P1++] = R0;
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NOP;
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.Lword8_loop_e:
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STI R3;
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RTS;
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#endif
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ENDPROC(_insw_8)
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ENDPROC(_insw_8)
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ENTRY(_insb)
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ENTRY(_insb)
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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P0 = R0; /* P0 = port */
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P0 = R0; /* P0 = port */
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cli R3;
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cli R3;
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P1 = R1; /* P1 = address */
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P1 = R1; /* P1 = address */
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@ -93,9 +168,26 @@ ENTRY(_insb)
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.Lbyte_loop_e: NOP;
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.Lbyte_loop_e: NOP;
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sti R3;
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sti R3;
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RTS;
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RTS;
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#else
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
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.Lbyte_loop_s:
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CLI R3;
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NOP; NOP; NOP;
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R0 = B[P0];
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B[P1++] = R0;
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.Lbyte_loop_e:
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STI R3;
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RTS;
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#endif
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ENDPROC(_insb)
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ENDPROC(_insb)
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ENTRY(_insl_16)
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ENTRY(_insl_16)
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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P0 = R0; /* P0 = port */
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P0 = R0; /* P0 = port */
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cli R3;
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cli R3;
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P1 = R1; /* P1 = address */
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P1 = R1; /* P1 = address */
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@ -110,4 +202,21 @@ ENTRY(_insl_16)
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.Llong16_loop_e: NOP;
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.Llong16_loop_e: NOP;
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sti R3;
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sti R3;
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RTS;
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RTS;
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#else
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Llong16_loop_s, .Llong16_loop_e) LC0 = P2;
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.Llong16_loop_s:
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CLI R3;
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NOP; NOP; NOP;
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R0 = [P0];
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W[P1++] = R0;
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R0 = R0 >> 16;
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W[P1++] = R0;
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.Llong16_loop_e:
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STI R3;
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RTS;
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#endif
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ENDPROC(_insl_16)
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ENDPROC(_insl_16)
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