hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option 

Use a new config option to enable TX49XX I-cache index invalidate
workaround and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer 2020-08-24 18:32:47 +02:00
parent 142439b052
commit 24a1c023f3
15 changed files with 12 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/mips/Kconfig
View File

@ -890,6 +890,7 @@ config MACH_TX39XX
config MACH_TX49XX
bool "Toshiba TX49 series based machines"
select WAR_TX49XX_ICACHE_INDEX_INV
config MIKROTIK_RB532
bool "Mikrotik RB532 boards"
@ -2657,6 +2658,14 @@ config WAR_R4600_V1_HIT_CACHEOP
config WAR_R4600_V2_HIT_CACHEOP
bool
# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
# the line which this instruction itself exists, the following
# operation is not guaranteed."
#
# Workaround: do two phase flushing for Index_Invalidate_I
config WAR_TX49XX_ICACHE_INDEX_INV
bool
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed

1
arch/mips/include/asm/mach-cavium-octeon/war.h
View File

@ -11,7 +11,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0

1
arch/mips/include/asm/mach-generic/war.h
View File

@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0

1
arch/mips/include/asm/mach-ip22/war.h
View File

@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0

1
arch/mips/include/asm/mach-ip27/war.h
View File

@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0

1
arch/mips/include/asm/mach-ip28/war.h
View File

@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0

1
arch/mips/include/asm/mach-ip30/war.h
View File

@ -7,7 +7,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#ifdef CONFIG_CPU_R10000
#define R10000_LLSC_WAR 1

1
arch/mips/include/asm/mach-ip32/war.h
View File

@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0

1
arch/mips/include/asm/mach-malta/war.h
View File

@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0

1
arch/mips/include/asm/mach-rc32434/war.h
View File

@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0

1
arch/mips/include/asm/mach-rm/war.h
View File

@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0

1
arch/mips/include/asm/mach-sibyte/war.h
View File

@ -24,7 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
#endif
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0

1
arch/mips/include/asm/mach-tx49xx/war.h
View File

@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 1
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0

11
arch/mips/include/asm/war.h
View File

@ -93,17 +93,6 @@
#error Check setting of SIBYTE_1956_WAR for your platform
#endif
/*
* From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
* the line which this instruction itself exists, the following
* operation is not guaranteed."
*
* Workaround: do two phase flushing for Index_Invalidate_I
*/
#ifndef TX49XX_ICACHE_INDEX_INV_WAR
#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
#endif
/*
* The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
* opposes it being called that) where invalid instructions in the same

6
arch/mips/mm/c-r4k.c
View File

@ -239,7 +239,7 @@ static void r4k_blast_dcache_setup(void)
r4k_blast_dcache = blast_dcache128;
}
/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
/* force code alignment (used for CONFIG_WAR_TX49XX_ICACHE_INDEX_INV) */
#define JUMP_TO_ALIGN(order) \
__asm__ __volatile__( \
"b\t1f\n\t" \
@ -371,7 +371,7 @@ static void r4k_blast_icache_page_indexed_setup(void)
cpu_is_r4600_v1_x())
r4k_blast_icache_page_indexed =
blast_icache32_r4600_v1_page_indexed;
else if (TX49XX_ICACHE_INDEX_INV_WAR)
else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
r4k_blast_icache_page_indexed =
tx49_blast_icache32_page_indexed;
else if (current_cpu_type() == CPU_LOONGSON2EF)
@ -399,7 +399,7 @@ static void r4k_blast_icache_setup(void)
if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
cpu_is_r4600_v1_x())
r4k_blast_icache = blast_r4600_v1_icache32;
else if (TX49XX_ICACHE_INDEX_INV_WAR)
else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
r4k_blast_icache = tx49_blast_icache32;
else if (current_cpu_type() == CPU_LOONGSON2EF)
r4k_blast_icache = loongson2_blast_icache32;