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Blackfin arch: initial supporting for BF548-EZKIT 

The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia
applications where system performance and cost are essential ingredients. The
integration of multimedia, human interface, and connectivity peripherals combined
with increased system bandwidth and on-chip memory provides customers a platform to
design the most demanding applications.

Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers
such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will
be submitted later.

Please enjoy the show.

Signed-off-by: Roy Huang <roy.huang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Roy Huang 2007-07-12 22:41:45 +08:00 committed by Bryan Wu
parent 088eec1192
commit 24a07a1241
40 changed files with 2761 additions and 2905 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
arch/blackfin/Kconfig
View File

@ -71,6 +71,7 @@ config GENERIC_CALIBRATE_DELAY
config IRQCHIP_DEMUX_GPIO config IRQCHIP_DEMUX_GPIO
bool bool
depends on (BF53x || BF561)
default y default y
source "init/Kconfig" source "init/Kconfig"
@ -114,6 +115,26 @@ config BF537
help help
BF537 Processor Support. BF537 Processor Support.
config BF542
bool "BF542"
help
BF542 Processor Support.
config BF544
bool "BF544"
help
BF544 Processor Support.
config BF548
bool "BF548"
help
BF548 Processor Support.
config BF549
bool "BF549"
help
BF549 Processor Support.
config BF561 config BF561
bool "BF561" bool "BF561"
help help
@ -125,6 +146,11 @@ choice
prompt "Silicon Rev" prompt "Silicon Rev"
default BF_REV_0_2 if BF537 default BF_REV_0_2 if BF537
default BF_REV_0_3 if BF533 default BF_REV_0_3 if BF533
default BF_REV_0_0 if BF549
config BF_REV_0_0
bool "0.0"
depends on (BF549)
config BF_REV_0_2 config BF_REV_0_2
bool "0.2" bool "0.2"
@ -150,6 +176,16 @@ config BF_REV_NONE
endchoice endchoice
config BF53x
bool
depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
default y
config BF54x
bool
depends on (BF542 || BF544 || BF548 || BF549)
default y
config BFIN_DUAL_CORE config BFIN_DUAL_CORE
bool bool
depends on (BF561) depends on (BF561)
@ -198,6 +234,12 @@ config BFIN537_BLUETECHNIX_CM
help help
CM-BF537 support for EVAL- and DEV-Board. CM-BF537 support for EVAL- and DEV-Board.
config BFIN548_EZKIT
bool "BF548-EZKIT"
depends on (BF548 || BF549)
help
BFIN548-EZKIT board Support.
config BFIN561_BLUETECHNIX_CM config BFIN561_BLUETECHNIX_CM
bool "Bluetechnix CM-BF561" bool "Bluetechnix CM-BF561"
depends on (BF561) depends on (BF561)
@ -265,6 +307,7 @@ config BFIN_SHARED_FLASH_ENET
source "arch/blackfin/mach-bf533/Kconfig" source "arch/blackfin/mach-bf533/Kconfig"
source "arch/blackfin/mach-bf561/Kconfig" source "arch/blackfin/mach-bf561/Kconfig"
source "arch/blackfin/mach-bf537/Kconfig" source "arch/blackfin/mach-bf537/Kconfig"
source "arch/blackfin/mach-bf548/Kconfig"
menu "Board customizations" menu "Board customizations"
@ -543,7 +586,7 @@ source "mm/Kconfig"
config BFIN_DMA_5XX config BFIN_DMA_5XX
bool "Enable DMA Support" bool "Enable DMA Support"
depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561) depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x)
default y default y
help help
DMA driver for BF5xx. DMA driver for BF5xx.
@ -839,7 +882,7 @@ endchoice
endmenu endmenu
if (BF537 || BF533) if (BF537 || BF533 || BF54x)
menu "CPU Frequency scaling" menu "CPU Frequency scaling"

2
arch/blackfin/Makefile
View File

@ -24,6 +24,8 @@ machine-$(CONFIG_BF533) := bf533
machine-$(CONFIG_BF534) := bf537 machine-$(CONFIG_BF534) := bf537
machine-$(CONFIG_BF536) := bf537 machine-$(CONFIG_BF536) := bf537
machine-$(CONFIG_BF537) := bf537 machine-$(CONFIG_BF537) := bf537
machine-$(CONFIG_BF548) := bf548
machine-$(CONFIG_BF549) := bf548
machine-$(CONFIG_BF561) := bf561 machine-$(CONFIG_BF561) := bf561
MACHINE := $(machine-y) MACHINE := $(machine-y)
export MACHINE export MACHINE

5
arch/blackfin/kernel/Makefile
View File

@ -6,9 +6,10 @@ extra-y := init_task.o vmlinux.lds
obj-y := \ obj-y := \
entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
sys_bfin.o time.o traps.o irqchip.o dma-mapping.o bfin_gpio.o \ sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o
flat.o
obj-$(CONFIG_BF53x) += bfin_gpio.o
obj-$(CONFIG_BF561) += bfin_gpio.o
obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o
obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o

205
arch/blackfin/kernel/bfin_dma_5xx.c
View File

@ -34,6 +34,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/param.h> #include <linux/param.h>
#include <asm/blackfin.h>
#include <asm/dma.h> #include <asm/dma.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
@ -45,67 +46,6 @@
***************************************************************************/ ***************************************************************************/
static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL]; static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
#if defined (CONFIG_BF561)
static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA1_0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_1_NEXT_DESC_PTR,
(struct dma_register *) DMA1_2_NEXT_DESC_PTR,
(struct dma_register *) DMA1_3_NEXT_DESC_PTR,
(struct dma_register *) DMA1_4_NEXT_DESC_PTR,
(struct dma_register *) DMA1_5_NEXT_DESC_PTR,
(struct dma_register *) DMA1_6_NEXT_DESC_PTR,
(struct dma_register *) DMA1_7_NEXT_DESC_PTR,
(struct dma_register *) DMA1_8_NEXT_DESC_PTR,
(struct dma_register *) DMA1_9_NEXT_DESC_PTR,
(struct dma_register *) DMA1_10_NEXT_DESC_PTR,
(struct dma_register *) DMA1_11_NEXT_DESC_PTR,
(struct dma_register *) DMA2_0_NEXT_DESC_PTR,
(struct dma_register *) DMA2_1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_2_NEXT_DESC_PTR,
(struct dma_register *) DMA2_3_NEXT_DESC_PTR,
(struct dma_register *) DMA2_4_NEXT_DESC_PTR,
(struct dma_register *) DMA2_5_NEXT_DESC_PTR,
(struct dma_register *) DMA2_6_NEXT_DESC_PTR,
(struct dma_register *) DMA2_7_NEXT_DESC_PTR,
(struct dma_register *) DMA2_8_NEXT_DESC_PTR,
(struct dma_register *) DMA2_9_NEXT_DESC_PTR,
(struct dma_register *) DMA2_10_NEXT_DESC_PTR,
(struct dma_register *) DMA2_11_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
};
#else
static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,
(struct dma_register *) DMA3_NEXT_DESC_PTR,
(struct dma_register *) DMA4_NEXT_DESC_PTR,
(struct dma_register *) DMA5_NEXT_DESC_PTR,
(struct dma_register *) DMA6_NEXT_DESC_PTR,
(struct dma_register *) DMA7_NEXT_DESC_PTR,
#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
(struct dma_register *) DMA8_NEXT_DESC_PTR,
(struct dma_register *) DMA9_NEXT_DESC_PTR,
(struct dma_register *) DMA10_NEXT_DESC_PTR,
(struct dma_register *) DMA11_NEXT_DESC_PTR,
#endif
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
};
#endif
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* Set the Buffer Clear bit in the Configuration register of specific DMA * Set the Buffer Clear bit in the Configuration register of specific DMA
@ -138,149 +78,6 @@ static int __init blackfin_dma_init(void)
arch_initcall(blackfin_dma_init); arch_initcall(blackfin_dma_init);
/*
* Form the channel find the irq number for that channel.
*/
#if !defined(CONFIG_BF561)
static int bf533_channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI:
ret_irq = IRQ_PPI;
break;
#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
case CH_EMAC_RX:
ret_irq = IRQ_MAC_RX;
break;
case CH_EMAC_TX:
ret_irq = IRQ_MAC_TX;
break;
case CH_UART1_RX:
ret_irq = IRQ_UART1_RX;
break;
case CH_UART1_TX:
ret_irq = IRQ_UART1_TX;
break;
#endif
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI:
ret_irq = IRQ_SPI;
break;
case CH_UART_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM_DMA1;
break;
}
return ret_irq;
}
# define channel2irq(channel) bf533_channel2irq(channel)
#else
static int bf561_channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI0:
ret_irq = IRQ_PPI0;
break;
case CH_PPI1:
ret_irq = IRQ_PPI1;
break;
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI:
ret_irq = IRQ_SPI;
break;
case CH_UART_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM_DMA1;
break;
case CH_MEM_STREAM2_SRC:
case CH_MEM_STREAM2_DEST:
ret_irq = IRQ_MEM_DMA2;
break;
case CH_MEM_STREAM3_SRC:
case CH_MEM_STREAM3_DEST:
ret_irq = IRQ_MEM_DMA3;
break;
case CH_IMEM_STREAM0_SRC:
case CH_IMEM_STREAM0_DEST:
ret_irq = IRQ_IMEM_DMA0;
break;
case CH_IMEM_STREAM1_SRC:
case CH_IMEM_STREAM1_DEST:
ret_irq = IRQ_IMEM_DMA1;
break;
}
return ret_irq;
}
# define channel2irq(channel) bf561_channel2irq(channel)
#endif
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* Request the specific DMA channel from the system. * Request the specific DMA channel from the system.
*-----------------------------------------------------------------------------*/ *-----------------------------------------------------------------------------*/

3
arch/blackfin/kernel/setup.c
View File

@ -500,8 +500,9 @@ static void __fill_code_cplbtab(struct cplb_tab *t, int i,
cplb_data[i].end, cplb_data[i].end,
SIZE_4M, SIZE_4M,
cplb_data[i].i_conf); cplb_data[i].i_conf);
} else { } else
#endif #endif
{
fill_cplbtab(t, fill_cplbtab(t,
cplb_data[i].start, cplb_data[i].start,
a_start, a_start,

2
arch/blackfin/mach-bf533/Makefile
View File

@ -4,6 +4,6 @@
extra-y := head.o extra-y := head.o
obj-y := ints-priority.o obj-y := ints-priority.o dma.o
obj-$(CONFIG_CPU_FREQ_BF533) += cpu.o obj-$(CONFIG_CPU_FREQ_BF533) += cpu.o

95
arch/blackfin/mach-bf533/dma.c Normal file
View File

@ -0,0 +1,95 @@
/*
* File: arch/blackfin/mach-bf533/dma.c
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,
(struct dma_register *) DMA3_NEXT_DESC_PTR,
(struct dma_register *) DMA4_NEXT_DESC_PTR,
(struct dma_register *) DMA5_NEXT_DESC_PTR,
(struct dma_register *) DMA6_NEXT_DESC_PTR,
(struct dma_register *) DMA7_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
};
int bf533_channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI:
ret_irq = IRQ_PPI;
break;
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI:
ret_irq = IRQ_SPI;
break;
case CH_UART_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM_DMA1;
break;
}
return ret_irq;
}

2
arch/blackfin/mach-bf537/Makefile
View File

@ -4,6 +4,6 @@
extra-y := head.o extra-y := head.o
obj-y := ints-priority.o obj-y := ints-priority.o dma.o
obj-$(CONFIG_CPU_FREQ) += cpu.o obj-$(CONFIG_CPU_FREQ) += cpu.o

115
arch/blackfin/mach-bf537/dma.c Normal file
View File

@ -0,0 +1,115 @@
/*
* File: arch/blackfin/mach-bf537/dma.c
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,
(struct dma_register *) DMA3_NEXT_DESC_PTR,
(struct dma_register *) DMA4_NEXT_DESC_PTR,
(struct dma_register *) DMA5_NEXT_DESC_PTR,
(struct dma_register *) DMA6_NEXT_DESC_PTR,
(struct dma_register *) DMA7_NEXT_DESC_PTR,
(struct dma_register *) DMA8_NEXT_DESC_PTR,
(struct dma_register *) DMA9_NEXT_DESC_PTR,
(struct dma_register *) DMA10_NEXT_DESC_PTR,
(struct dma_register *) DMA11_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
};
int channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI:
ret_irq = IRQ_PPI;
break;
case CH_EMAC_RX:
ret_irq = IRQ_MAC_RX;
break;
case CH_EMAC_TX:
ret_irq = IRQ_MAC_TX;
break;
case CH_UART1_RX:
ret_irq = IRQ_UART1_RX;
break;
case CH_UART1_TX:
ret_irq = IRQ_UART1_TX;
break;
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI:
ret_irq = IRQ_SPI;
break;
case CH_UART_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM_DMA1;
break;
}
return ret_irq;
}

282
arch/blackfin/mach-bf548/Kconfig Normal file
View File

@ -0,0 +1,282 @@
if (BF54x)
menu "BF548 Specific Configuration"
comment "Interrupt Priority Assignment"
menu "Priority"
config IRQ_PLL_WAKEUP
int "IRQ_PLL_WAKEUP"
default 7
config IRQ_DMAC0_ERR
int "IRQ_DMAC0_ERR"
default 7
config IRQ_EPPI0_ERR
int "IRQ_EPPI0_ERR"
default 7
config IRQ_SPORT0_ERR
int "IRQ_SPORT0_ERR"
default 7
config IRQ_SPORT1_ERR
int "IRQ_SPORT1_ERR"
default 7
config IRQ_SPI0_ERR
int "IRQ_SPI0_ERR"
default 7
config IRQ_UART0_ERR
int "IRQ_UART0_ERR"
default 7
config IRQ_RTC
int "IRQ_RTC"
default 8
config IRQ_EPPI0
int "IRQ_EPPI0"
default 8
config IRQ_SPORT0_RX
int "IRQ_SPORT0_RX"
default 9
config IRQ_SPORT0_TX
int "IRQ_SPORT0_TX"
default 9
config IRQ_SPORT1_RX
int "IRQ_SPORT1_RX"
default 9
config IRQ_SPORT1_TX
int "IRQ_SPORT1_TX"
default 9
config IRQ_SPI0
int "IRQ_SPI0"
default 10
config IRQ_UART0_RX
int "IRQ_UART0_RX"
default 10
config IRQ_UART0_TX
int "IRQ_UART0_TX"
default 10
config IRQ_TIMER8
int "IRQ_TIMER8"
default 11
config IRQ_TIMER9
int "IRQ_TIMER9"
default 11
config IRQ_TIMER10
int "IRQ_TIMER10"
default 11
config IRQ_PINT0
int "IRQ_PINT0"
default 12
config IRQ_PINT1
int "IRQ_PINT0"
default 12
config IRQ_MDMAS0
int "IRQ_MDMAS0"
default 13
config IRQ_MDMAS1
int "IRQ_DMDMAS1"
default 13
config IRQ_WATCHDOG
int "IRQ_WATCHDOG"
default 13
config IRQ_DMAC1_ERR
int "IRQ_DMAC1_ERR"
default 7
config IRQ_SPORT2_ERR
int "IRQ_SPORT2_ERR"
default 7
config IRQ_SPORT3_ERR
int "IRQ_SPORT3_ERR"
default 7
config IRQ_MXVR_DATA
int "IRQ MXVR Data"
default 7
config IRQ_SPI1_ERR
int "IRQ_SPI1_ERR"
default 7
config IRQ_SPI2_ERR
int "IRQ_SPI2_ERR"
default 7
config IRQ_UART1_ERR
int "IRQ_UART1_ERR"
default 7
config IRQ_UART2_ERR
int "IRQ_UART2_ERR"
default 7
config IRQ_CAN0_ERR
int "IRQ_CAN0_ERR"
default 7
config IRQ_SPORT2_RX
int "IRQ_SPORT2_RX"
default 9
config IRQ_SPORT2_TX
int "IRQ_SPORT2_TX"
default 9
config IRQ_SPORT3_RX
int "IRQ_SPORT3_RX"
default 9
config IRQ_SPORT3_TX
int "IRQ_SPORT3_TX"
default 9
config IRQ_EPPI1
int "IRQ_EPPI1"
default 9
config IRQ_EPPI2
int "IRQ_EPPI2"
default 9
config IRQ_SPI1
int "IRQ_SPI1"
default 10
config IRQ_SPI2
int "IRQ_SPI2"
default 10
config IRQ_UART1_RX
int "IRQ_UART1_RX"
default 10
config IRQ_UART1_TX
int "IRQ_UART1_TX"
default 10
config IRQ_ATAPI_RX
int "IRQ_ATAPI_RX"
default 10
config IRQ_ATAPI_TX
int "IRQ_ATAPI_TX"
default 10
config IRQ_TWI0
int "IRQ_TWI0"
default 11
config IRQ_TWI1
int "IRQ_TWI1"
default 11
config IRQ_CAN0_RX
int "IRQ_CAN_RX"
default 11
config IRQ_CAN0_TX
int "IRQ_CAN_TX"
default 11
config IRQ_MDMAS2
int "IRQ_MDMAS2"
default 13
config IRQ_MDMAS3
int "IRQ_DMMAS3"
default 13
config IRQ_MXVR_ERR
int "IRQ_MXVR_ERR"
default 11
config IRQ_MXVR_MSG
int "IRQ_MXVR_MSG"
default 11
config IRQ_MXVR_PKT
int "IRQ_MXVR_PKT"
default 11
config IRQ_EPPI1_ERR
int "IRQ_EPPI1_ERR"
default 7
config IRQ_EPPI2_ERR
int "IRQ_EPPI2_ERR"
default 7
config IRQ_UART3_ERR
int "IRQ_UART3_ERR"
default 7
config IRQ_HOST_ERR
int "IRQ_HOST_ERR"
default 7
config IRQ_PIXC_ERR
int "IRQ_PIXC_ERR"
default 7
config IRQ_NFC_ERR
int "IRQ_NFC_ERR"
default 7
config IRQ_ATAPI_ERR
int "IRQ_ATAPI_ERR"
default 7
config IRQ_CAN1_ERR
int "IRQ_CAN1_ERR"
default 7
config IRQ_HS_DMA_ERR
int "IRQ Handshake DMA Status"
default 7
config IRQ_PIXC_IN0
int "IRQ PIXC IN0"
default 8
config IRQ_PIXC_IN1
int "IRQ PIXC IN1"
default 8
config IRQ_PIXC_OUT
int "IRQ PIXC OUT"
default 8
config IRQ_SDH
int "IRQ SDH"
default 8
config IRQ_CNT
int "IRQ CNT"
default 8
config IRQ_KEY
int "IRQ KEY"
default 8
config IRQ_CAN1_RX
int "IRQ CAN1 RX"
default 11
config IRQ_CAN1_TX
int "IRQ_CAN1_TX"
default 11
config IRQ_SDH_MASK0
int "IRQ_SDH_MASK0"
default 11
config IRQ_SDH_MASK1
int "IRQ_SDH_MASK1"
default 11
config IRQ_USB_INT0
int "IRQ USB INT0"
default 11
config IRQ_USB_INT1
int "IRQ USB INT1"
default 11
config IRQ_USB_INT2
int "IRQ USB INT2"
default 11
config IRQ_USB_DMA
int "IRQ USB DMA"
default 11
config IRQ_OTPSEC
int "IRQ OPTSEC"
default 11
config IRQ_TIMER0
int "IRQ_TIMER0"
default 11
config IRQ_TIMER1
int "IRQ_TIMER1"
default 11
config IRQ_TIMER2
int "IRQ_TIMER2"
default 11
config IRQ_TIMER3
int "IRQ_TIMER3"
default 11
config IRQ_TIMER4
int "IRQ_TIMER4"
default 11
config IRQ_TIMER5
int "IRQ_TIMER5"
default 11
config IRQ_TIMER6
int "IRQ_TIMER6"
default 11
config IRQ_TIMER7
int "IRQ_TIMER7"
default 11
config IRQ_PINT2
int "IRQ_PIN2"
default 11
config IRQ_PINT3
int "IRQ_PIN3"
default 11
help
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
This applies to all the above. It is not recommended to assign the
highest priority number 7 to UART or any other device.
endmenu
endmenu
endif

9
arch/blackfin/mach-bf548/Makefile Normal file
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#
# arch/blackfin/mach-bf537/Makefile
#
extra-y := head.o
obj-y := ints-priority.o dma.o gpio.o
obj-$(CONFIG_CPU_FREQ) += cpu.o

5
arch/blackfin/mach-bf548/boards/Makefile Normal file
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#
# arch/blackfin/mach-bf548/boards/Makefile
#
obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o led.o

114
arch/blackfin/mach-bf548/boards/ezkit.c Normal file
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/*
* File: arch/blackfin/mach-bf548/boards/ezkit.c
* Based on: arch/blackfin/mach-bf537/boards/ezkit.c
* Author: Aidan Williams <aidan@nicta.com.au>
*
* Created:
* Description:
*
* Modified:
* Copyright 2005 National ICT Australia (NICTA)
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <asm/irq.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/bfin5xx_spi.h>
/*
* Name the Board for the /proc/cpuinfo
*/
char *bfin_board_name = "ADSP-BF548-EZKIT";
/*
* Driver needs to know address, irq and flag pin.
*/
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
static struct platform_device rtc_device = {
.name = "rtc-bfin",
.id = -1,
};
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
static struct resource bfin_uart_resources[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
{
.start = 0xFFC00400,
.end = 0xFFC004FF,
.flags = IORESOURCE_MEM,
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
{
.start = 0xFFC02000,
.end = 0xFFC020FF,
.flags = IORESOURCE_MEM,
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART2
{
.start = 0xFFC02100,
.end = 0xFFC021FF,
.flags = IORESOURCE_MEM,
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART3
{
.start = 0xFFC03100,
.end = 0xFFC031FF,
},
#endif
};
static struct platform_device bfin_uart_device = {
.name = "bfin-uart",
.id = 1,
.num_resources = ARRAY_SIZE(bfin_uart_resources),
.resource = bfin_uart_resources,
};
#endif
static struct platform_device *ezkit_devices[] __initdata = {
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
&bfin_uart_device,
#endif
};
static int __init stamp_init(void)
{
printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
return 0;
}
arch_initcall(stamp_init);

172
arch/blackfin/mach-bf548/boards/led.S Normal file
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/****************************************************
* LED1 ---- PG6 LED2 ---- PG7 *
* LED3 ---- PG8 LED4 ---- PG9 *
* LED5 ---- PG10 LED6 ---- PG11 *
****************************************************/
#include <linux/linkage.h>
#include <asm/blackfin.h>
/* All functions in this file save the registers they uses.
So there is no need to save any registers before calling them. */
.text;
/* Initialize LEDs. */
ENTRY(_led_init)
LINK 0;
[--SP] = P0;
[--SP] = R0;
[--SP] = R1;
[--SP] = R2;
R1 = (PG6|PG7|PG8|PG9|PG10|PG11)(Z);
R2 = ~R1;
P0.H = hi(PORTG_FER);
P0.L = lo(PORTG_FER);
R0 = W[P0](Z);
SSYNC;
R0 = R0 & R2;
W[P0] = R0.L;
SSYNC;
P0.H = hi(PORTG_DIR_SET);
P0.L = lo(PORTG_DIR_SET);
W[P0] = R1.L;
SSYNC;
P0.H = hi(PORTG_INEN);
P0.L = lo(PORTG_INEN);
R0 = W[P0](Z);
SSYNC;
R0 = R0 & R2;
W[P0] = R0.L;
SSYNC;
R2 = [SP++];
R1 = [SP++];
R0 = [SP++];
P0 = [SP++];
RTS;
.size _led_init, .-_led_init
/* Set one LED on. Leave other LEDs unchanged.
It expects the LED number passed through R0. */
ENTRY(_led_on)
LINK 0;
[--SP] = P0;
[--SP] = R1;
CALL _led_init;
R1 = 1;
R0 += 5;
R1 <<= R0;
P0.H = hi(PORTG_SET);
P0.L = lo(PORTG_SET);
W[P0] = R1.L;
SSYNC;
R1 = [SP++];
P0 = [SP++];
UNLINK;
RTS;
.size _led_on, .-_led_on
/* Set one LED off. Leave other LEDs unchanged. */
ENTRY(_led_off)
LINK 0;
[--SP] = P0;
[--SP] = R1;
CALL _led_init;
R1 = 1;
R0 += 5;
R1 <<= R0;
P0.H = hi(PORTG_CLEAR);
P0.L = lo(PORTG_CLEAR);
W[P0] = R1.L;
SSYNC;
R1 = [SP++];
P0 = [SP++];
UNLINK;
RTS;
.size _led_off, .-_led_off
/* Toggle one LED. Leave other LEDs unchanged. */
ENTRY(_led_toggle)
LINK 0;
[--SP] = P0;
[--SP] = R1;
CALL _led_init;
R1 = 1;
R0 += 5;
R1 <<= R0;
P0.H = hi(PORTG);
P0.L = lo(PORTG);
R0 = W[P0](Z);
SSYNC;
R0 = R0 ^ R1;
W[P0] = R0.L;
SSYNC;
R1 = [SP++];
P0 = [SP++];
UNLINK;
RTS;
.size _led_toggle, .-_led_toggle
/* Display the number using LEDs in binary format. */
ENTRY(_led_disp_num)
LINK 0;
[--SP] = P0;
[--SP] = R1;
[--SP] = R2;
CALL _led_init;
R1 = 0x3f(X);
R0 = R0 & R1;
R2 = 6(X);
R0 <<= R2;
R1 <<= R2;
P0.H = hi(PORTG);
P0.L = lo(PORTG);
R2 = W[P0](Z);
SSYNC;
R1 = ~R1;
R2 = R2 & R1;
R2 = R2 | R0;
W[P0] = R2.L;
SSYNC;
R2 = [SP++];
R1 = [SP++];
P0 = [SP++];
UNLINK;
RTS;
.size _led_disp_num, .-_led_disp_num
/* Toggle the number using LEDs in binary format. */
ENTRY(_led_toggle_num)
LINK 0;
[--SP] = P0;
[--SP] = R1;
[--SP] = R2;
CALL _led_init;
R1 = 0x3f(X);
R0 = R0 & R1;
R1 = 6(X);
R0 <<= R1;
P0.H = hi(PORTG);
P0.L = lo(PORTG);
R1 = W[P0](Z);
SSYNC;
R1 = R1 ^ R0;
W[P0] = R1.L;
SSYNC;
R2 = [SP++];
R1 = [SP++];
P0 = [SP++];
UNLINK;
RTS;
.size _led_toggle_num, .-_led_toggle_num

159
arch/blackfin/mach-bf548/cpu.c Normal file
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/*
* File: arch/blackfin/mach-bf548/cpu.c
* Based on:
* Author:
*
* Created:
* Description: clock scaling for the bf54x
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <asm/dpmc.h>
#include <linux/fs.h>
#include <asm/bfin-global.h>
/* CONFIG_CLKIN_HZ=25000000 */
#define VCO5 (CONFIG_CLKIN_HZ*45)
#define VCO4 (CONFIG_CLKIN_HZ*36)
#define VCO3 (CONFIG_CLKIN_HZ*27)
#define VCO2 (CONFIG_CLKIN_HZ*18)
#define VCO1 (CONFIG_CLKIN_HZ*9)
#define VCO(x) VCO##x
#define MFREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)}
/* frequency */
static struct cpufreq_frequency_table bf548_freq_table[] = {
MFREQ(1),
MFREQ(3),
{VCO4, VCO4 / 2}, {VCO4, VCO4},
MFREQ(5),
{0, CPUFREQ_TABLE_END},
};
/*
* dpmc_fops->ioctl()
* static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
*/
static int bf548_getfreq(unsigned int cpu)
{
unsigned long cclk_mhz;
/* The driver only support single cpu */
if (cpu == 0)
dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
else
cclk_mhz = -1;
return cclk_mhz;
}
static int bf548_target(struct cpufreq_policy *policy,
unsigned int target_freq, unsigned int relation)
{
unsigned long cclk_mhz;
unsigned long vco_mhz;
unsigned long flags;
unsigned int index;
struct cpufreq_freqs freqs;
if (cpufreq_frequency_table_target(policy, bf548_freq_table, target_freq, relation, &index))
return -EINVAL;
cclk_mhz = bf548_freq_table[index].frequency;
vco_mhz = bf548_freq_table[index].index;
dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
freqs.old = bf548_getfreq(0);
freqs.new = cclk_mhz;
freqs.cpu = 0;
pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
cclk_mhz, vco_mhz, index, target_freq, freqs.old);
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
local_irq_save(flags);
dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
local_irq_restore(flags);
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
vco_mhz = get_vco();
cclk_mhz = get_cclk();
return 0;
}
/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
* this platform, anyway.
*/
static int bf548_verify_speed(struct cpufreq_policy *policy)
{
return cpufreq_frequency_table_verify(policy, &bf548_freq_table);
}
static int __init __bf548_cpu_init(struct cpufreq_policy *policy)
{
if (policy->cpu != 0)
return -EINVAL;
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
/*Now ,only support one cpu */
policy->cur = bf548_getfreq(0);
cpufreq_frequency_table_get_attr(bf548_freq_table, policy->cpu);
return cpufreq_frequency_table_cpuinfo(policy, bf548_freq_table);
}
static struct freq_attr *bf548_freq_attr[] = {
&cpufreq_freq_attr_scaling_available_freqs,
NULL,
};
static struct cpufreq_driver bf548_driver = {
.verify = bf548_verify_speed,
.target = bf548_target,
.get = bf548_getfreq,
.init = __bf548_cpu_init,
.name = "bf548",
.owner = THIS_MODULE,
.attr = bf548_freq_attr,
};
static int __init bf548_cpu_init(void)
{
return cpufreq_register_driver(&bf548_driver);
}
static void __exit bf548_cpu_exit(void)
{
cpufreq_unregister_driver(&bf548_driver);
}
MODULE_AUTHOR("Mickael Kang");
MODULE_DESCRIPTION("cpufreq driver for BF548 CPU");
MODULE_LICENSE("GPL");
module_init(bf548_cpu_init);
module_exit(bf548_cpu_exit);

156
arch/blackfin/mach-bf548/dma.c Normal file
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/*
* File: arch/blackfin/mach-bf561/dma.c
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_NEXT_DESC_PTR,
(struct dma_register *) DMA3_NEXT_DESC_PTR,
(struct dma_register *) DMA4_NEXT_DESC_PTR,
(struct dma_register *) DMA5_NEXT_DESC_PTR,
(struct dma_register *) DMA6_NEXT_DESC_PTR,
(struct dma_register *) DMA7_NEXT_DESC_PTR,
(struct dma_register *) DMA8_NEXT_DESC_PTR,
(struct dma_register *) DMA9_NEXT_DESC_PTR,
(struct dma_register *) DMA10_NEXT_DESC_PTR,
(struct dma_register *) DMA11_NEXT_DESC_PTR,
(struct dma_register *) DMA12_NEXT_DESC_PTR,
(struct dma_register *) DMA13_NEXT_DESC_PTR,
(struct dma_register *) DMA14_NEXT_DESC_PTR,
(struct dma_register *) DMA15_NEXT_DESC_PTR,
(struct dma_register *) DMA16_NEXT_DESC_PTR,
(struct dma_register *) DMA17_NEXT_DESC_PTR,
(struct dma_register *) DMA18_NEXT_DESC_PTR,
(struct dma_register *) DMA19_NEXT_DESC_PTR,
(struct dma_register *) DMA20_NEXT_DESC_PTR,
(struct dma_register *) DMA21_NEXT_DESC_PTR,
(struct dma_register *) DMA22_NEXT_DESC_PTR,
(struct dma_register *) DMA23_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
(struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
(struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
};
int channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
case CH_SPI0:
ret_irq = IRQ_SPI0;
break;
case CH_SPI1:
ret_irq = IRQ_SPI1;
break;
case CH_UART0_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART0_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_UART1_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART1_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_EPPI0:
ret_irq = IRQ_EPPI0;
break;
case CH_EPPI1:
ret_irq = IRQ_EPPI1;
break;
case CH_EPPI2:
ret_irq = IRQ_EPPI2;
break;
case CH_PIXC_IMAGE:
ret_irq = IRQ_PIXC_IN0;
break;
case CH_PIXC_OVERLAY:
ret_irq = IRQ_PIXC_IN1;
break;
case CH_PIXC_OUTPUT:
ret_irq = IRQ_PIXC_OUT;
break;
case CH_SPORT2_RX:
ret_irq = IRQ_SPORT2_RX;
break;
case CH_SPORT2_TX:
ret_irq = IRQ_SPORT2_TX;
break;
case CH_SPORT3_RX:
ret_irq = IRQ_SPORT3_RX;
break;
case CH_SPORT3_TX:
ret_irq = IRQ_SPORT3_TX;
break;
case CH_SDH:
ret_irq = IRQ_SDH;
break;
case CH_SPI2:
ret_irq = IRQ_SPI2;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MDMAS0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MDMAS1;
break;
case CH_MEM_STREAM2_SRC:
case CH_MEM_STREAM2_DEST:
ret_irq = IRQ_MDMAS2;
break;
case CH_MEM_STREAM3_SRC:
case CH_MEM_STREAM3_DEST:
ret_irq = IRQ_MDMAS3;
break;
}
return ret_irq;
}

175
arch/blackfin/mach-bf548/gpio.c Normal file
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/*
* File: arch/blackfin/mach-bf548/gpio.c
* Based on:
* Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
*
* Created:
* Description: GPIO Abstraction Layer
*
* Modified:
* Copyright 2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <linux/err.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <linux/irq.h>
static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
(struct gpio_port_t *) PORTA_FER,
(struct gpio_port_t *) PORTB_FER,
(struct gpio_port_t *) PORTC_FER,
(struct gpio_port_t *) PORTD_FER,
(struct gpio_port_t *) PORTE_FER,
(struct gpio_port_t *) PORTF_FER,
(struct gpio_port_t *) PORTG_FER,
(struct gpio_port_t *) PORTH_FER,
(struct gpio_port_t *) PORTI_FER,
(struct gpio_port_t *) PORTJ_FER,
};
static unsigned short reserved_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
inline int check_gpio(unsigned short gpio)
{
if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 \
|| gpio == GPIO_PH14 || gpio == GPIO_PH15 \
|| gpio > MAX_BLACKFIN_GPIOS)
return -EINVAL;
return 0;
}
static void port_setup(unsigned short gpio, unsigned short usage)
{
if (usage == GPIO_USAGE) {
if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio))
printk(KERN_WARNING "bfin-gpio: Possible Conflict with Peripheral "
"usage and GPIO %d detected!\n", gpio);
gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
} else
gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
SSYNC();
}
static int __init bfin_gpio_init(void)
{
int i;
printk(KERN_INFO "Blackfin GPIO Controller\n");
for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE)
reserved_map[gpio_bank(i)] = 0;
return 0;
}
arch_initcall(bfin_gpio_init);
/***********************************************************
*
* FUNCTIONS: Blackfin GPIO Driver
*
* INPUTS/OUTPUTS:
* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
*
*
* DESCRIPTION: Blackfin GPIO Driver API
*
* CAUTION:
*************************************************************
* MODIFICATION HISTORY :
**************************************************************/
int gpio_request(unsigned short gpio, const char *label)
{
unsigned long flags;
if (check_gpio(gpio) < 0)
return -EINVAL;
local_irq_save(flags);
if (unlikely(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
dump_stack();
local_irq_restore(flags);
return -EBUSY;
}
reserved_map[gpio_bank(gpio)] |= gpio_bit(gpio);
local_irq_restore(flags);
port_setup(gpio, GPIO_USAGE);
return 0;
}
EXPORT_SYMBOL(gpio_request);
void gpio_free(unsigned short gpio)
{
unsigned long flags;
if (check_gpio(gpio) < 0)
return;
local_irq_save(flags);
if (unlikely(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
dump_stack();
local_irq_restore(flags);
return;
}
reserved_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
local_irq_restore(flags);
}
EXPORT_SYMBOL(gpio_free);
void gpio_direction_input(unsigned short gpio)
{
unsigned long flags;
BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)));
local_irq_save(flags);
gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
local_irq_restore(flags);
}
EXPORT_SYMBOL(gpio_direction_input);
void gpio_direction_output(unsigned short gpio)
{
unsigned long flags;
BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)));
local_irq_save(flags);
gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
local_irq_restore(flags);
}
EXPORT_SYMBOL(gpio_direction_output);

507
arch/blackfin/mach-bf548/head.S Normal file
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/*
* File: arch/blackfin/mach-bf548/head.S
* Based on: arch/blackfin/mach-bf537/head.S
* Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
*
* Created: 1998
* Description: Startup code for Blackfin BF548
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/linkage.h>
#include <asm/blackfin.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach/mem_init.h>
#endif
.global __rambase
.global __ramstart
.global __ramend
.extern ___bss_stop
.extern ___bss_start
.extern _bf53x_relocate_l1_mem
#define INITIAL_STACK 0xFFB01000
.text
ENTRY(__start)
ENTRY(__stext)
/* R0: argument of command line string, passed from uboot, save it */
R7 = R0;
/* Set the SYSCFG register */
R0 = 0x36;
SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
R0 = 0;
/* Clear Out All the data and pointer Registers*/
R1 = R0;
R2 = R0;
R3 = R0;
R4 = R0;
R5 = R0;
R6 = R0;
P0 = R0;
P1 = R0;
P2 = R0;
P3 = R0;
P4 = R0;
P5 = R0;
LC0 = r0;
LC1 = r0;
L0 = r0;
L1 = r0;
L2 = r0;
L3 = r0;
/* Clear Out All the DAG Registers*/
B0 = r0;
B1 = r0;
B2 = r0;
B3 = r0;
I0 = r0;
I1 = r0;
I2 = r0;
I3 = r0;
M0 = r0;
M1 = r0;
M2 = r0;
M3 = r0;
/* Turn off the icache */
p0.l = (IMEM_CONTROL & 0xFFFF);
p0.h = (IMEM_CONTROL >> 16);
R1 = [p0];
R0 = ~ENICPLB;
R0 = R0 & R1;
[p0] = R0;
SSYNC;
/* Turn off the dcache */
p0.l = (DMEM_CONTROL & 0xFFFF);
p0.h = (DMEM_CONTROL >> 16);
R1 = [p0];
R0 = ~ENDCPLB;
R0 = R0 & R1;
[p0] = R0;
SSYNC;
/* Initialize stack pointer */
SP.L = LO(INITIAL_STACK);
SP.H = HI(INITIAL_STACK);
FP = SP;
USP = SP;
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
call _bf53x_relocate_l1_mem;
#if CONFIG_BFIN_KERNEL_CLOCK
call _start_dma_code;
#endif
/* Code for initializing Async memory banks */
p2.h = hi(EBIU_AMBCTL1);
p2.l = lo(EBIU_AMBCTL1);
r0.h = hi(AMBCTL1VAL);
r0.l = lo(AMBCTL1VAL);
[p2] = r0;
ssync;
p2.h = hi(EBIU_AMBCTL0);
p2.l = lo(EBIU_AMBCTL0);
r0.h = hi(AMBCTL0VAL);
r0.l = lo(AMBCTL0VAL);
[p2] = r0;
ssync;
p2.h = hi(EBIU_AMGCTL);
p2.l = lo(EBIU_AMGCTL);
r0 = AMGCTLVAL;
w[p2] = r0;
ssync;
/* This section keeps the processor in supervisor mode
* during kernel boot. Switches to user mode at end of boot.
* See page 3-9 of Hardware Reference manual for documentation.
*/
/* EVT15 = _real_start */
p0.l = lo(EVT15);
p0.h = hi(EVT15);
p1.l = _real_start;
p1.h = _real_start;
[p0] = p1;
csync;
p0.l = lo(IMASK);
p0.h = hi(IMASK);
p1.l = IMASK_IVG15;
p1.h = 0x0;
[p0] = p1;
csync;
raise 15;
p0.l = .LWAIT_HERE;
p0.h = .LWAIT_HERE;
reti = p0;
#if defined (ANOMALY_05000281)
nop;
nop;
nop;
#endif
rti;
.LWAIT_HERE:
jump .LWAIT_HERE;
ENTRY(_real_start)
[ -- sp ] = reti;
p0.l = lo(WDOG_CTL);
p0.h = hi(WDOG_CTL);
r0 = 0xAD6(z);
w[p0] = r0; /* watchdog off for now */
ssync;
/* Code update for BSS size == 0
* Zero out the bss region.
*/
p1.l = ___bss_start;
p1.h = ___bss_start;
p2.l = ___bss_stop;
p2.h = ___bss_stop;
r0 = 0;
p2 -= p1;
lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
.L_clear_bss:
B[p1++] = r0;
/* In case there is a NULL pointer reference
* Zero out region before stext
*/
p1.l = 0x0;
p1.h = 0x0;
r0.l = __stext;
r0.h = __stext;
r0 = r0 >> 1;
p2 = r0;
r0 = 0;
lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
.L_clear_zero:
W[p1++] = r0;
/* pass the uboot arguments to the global value command line */
R0 = R7;
call _cmdline_init;
p1.l = __rambase;
p1.h = __rambase;
r0.l = __sdata;
r0.h = __sdata;
[p1] = r0;
p1.l = __ramstart;
p1.h = __ramstart;
p3.l = ___bss_stop;
p3.h = ___bss_stop;
r1 = p3;
[p1] = r1;
/*
* load the current thread pointer and stack
*/
r1.l = _init_thread_union;
r1.h = _init_thread_union;
r2.l = 0x2000;
r2.h = 0x0000;
r1 = r1 + r2;
sp = r1;
usp = sp;
fp = sp;
call _start_kernel;
.L_exit:
jump.s .L_exit;
.section .l1.text
#if CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)
/* Enable PHY CLK buffer output */
p0.h = hi(VR_CTL);
p0.l = lo(VR_CTL);
r0.l = w[p0];
bitset(r0, 14);
w[p0] = r0.l;
ssync;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = 0x1;
r0.h = 0x0;
[p0] = r0;
SSYNC;
/*
* Set PLL_CTL
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
r0 = 0x300(Z);
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
[P2] = R0;
SSYNC;
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0;
r1 = PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
cli r2; /* Disable interrupts */
ssync;
w[p0] = r0.l; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
.Lcheck_again:
p0.h = hi(PLL_STAT);
p0.l = lo(PLL_STAT);
R0 = W[P0](Z);
CC = BITTST(R0,5);
if ! CC jump .Lcheck_again;
/* Configure SCLK & CCLK Dividers */
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
p0.h = hi(PLL_DIV);
p0.l = lo(PLL_DIV);
w[p0] = r0.l;
ssync;
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
p0.l = (EBIU_SDBCTL & 0xFFFF);
p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITCLR (R0, 24);
p0.h = hi(EBIU_SDSTAT);
p0.l = lo(EBIU_SDSTAT);
r2.l = w[p0];
cc = bittst(r2,3);
if !cc jump .Lskip;
NOP;
BITSET (R0, 23);
.Lskip:
[P2] = R0;
SSYNC;
R0.L = lo(mem_SDGCTL);
R0.H = hi(mem_SDGCTL);
R1 = [p2];
R1 = R1 | R0;
[P2] = R1;
SSYNC;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = lo(IWR_ENABLE_ALL);
r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;
SSYNC;
RTS;
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
ENTRY(_bfin_reset)
/* No more interrupts to be handled*/
CLI R6;
SSYNC;
#if defined(CONFIG_MTD_M25P80)
/*
* The following code fix the SPI flash reboot issue,
* /CS signal of the chip which is using PF10 return to GPIO mode
*/
p0.h = hi(PORTF_FER);
p0.l = lo(PORTF_FER);
r0.l = 0x0000;
w[p0] = r0.l;
SSYNC;
/* /CS return to high */
p0.h = hi(PORTFIO);
p0.l = lo(PORTFIO);
r0.l = 0xFFFF;
w[p0] = r0.l;
SSYNC;
/* Delay some time, This is necessary */
r1.h = 0;
r1.l = 0x400;
p1 = r1;
lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
_delay_lab1:
r0.h = 0;
r0.l = 0x8000;
p0 = r0;
lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
_delay_lab0:
nop;
_delay_lab0_end:
nop;
_delay_lab1_end:
nop;
#endif
/* Clear the bits 13-15 in SWRST if they werent cleared */
p0.h = hi(SWRST);
p0.l = lo(SWRST);
csync;
r0.l = w[p0];
/* Clear the IMASK register */
p0.h = hi(IMASK);
p0.l = lo(IMASK);
r0 = 0x0;
[p0] = r0;
/* Clear the ILAT register */
p0.h = hi(ILAT);
p0.l = lo(ILAT);
r0 = [p0];
[p0] = r0;
SSYNC;
/* Disable the WDOG TIMER */
p0.h = hi(WDOG_CTL);
p0.l = lo(WDOG_CTL);
r0.l = 0xAD6;
w[p0] = r0.l;
SSYNC;
/* Clear the sticky bit incase it is already set */
p0.h = hi(WDOG_CTL);
p0.l = lo(WDOG_CTL);
r0.l = 0x8AD6;
w[p0] = r0.l;
SSYNC;
/* Program the count value */
R0.l = 0x100;
R0.h = 0x0;
P0.h = hi(WDOG_CNT);
P0.l = lo(WDOG_CNT);
[P0] = R0;
SSYNC;
/* Program WDOG_STAT if necessary */
P0.h = hi(WDOG_CTL);
P0.l = lo(WDOG_CTL);
R0 = W[P0](Z);
CC = BITTST(R0,1);
if !CC JUMP .LWRITESTAT;
CC = BITTST(R0,2);
if !CC JUMP .LWRITESTAT;
JUMP .LSKIP_WRITE;
.LWRITESTAT:
/* When watch dog timer is enabled,
* a write to STAT will load the contents of CNT to STAT
*/
R0 = 0x0000(z);
P0.h = hi(WDOG_STAT);
P0.l = lo(WDOG_STAT)
[P0] = R0;
SSYNC;
.LSKIP_WRITE:
/* Enable the reset event */
P0.h = hi(WDOG_CTL);
P0.l = lo(WDOG_CTL);
R0 = W[P0](Z);
BITCLR(R0,1);
BITCLR(R0,2);
W[P0] = R0.L;
SSYNC;
NOP;
/* Enable the wdog counter */
R0 = W[P0](Z);
BITCLR(R0,4);
W[P0] = R0.L;
SSYNC;
IDLE;
RTS;
.data
/*
* Set up the usable of RAM stuff. Size of RAM is determined then
* an initial stack set up at the end.
*/
.align 4
__rambase:
.long 0
__ramstart:
.long 0
__ramend:
.long 0

137
arch/blackfin/mach-bf548/ints-priority.c Normal file
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/*
* File: arch/blackfin/mach-bf537/ints-priority.c
* Based on: arch/blackfin/mach-bf533/ints-priority.c
* Author: Michael Hennerich
*
* Created:
* Description: Set up the interupt priorities
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <asm/blackfin.h>
#include <asm/irq.h>
void program_IAR(void)
{
/* Program the IAR0 Register with the configured priority */
bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));
bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
SSYNC();
}

2
arch/blackfin/mach-bf561/Makefile
View File

@ -4,6 +4,6 @@
extra-y := head.o extra-y := head.o
obj-y := ints-priority.o obj-y := ints-priority.o dma.o
obj-$(CONFIG_BF561_COREB) += coreb.o obj-$(CONFIG_BF561_COREB) += coreb.o

131
arch/blackfin/mach-bf561/dma.c Normal file
View File

@ -0,0 +1,131 @@
/*
* File: arch/blackfin/mach-bf561/dma.c
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <asm/blackfin.h>
#include <asm/dma.h>
struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
(struct dma_register *) DMA1_0_NEXT_DESC_PTR,
(struct dma_register *) DMA1_1_NEXT_DESC_PTR,
(struct dma_register *) DMA1_2_NEXT_DESC_PTR,
(struct dma_register *) DMA1_3_NEXT_DESC_PTR,
(struct dma_register *) DMA1_4_NEXT_DESC_PTR,
(struct dma_register *) DMA1_5_NEXT_DESC_PTR,
(struct dma_register *) DMA1_6_NEXT_DESC_PTR,
(struct dma_register *) DMA1_7_NEXT_DESC_PTR,
(struct dma_register *) DMA1_8_NEXT_DESC_PTR,
(struct dma_register *) DMA1_9_NEXT_DESC_PTR,
(struct dma_register *) DMA1_10_NEXT_DESC_PTR,
(struct dma_register *) DMA1_11_NEXT_DESC_PTR,
(struct dma_register *) DMA2_0_NEXT_DESC_PTR,
(struct dma_register *) DMA2_1_NEXT_DESC_PTR,
(struct dma_register *) DMA2_2_NEXT_DESC_PTR,
(struct dma_register *) DMA2_3_NEXT_DESC_PTR,
(struct dma_register *) DMA2_4_NEXT_DESC_PTR,
(struct dma_register *) DMA2_5_NEXT_DESC_PTR,
(struct dma_register *) DMA2_6_NEXT_DESC_PTR,
(struct dma_register *) DMA2_7_NEXT_DESC_PTR,
(struct dma_register *) DMA2_8_NEXT_DESC_PTR,
(struct dma_register *) DMA2_9_NEXT_DESC_PTR,
(struct dma_register *) DMA2_10_NEXT_DESC_PTR,
(struct dma_register *) DMA2_11_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
};
int channel2irq(unsigned int channel)
{
int ret_irq = -1;
switch (channel) {
case CH_PPI0:
ret_irq = IRQ_PPI0;
break;
case CH_PPI1:
ret_irq = IRQ_PPI1;
break;
case CH_SPORT0_RX:
ret_irq = IRQ_SPORT0_RX;
break;
case CH_SPORT0_TX:
ret_irq = IRQ_SPORT0_TX;
break;
case CH_SPORT1_RX:
ret_irq = IRQ_SPORT1_RX;
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI:
ret_irq = IRQ_SPI;
break;
case CH_UART_RX:
ret_irq = IRQ_UART_RX;
break;
case CH_UART_TX:
ret_irq = IRQ_UART_TX;
break;
case CH_MEM_STREAM0_SRC:
case CH_MEM_STREAM0_DEST:
ret_irq = IRQ_MEM_DMA0;
break;
case CH_MEM_STREAM1_SRC:
case CH_MEM_STREAM1_DEST:
ret_irq = IRQ_MEM_DMA1;
break;
case CH_MEM_STREAM2_SRC:
case CH_MEM_STREAM2_DEST:
ret_irq = IRQ_MEM_DMA2;
break;
case CH_MEM_STREAM3_SRC:
case CH_MEM_STREAM3_DEST:
ret_irq = IRQ_MEM_DMA3;
break;
case CH_IMEM_STREAM0_SRC:
case CH_IMEM_STREAM0_DEST:
ret_irq = IRQ_IMEM_DMA0;
break;
case CH_IMEM_STREAM1_SRC:
case CH_IMEM_STREAM1_DEST:
ret_irq = IRQ_IMEM_DMA1;
break;
}
return ret_irq;
}

4
arch/blackfin/mach-common/Makefile
View File

@ -4,9 +4,9 @@
obj-y := \ obj-y := \
cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \ cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
interrupt.o lock.o dpmc.o irqpanic.o interrupt.o lock.o irqpanic.o
obj-$(CONFIG_CPLB_INFO) += cplbinfo.o obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += pm.o dpmc.o

50
arch/blackfin/mach-common/ints-priority-sc.c
View File

@ -13,7 +13,7 @@
* 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* 2003 Metrowerks/Motorola * 2003 Metrowerks/Motorola
* 2003 Bas Vermeulen <bas@buyways.nl> * 2003 Bas Vermeulen <bas@buyways.nl>
* Copyright 2004-2006 Analog Devices Inc. * Copyright 2004-2007 Analog Devices Inc.
* *
* Bugs: Enter bugs at http://blackfin.uclinux.org/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
* *
@ -65,9 +65,9 @@ atomic_t num_spurious;
struct ivgx { struct ivgx {
/* irq number for request_irq, available in mach-bf533/irq.h */ /* irq number for request_irq, available in mach-bf533/irq.h */
int irqno; unsigned int irqno;
/* corresponding bit in the SIC_ISR register */ /* corresponding bit in the SIC_ISR register */
int isrflag; unsigned int isrflag;
} ivg_table[NR_PERI_INTS]; } ivg_table[NR_PERI_INTS];
struct ivg_slice { struct ivg_slice {
@ -98,7 +98,7 @@ static void __init search_IAR(void)
bfin_read32((unsigned long *) SIC_IAR0 + bfin_read32((unsigned long *) SIC_IAR0 +
(irqn >> 3)) >> iar_shift)) { (irqn >> 3)) >> iar_shift)) {
ivg_table[irq_pos].irqno = IVG7 + irqn; ivg_table[irq_pos].irqno = IVG7 + irqn;
ivg_table[irq_pos].isrflag = 1 << irqn; ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
ivg7_13[ivg].istop++; ivg7_13[ivg].istop++;
irq_pos++; irq_pos++;
} }
@ -141,15 +141,31 @@ static void bfin_core_unmask_irq(unsigned int irq)
static void bfin_internal_mask_irq(unsigned int irq) static void bfin_internal_mask_irq(unsigned int irq)
{ {
#ifndef CONFIG_BF54x
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
~(1 << (irq - (IRQ_CORETMR + 1)))); ~(1 << (irq - (IRQ_CORETMR + 1))));
#else
unsigned mask_bank, mask_bit;
mask_bank = (irq - (IRQ_CORETMR +1))/32;
mask_bit = (irq - (IRQ_CORETMR + 1))%32;
bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \
~(1 << mask_bit));
#endif
SSYNC(); SSYNC();
} }
static void bfin_internal_unmask_irq(unsigned int irq) static void bfin_internal_unmask_irq(unsigned int irq)
{ {
#ifndef CONFIG_BF54x
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
(1 << (irq - (IRQ_CORETMR + 1)))); (1 << (irq - (IRQ_CORETMR + 1))));
#else
unsigned mask_bank, mask_bit;
mask_bank = (irq - (IRQ_CORETMR +1))/32;
mask_bit = (irq - (IRQ_CORETMR + 1))%32;
bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \
( 1 << mask_bit));
#endif
SSYNC(); SSYNC();
} }
@ -452,7 +468,14 @@ int __init init_arch_irq(void)
int irq; int irq;
unsigned long ilat = 0; unsigned long ilat = 0;
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */ /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
#ifdef CONFIG_BF54x
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
#else
bfin_write_SIC_IMASK(SIC_UNMASK_ALL); bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
#endif
SSYNC(); SSYNC();
local_irq_disable(); local_irq_disable();
@ -555,8 +578,24 @@ void do_irq(int vec, struct pt_regs *fp)
} else { } else {
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
unsigned long sic_status; #ifdef CONFIG_BF54x
unsigned long sic_status[3];
SSYNC();
sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
SSYNC();
for(;; ivg++) {
if (ivg >= ivg_stop) {
atomic_inc(&num_spurious);
return;
}
if (sic_status[(ivg->irqno - IVG7)/32] & ivg->isrflag)
break;
}
#else
unsigned long sic_status;
SSYNC(); SSYNC();
sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
@ -567,6 +606,7 @@ void do_irq(int vec, struct pt_regs *fp)
} else if (sic_status & ivg->isrflag) } else if (sic_status & ivg->isrflag)
break; break;
} }
#endif
vec = ivg->irqno; vec = ivg->irqno;
} }
asm_do_IRQ(vec, fp); asm_do_IRQ(vec, fp);

6
include/asm-blackfin/gpio.h
View File

@ -204,6 +204,10 @@
#endif #endif
#ifdef BF548_FAMILY
#include <asm-blackfin/mach-bf548/gpio.h>
#endif
#ifdef BF561_FAMILY #ifdef BF561_FAMILY
#define MAX_BLACKFIN_GPIOS 48 #define MAX_BLACKFIN_GPIOS 48
#define PORT_FIO0 GPIO_0 #define PORT_FIO0 GPIO_0
@ -264,6 +268,7 @@ unsigned short get_gpiop_maska(unsigned short);
unsigned short get_gpiop_maskb(unsigned short); unsigned short get_gpiop_maskb(unsigned short);
unsigned short get_gpiop_data(unsigned short); unsigned short get_gpiop_data(unsigned short);
#ifndef BF548_FAMILY
struct gpio_port_t { struct gpio_port_t {
unsigned short data; unsigned short data;
unsigned short dummy1; unsigned short dummy1;
@ -299,6 +304,7 @@ struct gpio_port_t {
unsigned short dummy16; unsigned short dummy16;
unsigned short inen; unsigned short inen;
}; };
#endif
#ifdef CONFIG_PM #ifdef CONFIG_PM
#define PM_WAKE_RISING 0x1 #define PM_WAKE_RISING 0x1

3
include/asm-blackfin/mach-bf533/dma.h
View File

@ -51,4 +51,7 @@
#define CH_MEM_STREAM1_DEST 10 /* TX */ #define CH_MEM_STREAM1_DEST 10 /* TX */
#define CH_MEM_STREAM1_SRC 11 /* RX */ #define CH_MEM_STREAM1_SRC 11 /* RX */
extern int channel2irq(unsigned int channel);
extern struct dma_register *base_addr[];
#endif #endif

3
include/asm-blackfin/mach-bf537/dma.h
View File

@ -52,4 +52,7 @@
#define CH_MEM_STREAM1_DEST 14 /* TX */ #define CH_MEM_STREAM1_DEST 14 /* TX */
#define CH_MEM_STREAM1_SRC 15 /* RX */ #define CH_MEM_STREAM1_SRC 15 /* RX */
extern int channel2irq(unsigned int channel);
extern struct dma_register *base_addr[];
#endif #endif

2
include/asm-blackfin/mach-bf548/anomaly.h
View File

@ -47,6 +47,8 @@
SPORT external receive and transmit clocks. */ SPORT external receive and transmit clocks. */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for #define ANOMALY_05000272 /* Certain data cache write through modes fail for
VDDint <=0.9V */ VDDint <=0.9V */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
not restored */
#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the #define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
Boundary of Reserved Memory */ Boundary of Reserved Memory */
#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and #define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and

2
include/asm-blackfin/mach-bf548/bf548.h
View File

@ -30,6 +30,8 @@
#ifndef __MACH_BF548_H__ #ifndef __MACH_BF548_H__
#define __MACH_BF548_H__ #define __MACH_BF548_H__
#define SUPPORTED_REVID 0
/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ /* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ #define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */

84
include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
View File

@ -1,34 +1,35 @@
#include <linux/serial.h> #include <linux/serial.h>
#include <asm/dma.h> #include <asm/dma.h>
#define NR_PORTS 2 #define NR_PORTS 4
#define OFFSET_THR 0x00 /* Transmit Holding register */
#define OFFSET_RBR 0x00 /* Receive Buffer register */
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
#define OFFSET_IER 0x04 /* Interrupt Enable Register */
#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ #define OFFSET_GCTL 0x08 /* Global Control Register */
#define OFFSET_LCR 0x0C /* Line Control Register */ #define OFFSET_LCR 0x0C /* Line Control Register */
#define OFFSET_MCR 0x10 /* Modem Control Register */ #define OFFSET_MCR 0x10 /* Modem Control Register */
#define OFFSET_LSR 0x14 /* Line Status Register */ #define OFFSET_LSR 0x14 /* Line Status Register */
#define OFFSET_MSR 0x18 /* Modem Status Register */ #define OFFSET_MSR 0x18 /* Modem Status Register */
#define OFFSET_SCR 0x1C /* SCR Scratch Register */ #define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */ #define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
#define OFFSET_THR 0x28 /* Transmit Holding register */
#define OFFSET_RBR 0x2C /* Receive Buffer register */
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) #define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
@ -112,9 +113,29 @@ struct bfin_serial_res bfin_serial_resource[] = {
CH_UART1_TX, CH_UART1_TX,
CH_UART1_RX, CH_UART1_RX,
#endif #endif
#ifdef CONFIG_BFIN_UART1_CTSRTS },
CONFIG_UART1_CTS_PIN, #endif
CONFIG_UART1_RTS_PIN, #ifdef CONFIG_SERIAL_BFIN_UART2
{
0xFFC02100,
IRQ_UART2_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART2_TX,
CH_UART2_RX,
#endif
#ifdef CONFIG_BFIN_UART2_CTSRTS
CONFIG_UART2_CTS_PIN,
CONFIG_UART2_RTS_PIN,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART3
{
0xFFC03100,
IRQ_UART3_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART3_TX,
CH_UART3_RX,
#endif #endif
}, },
#endif #endif
@ -124,15 +145,40 @@ int nr_ports = ARRAY_SIZE(bfin_serial_resource);
static void bfin_serial_hw_init(struct bfin_serial_port *uart) static void bfin_serial_hw_init(struct bfin_serial_port *uart)
{ {
unsigned short val; #ifdef CONFIG_SERIAL_BFIN_UART0
val = bfin_read16(BFIN_PORT_MUX); /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
val &= ~(PFDE | PFTE); bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
bfin_write16(BFIN_PORT_MUX, val); bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
#endif
val = bfin_read16(PORTF_FER); #ifdef CONFIG_SERIAL_BFIN_UART1
val |= 0xF; /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */
bfin_write16(PORTF_FER, val); bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER());
bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX());
#ifdef CONFIG_BFIN_UART1_CTSRTS
/* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */
bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER());
bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX());
#endif
#endif
#ifdef CONFIG_SERIAL_BFIN_UART2
/* Enable UART2 RX and TX on pin 4 & 5 of PORT B */
bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER());
bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX());
#endif
#ifdef CONFIG_SERIAL_BFIN_UART3
/* Enable UART3 RX and TX on pin 6 & 7 of PORT B */
bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER());
bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX());
#ifdef CONFIG_BFIN_UART3_CTSRTS
/* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */
bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER());
bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX());
#endif
#endif
SSYNC();
#ifdef CONFIG_SERIAL_BFIN_CTSRTS #ifdef CONFIG_SERIAL_BFIN_CTSRTS
if (uart->cts_pin >= 0) { if (uart->cts_pin >= 0) {
gpio_request(uart->cts_pin, NULL); gpio_request(uart->cts_pin, NULL);

16
include/asm-blackfin/mach-bf548/blackfin.h
View File

@ -34,24 +34,26 @@
#define BF548_FAMILY #define BF548_FAMILY
#include "bf548.h"
#include "mem_map.h"
#include "anomaly.h"
#ifdef CONFIG_BF542 #ifdef CONFIG_BF542
#include "bf542.h" #include "defBF542.h"
#endif
#ifdef CONFIG_BF544 #ifdef CONFIG_BF544
#include "bf544.h" #include "defBF544.h"
#endif #endif
#ifdef CONFIG_BF548 #ifdef CONFIG_BF548
#include "bf548.h" #include "defBF548.h"
#endif #endif
#ifdef CONFIG_BF549 #ifdef CONFIG_BF549
#include "bf549.h" #include "defBF549.h"
#endif #endif
#include "mem_map.h"
#include "anomaly.h"
#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) #if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
#ifdef CONFIG_BF542 #ifdef CONFIG_BF542
#include "cdefBF542.h" #include "cdefBF542.h"

46
include/asm-blackfin/mach-bf548/cdefBF54x_base.h
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@ -31,7 +31,7 @@
#ifndef _CDEF_BF54X_H #ifndef _CDEF_BF54X_H
#define _CDEF_BF54X_H #define _CDEF_BF54X_H
#include <defBF54x_base.h> #include "defBF54x_base.h"
/* ************************************************************** */ /* ************************************************************** */
/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
@ -70,12 +70,18 @@
#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
@ -710,21 +716,21 @@
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR)
#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR) #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY) #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY) #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR) #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR) #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
@ -734,23 +740,23 @@
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR) #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR) #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY) #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY) #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR) #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR) #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
@ -763,9 +769,9 @@
/* MDMA Stream 1 Registers */ /* MDMA Stream 1 Registers */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR) #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR) #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
@ -777,9 +783,9 @@
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY)
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR) #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR) #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
@ -789,9 +795,9 @@
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR) #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR) #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
@ -803,9 +809,9 @@
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY)
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR) #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR) #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)

281
include/asm-blackfin/mach-bf548/defBF542.h
View File

@ -362,7 +362,6 @@
/* Bit masks for KPAD_CTL */ /* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1 /* Keypad Enable */ #define KPAD_EN 0x1 /* Keypad Enable */
#define nKPAD_EN 0x0
#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */
@ -384,29 +383,21 @@
/* Bit masks for KPAD_STAT */ /* Bit masks for KPAD_STAT */
#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
#define nKPAD_IRQ 0x0
#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
#define KPAD_PRESSED 0x8 /* Key press current status */ #define KPAD_PRESSED 0x8 /* Key press current status */
#define nKPAD_PRESSED 0x0
/* Bit masks for KPAD_SOFTEVAL */ /* Bit masks for KPAD_SOFTEVAL */
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
#define nKPAD_SOFTEVAL_E 0x0
/* Bit masks for SDH_COMMAND */ /* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */ #define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */ #define CMD_RSP 0x40 /* Response */
#define nCMD_RSP 0x0
#define CMD_L_RSP 0x80 /* Long Response */ #define CMD_L_RSP 0x80 /* Long Response */
#define nCMD_L_RSP 0x0
#define CMD_INT_E 0x100 /* Command Interrupt */ #define CMD_INT_E 0x100 /* Command Interrupt */
#define nCMD_INT_E 0x0
#define CMD_PEND_E 0x200 /* Command Pending */ #define CMD_PEND_E 0x200 /* Command Pending */
#define nCMD_PEND_E 0x0
#define CMD_E 0x400 /* Command Enable */ #define CMD_E 0x400 /* Command Enable */
#define nCMD_E 0x0
/* Bit masks for SDH_PWR_CTL */ /* Bit masks for SDH_PWR_CTL */
@ -415,21 +406,15 @@
#define TBD 0x3c /* TBD */ #define TBD 0x3c /* TBD */
#endif #endif
#define SD_CMD_OD 0x40 /* Open Drain Output */ #define SD_CMD_OD 0x40 /* Open Drain Output */
#define nSD_CMD_OD 0x0
#define ROD_CTL 0x80 /* Rod Control */ #define ROD_CTL 0x80 /* Rod Control */
#define nROD_CTL 0x0
/* Bit masks for SDH_CLK_CTL */ /* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */ #define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
#define nCLK_E 0x0
#define PWR_SV_E 0x200 /* Power Save Enable */ #define PWR_SV_E 0x200 /* Power Save Enable */
#define nPWR_SV_E 0x0
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
#define nCLKDIV_BYPASS 0x0
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
#define nWIDE_BUS 0x0
/* Bit masks for SDH_RESP_CMD */ /* Bit masks for SDH_RESP_CMD */
@ -438,133 +423,74 @@
/* Bit masks for SDH_DATA_CTL */ /* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */ #define DTX_E 0x1 /* Data Transfer Enable */
#define nDTX_E 0x0
#define DTX_DIR 0x2 /* Data Transfer Direction */ #define DTX_DIR 0x2 /* Data Transfer Direction */
#define nDTX_DIR 0x0
#define DTX_MODE 0x4 /* Data Transfer Mode */ #define DTX_MODE 0x4 /* Data Transfer Mode */
#define nDTX_MODE 0x0
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
#define nDTX_DMA_E 0x0
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */ /* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define nCMD_CRC_FAIL 0x0
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
#define nDAT_CRC_FAIL 0x0
#define CMD_TIMEOUT 0x4 /* CMD Time Out */ #define CMD_TIMEOUT 0x4 /* CMD Time Out */
#define nCMD_TIMEOUT 0x0
#define DAT_TIMEOUT 0x8 /* Data Time Out */ #define DAT_TIMEOUT 0x8 /* Data Time Out */
#define nDAT_TIMEOUT 0x0
#define TX_UNDERRUN 0x10 /* Transmit Underrun */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define nTX_UNDERRUN 0x0
#define RX_OVERRUN 0x20 /* Receive Overrun */ #define RX_OVERRUN 0x20 /* Receive Overrun */
#define nRX_OVERRUN 0x0
#define CMD_RESP_END 0x40 /* CMD Response End */ #define CMD_RESP_END 0x40 /* CMD Response End */
#define nCMD_RESP_END 0x0
#define CMD_SENT 0x80 /* CMD Sent */ #define CMD_SENT 0x80 /* CMD Sent */
#define nCMD_SENT 0x0
#define DAT_END 0x100 /* Data End */ #define DAT_END 0x100 /* Data End */
#define nDAT_END 0x0
#define START_BIT_ERR 0x200 /* Start Bit Error */ #define START_BIT_ERR 0x200 /* Start Bit Error */
#define nSTART_BIT_ERR 0x0
#define DAT_BLK_END 0x400 /* Data Block End */ #define DAT_BLK_END 0x400 /* Data Block End */
#define nDAT_BLK_END 0x0
#define CMD_ACT 0x800 /* CMD Active */ #define CMD_ACT 0x800 /* CMD Active */
#define nCMD_ACT 0x0
#define TX_ACT 0x1000 /* Transmit Active */ #define TX_ACT 0x1000 /* Transmit Active */
#define nTX_ACT 0x0
#define RX_ACT 0x2000 /* Receive Active */ #define RX_ACT 0x2000 /* Receive Active */
#define nRX_ACT 0x0
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
#define nTX_FIFO_STAT 0x0
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
#define nRX_FIFO_STAT 0x0
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
#define nTX_FIFO_FULL 0x0
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
#define nRX_FIFO_FULL 0x0
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
#define nTX_FIFO_ZERO 0x0
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
#define nRX_DAT_ZERO 0x0
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ #define TX_DAT_RDY 0x100000 /* Transmit Data Available */
#define nTX_DAT_RDY 0x0
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ #define RX_FIFO_RDY 0x200000 /* Receive Data Available */
#define nRX_FIFO_RDY 0x0
/* Bit masks for SDH_STATUS_CLR */ /* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
#define nCMD_CRC_FAIL_STAT 0x0
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
#define nDAT_CRC_FAIL_STAT 0x0
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
#define nCMD_TIMEOUT_STAT 0x0
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
#define nDAT_TIMEOUT_STAT 0x0
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
#define nTX_UNDERRUN_STAT 0x0
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
#define nRX_OVERRUN_STAT 0x0
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
#define nCMD_RESP_END_STAT 0x0
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ #define CMD_SENT_STAT 0x80 /* CMD Sent Status */
#define nCMD_SENT_STAT 0x0
#define DAT_END_STAT 0x100 /* Data End Status */ #define DAT_END_STAT 0x100 /* Data End Status */
#define nDAT_END_STAT 0x0
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
#define nSTART_BIT_ERR_STAT 0x0
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
#define nDAT_BLK_END_STAT 0x0
/* Bit masks for SDH_MASK0 */ /* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
#define nCMD_CRC_FAIL_MASK 0x0
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
#define nDAT_CRC_FAIL_MASK 0x0
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
#define nCMD_TIMEOUT_MASK 0x0
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
#define nDAT_TIMEOUT_MASK 0x0
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
#define nTX_UNDERRUN_MASK 0x0
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
#define nRX_OVERRUN_MASK 0x0
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
#define nCMD_RESP_END_MASK 0x0
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
#define nCMD_SENT_MASK 0x0
#define DAT_END_MASK 0x100 /* Data End Mask */ #define DAT_END_MASK 0x100 /* Data End Mask */
#define nDAT_END_MASK 0x0
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
#define nSTART_BIT_ERR_MASK 0x0
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
#define nDAT_BLK_END_MASK 0x0
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ #define CMD_ACT_MASK 0x800 /* CMD Active Mask */
#define nCMD_ACT_MASK 0x0
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
#define nTX_ACT_MASK 0x0
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ #define RX_ACT_MASK 0x2000 /* Receive Active Mask */
#define nRX_ACT_MASK 0x0
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
#define nTX_FIFO_STAT_MASK 0x0
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
#define nRX_FIFO_STAT_MASK 0x0
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
#define nTX_FIFO_FULL_MASK 0x0
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
#define nRX_FIFO_FULL_MASK 0x0
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
#define nTX_FIFO_ZERO_MASK 0x0
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
#define nRX_DAT_ZERO_MASK 0x0
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
#define nTX_DAT_RDY_MASK 0x0
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
#define nRX_FIFO_RDY_MASK 0x0
/* Bit masks for SDH_FIFO_CNT */ /* Bit masks for SDH_FIFO_CNT */
@ -573,73 +499,47 @@
/* Bit masks for SDH_E_STATUS */ /* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */
#define nSDIO_INT_DET 0x0
#define SD_CARD_DET 0x10 /* SD Card Detect */ #define SD_CARD_DET 0x10 /* SD Card Detect */
#define nSD_CARD_DET 0x0
/* Bit masks for SDH_E_MASK */ /* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
#define nSDIO_MSK 0x0
#define SCD_MSK 0x40 /* Mask Card Detect */ #define SCD_MSK 0x40 /* Mask Card Detect */
#define nSCD_MSK 0x0
/* Bit masks for SDH_CFG */ /* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */ #define CLKS_EN 0x1 /* Clocks Enable */
#define nCLKS_EN 0x0
#define SD4E 0x4 /* SDIO 4-Bit Enable */ #define SD4E 0x4 /* SDIO 4-Bit Enable */
#define nSD4E 0x0
#define MWE 0x8 /* Moving Window Enable */ #define MWE 0x8 /* Moving Window Enable */
#define nMWE 0x0
#define SD_RST 0x10 /* SDMMC Reset */ #define SD_RST 0x10 /* SDMMC Reset */
#define nSD_RST 0x0
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
#define nPUP_SDDAT 0x0
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
#define nPUP_SDDAT3 0x0
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
#define nPD_SDDAT3 0x0
/* Bit masks for SDH_RD_WAIT_EN */ /* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */ #define RWR 0x1 /* Read Wait Request */
#define nRWR 0x0
/* Bit masks for ATAPI_CONTROL */ /* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */ #define PIO_START 0x1 /* Start PIO/Reg Op */
#define nPIO_START 0x0
#define MULTI_START 0x2 /* Start Multi-DMA Op */ #define MULTI_START 0x2 /* Start Multi-DMA Op */
#define nMULTI_START 0x0
#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ #define ULTRA_START 0x4 /* Start Ultra-DMA Op */
#define nULTRA_START 0x0
#define XFER_DIR 0x8 /* Transfer Direction */ #define XFER_DIR 0x8 /* Transfer Direction */
#define nXFER_DIR 0x0
#define IORDY_EN 0x10 /* IORDY Enable */ #define IORDY_EN 0x10 /* IORDY Enable */
#define nIORDY_EN 0x0
#define FIFO_FLUSH 0x20 /* Flush FIFOs */ #define FIFO_FLUSH 0x20 /* Flush FIFOs */
#define nFIFO_FLUSH 0x0
#define SOFT_RST 0x40 /* Soft Reset */ #define SOFT_RST 0x40 /* Soft Reset */
#define nSOFT_RST 0x0
#define DEV_RST 0x80 /* Device Reset */ #define DEV_RST 0x80 /* Device Reset */
#define nDEV_RST 0x0
#define TFRCNT_RST 0x100 /* Trans Count Reset */ #define TFRCNT_RST 0x100 /* Trans Count Reset */
#define nTFRCNT_RST 0x0
#define END_ON_TERM 0x200 /* End/Terminate Select */ #define END_ON_TERM 0x200 /* End/Terminate Select */
#define nEND_ON_TERM 0x0
#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
#define nPIO_USE_DMA 0x0
#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
/* Bit masks for ATAPI_STATUS */ /* Bit masks for ATAPI_STATUS */
#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */
#define nPIO_XFER_ON 0x0
#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
#define nMULTI_XFER_ON 0x0
#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
#define nULTRA_XFER_ON 0x0
#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
/* Bit masks for ATAPI_DEV_ADDR */ /* Bit masks for ATAPI_DEV_ADDR */
@ -649,66 +549,39 @@
/* Bit masks for ATAPI_INT_MASK */ /* Bit masks for ATAPI_INT_MASK */
#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
#define nATAPI_DEV_INT_MASK 0x0
#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
#define nPIO_DONE_MASK 0x0
#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
#define nMULTI_DONE_MASK 0x0
#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
#define nUDMAIN_DONE_MASK 0x0
#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
#define nUDMAOUT_DONE_MASK 0x0
#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
#define nHOST_TERM_XFER_MASK 0x0
#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
#define nMULTI_TERM_MASK 0x0
#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
#define nUDMAIN_TERM_MASK 0x0
#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
#define nUDMAOUT_TERM_MASK 0x0
/* Bit masks for ATAPI_INT_STATUS */ /* Bit masks for ATAPI_INT_STATUS */
#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */
#define nATAPI_DEV_INT 0x0
#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
#define nPIO_DONE_INT 0x0
#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
#define nMULTI_DONE_INT 0x0
#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
#define nUDMAIN_DONE_INT 0x0
#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
#define nUDMAOUT_DONE_INT 0x0
#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
#define nHOST_TERM_XFER_INT 0x0
#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
#define nMULTI_TERM_INT 0x0
#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
#define nUDMAIN_TERM_INT 0x0
#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
#define nUDMAOUT_TERM_INT 0x0
/* Bit masks for ATAPI_LINE_STATUS */ /* Bit masks for ATAPI_LINE_STATUS */
#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */
#define nATAPI_INTR 0x0
#define ATAPI_DASP 0x2 /* Device dasp to host line status */ #define ATAPI_DASP 0x2 /* Device dasp to host line status */
#define nATAPI_DASP 0x0
#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
#define nATAPI_CS0N 0x0
#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
#define nATAPI_CS1N 0x0
#define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_ADDR 0x70 /* ATAPI address line status */
#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
#define nATAPI_DMAREQ 0x0
#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
#define nATAPI_DMAACKN 0x0
#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ #define ATAPI_DIOWN 0x200 /* ATAPI write line status */
#define nATAPI_DIOWN 0x0
#define ATAPI_DIORN 0x400 /* ATAPI read line status */ #define ATAPI_DIORN 0x400 /* ATAPI read line status */
#define nATAPI_DIORN 0x0
#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
#define nATAPI_IORDY 0x0
/* Bit masks for ATAPI_SM_STATE */ /* Bit masks for ATAPI_SM_STATE */
@ -720,7 +593,6 @@
/* Bit masks for ATAPI_TERMINATE */ /* Bit masks for ATAPI_TERMINATE */
#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */
#define nATAPI_HOST_TERM 0x0
/* Bit masks for ATAPI_REG_TIM_0 */ /* Bit masks for ATAPI_REG_TIM_0 */
@ -779,131 +651,77 @@
/* Bit masks for USB_POWER */ /* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
#define nENABLE_SUSPENDM 0x0
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
#define nSUSPEND_MODE 0x0
#define RESUME_MODE 0x4 /* DMA Mode */ #define RESUME_MODE 0x4 /* DMA Mode */
#define nRESUME_MODE 0x0
#define RESET 0x8 /* Reset indicator */ #define RESET 0x8 /* Reset indicator */
#define nRESET 0x0
#define HS_MODE 0x10 /* High Speed mode indicator */ #define HS_MODE 0x10 /* High Speed mode indicator */
#define nHS_MODE 0x0
#define HS_ENABLE 0x20 /* high Speed Enable */ #define HS_ENABLE 0x20 /* high Speed Enable */
#define nHS_ENABLE 0x0
#define SOFT_CONN 0x40 /* Soft connect */ #define SOFT_CONN 0x40 /* Soft connect */
#define nSOFT_CONN 0x0
#define ISO_UPDATE 0x80 /* Isochronous update */ #define ISO_UPDATE 0x80 /* Isochronous update */
#define nISO_UPDATE 0x0
/* Bit masks for USB_INTRTX */ /* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
#define nEP0_TX 0x0
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
#define nEP1_TX 0x0
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
#define nEP2_TX 0x0
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
#define nEP3_TX 0x0
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
#define nEP4_TX 0x0
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
#define nEP5_TX 0x0
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
#define nEP6_TX 0x0
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
#define nEP7_TX 0x0
/* Bit masks for USB_INTRRX */ /* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
#define nEP1_RX 0x0
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
#define nEP2_RX 0x0
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
#define nEP3_RX 0x0
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
#define nEP4_RX 0x0
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
#define nEP5_RX 0x0
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
#define nEP6_RX 0x0
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
#define nEP7_RX 0x0
/* Bit masks for USB_INTRTXE */ /* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
#define nEP0_TX_E 0x0
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
#define nEP1_TX_E 0x0
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
#define nEP2_TX_E 0x0
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
#define nEP3_TX_E 0x0
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
#define nEP4_TX_E 0x0
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
#define nEP5_TX_E 0x0
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
#define nEP6_TX_E 0x0
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
#define nEP7_TX_E 0x0
/* Bit masks for USB_INTRRXE */ /* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
#define nEP1_RX_E 0x0
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
#define nEP2_RX_E 0x0
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
#define nEP3_RX_E 0x0
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
#define nEP4_RX_E 0x0
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
#define nEP5_RX_E 0x0
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
#define nEP6_RX_E 0x0
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
#define nEP7_RX_E 0x0
/* Bit masks for USB_INTRUSB */ /* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */ #define SUSPEND_B 0x1 /* Suspend indicator */
#define nSUSPEND_B 0x0
#define RESUME_B 0x2 /* Resume indicator */ #define RESUME_B 0x2 /* Resume indicator */
#define nRESUME_B 0x0
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
#define nRESET_OR_BABLE_B 0x0
#define SOF_B 0x8 /* Start of frame */ #define SOF_B 0x8 /* Start of frame */
#define nSOF_B 0x0
#define CONN_B 0x10 /* Connection indicator */ #define CONN_B 0x10 /* Connection indicator */
#define nCONN_B 0x0
#define DISCON_B 0x20 /* Disconnect indicator */ #define DISCON_B 0x20 /* Disconnect indicator */
#define nDISCON_B 0x0
#define SESSION_REQ_B 0x40 /* Session Request */ #define SESSION_REQ_B 0x40 /* Session Request */
#define nSESSION_REQ_B 0x0
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
#define nVBUS_ERROR_B 0x0
/* Bit masks for USB_INTRUSBE */ /* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */
#define nSUSPEND_BE 0x0
#define RESUME_BE 0x2 /* Resume indicator int enable */ #define RESUME_BE 0x2 /* Resume indicator int enable */
#define nRESUME_BE 0x0
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
#define nRESET_OR_BABLE_BE 0x0
#define SOF_BE 0x8 /* Start of frame int enable */ #define SOF_BE 0x8 /* Start of frame int enable */
#define nSOF_BE 0x0
#define CONN_BE 0x10 /* Connection indicator int enable */ #define CONN_BE 0x10 /* Connection indicator int enable */
#define nCONN_BE 0x0
#define DISCON_BE 0x20 /* Disconnect indicator int enable */ #define DISCON_BE 0x20 /* Disconnect indicator int enable */
#define nDISCON_BE 0x0
#define SESSION_REQ_BE 0x40 /* Session Request int enable */ #define SESSION_REQ_BE 0x40 /* Session Request int enable */
#define nSESSION_REQ_BE 0x0
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
#define nVBUS_ERROR_BE 0x0
/* Bit masks for USB_FRAME */ /* Bit masks for USB_FRAME */
@ -916,117 +734,67 @@
/* Bit masks for USB_GLOBAL_CTL */ /* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */ #define GLOBAL_ENA 0x1 /* enables USB module */
#define nGLOBAL_ENA 0x0
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
#define nEP1_TX_ENA 0x0
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
#define nEP2_TX_ENA 0x0
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
#define nEP3_TX_ENA 0x0
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
#define nEP4_TX_ENA 0x0
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
#define nEP5_TX_ENA 0x0
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
#define nEP6_TX_ENA 0x0
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
#define nEP7_TX_ENA 0x0
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
#define nEP1_RX_ENA 0x0
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
#define nEP2_RX_ENA 0x0
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
#define nEP3_RX_ENA 0x0
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
#define nEP4_RX_ENA 0x0
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
#define nEP5_RX_ENA 0x0
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
#define nEP6_RX_ENA 0x0
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
#define nEP7_RX_ENA 0x0
/* Bit masks for USB_OTG_DEV_CTL */ /* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */ #define SESSION 0x1 /* session indicator */
#define nSESSION 0x0
#define HOST_REQ 0x2 /* Host negotiation request */ #define HOST_REQ 0x2 /* Host negotiation request */
#define nHOST_REQ 0x0
#define HOST_MODE 0x4 /* indicates USBDRC is a host */ #define HOST_MODE 0x4 /* indicates USBDRC is a host */
#define nHOST_MODE 0x0
#define VBUS0 0x8 /* Vbus level indicator[0] */ #define VBUS0 0x8 /* Vbus level indicator[0] */
#define nVBUS0 0x0
#define VBUS1 0x10 /* Vbus level indicator[1] */ #define VBUS1 0x10 /* Vbus level indicator[1] */
#define nVBUS1 0x0
#define LSDEV 0x20 /* Low-speed indicator */ #define LSDEV 0x20 /* Low-speed indicator */
#define nLSDEV 0x0
#define FSDEV 0x40 /* Full or High-speed indicator */ #define FSDEV 0x40 /* Full or High-speed indicator */
#define nFSDEV 0x0
#define B_DEVICE 0x80 /* A' or 'B' device indicator */ #define B_DEVICE 0x80 /* A' or 'B' device indicator */
#define nB_DEVICE 0x0
/* Bit masks for USB_OTG_VBUS_IRQ */ /* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
#define nDRIVE_VBUS_ON 0x0
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
#define nDRIVE_VBUS_OFF 0x0
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
#define nCHRG_VBUS_START 0x0
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
#define nCHRG_VBUS_END 0x0
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
#define nDISCHRG_VBUS_START 0x0
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
#define nDISCHRG_VBUS_END 0x0
/* Bit masks for USB_OTG_VBUS_MASK */ /* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
#define nDRIVE_VBUS_ON_ENA 0x0
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
#define nDRIVE_VBUS_OFF_ENA 0x0
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
#define nCHRG_VBUS_START_ENA 0x0
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
#define nCHRG_VBUS_END_ENA 0x0
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
#define nDISCHRG_VBUS_START_ENA 0x0
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
#define nDISCHRG_VBUS_END_ENA 0x0
/* Bit masks for USB_CSR0 */ /* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */ #define RXPKTRDY 0x1 /* data packet receive indicator */
#define nRXPKTRDY 0x0
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ #define TXPKTRDY 0x2 /* data packet in FIFO indicator */
#define nTXPKTRDY 0x0
#define STALL_SENT 0x4 /* STALL handshake sent */ #define STALL_SENT 0x4 /* STALL handshake sent */
#define nSTALL_SENT 0x0
#define DATAEND 0x8 /* Data end indicator */ #define DATAEND 0x8 /* Data end indicator */
#define nDATAEND 0x0
#define SETUPEND 0x10 /* Setup end */ #define SETUPEND 0x10 /* Setup end */
#define nSETUPEND 0x0
#define SENDSTALL 0x20 /* Send STALL handshake */ #define SENDSTALL 0x20 /* Send STALL handshake */
#define nSENDSTALL 0x0
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
#define nSERVICED_RXPKTRDY 0x0
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
#define nSERVICED_SETUPEND 0x0
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ #define FLUSHFIFO 0x100 /* flush endpoint FIFO */
#define nFLUSHFIFO 0x0
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
#define nSTALL_RECEIVED_H 0x0
#define SETUPPKT_H 0x8 /* send Setup token host mode */ #define SETUPPKT_H 0x8 /* send Setup token host mode */
#define nSETUPPKT_H 0x0
#define ERROR_H 0x10 /* timeout error indicator host mode */ #define ERROR_H 0x10 /* timeout error indicator host mode */
#define nERROR_H 0x0
#define REQPKT_H 0x20 /* Request an IN transaction host mode */ #define REQPKT_H 0x20 /* Request an IN transaction host mode */
#define nREQPKT_H 0x0
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ #define STATUSPKT_H 0x40 /* Status stage transaction host mode */
#define nSTATUSPKT_H 0x0
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
#define nNAK_TIMEOUT_H 0x0
/* Bit masks for USB_COUNT0 */ /* Bit masks for USB_COUNT0 */
@ -1047,37 +815,21 @@
/* Bit masks for USB_TXCSR */ /* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
#define nTXPKTRDY_T 0x0
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
#define nFIFO_NOT_EMPTY_T 0x0
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
#define nUNDERRUN_T 0x0
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
#define nFLUSHFIFO_T 0x0
#define STALL_SEND_T 0x10 /* issue a Stall handshake */ #define STALL_SEND_T 0x10 /* issue a Stall handshake */
#define nSTALL_SEND_T 0x0
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ #define STALL_SENT_T 0x20 /* Stall handshake transmitted */
#define nSTALL_SENT_T 0x0
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
#define nCLEAR_DATATOGGLE_T 0x0
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ #define INCOMPTX_T 0x80 /* indicates that a large packet is split */
#define nINCOMPTX_T 0x0
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
#define nDMAREQMODE_T 0x0
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
#define nFORCE_DATATOGGLE_T 0x0
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
#define nDMAREQ_ENA_T 0x0
#define ISO_T 0x4000 /* enable Isochronous transfers */ #define ISO_T 0x4000 /* enable Isochronous transfers */
#define nISO_T 0x0
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
#define nAUTOSET_T 0x0
#define ERROR_TH 0x4 /* error condition host mode */ #define ERROR_TH 0x4 /* error condition host mode */
#define nERROR_TH 0x0
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
#define nSTALL_RECEIVED_TH 0x0
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
#define nNAK_TIMEOUT_TH 0x0
/* Bit masks for USB_TXCOUNT */ /* Bit masks for USB_TXCOUNT */
@ -1086,45 +838,25 @@
/* Bit masks for USB_RXCSR */ /* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
#define nRXPKTRDY_R 0x0
#define FIFO_FULL_R 0x2 /* FIFO not empty */ #define FIFO_FULL_R 0x2 /* FIFO not empty */
#define nFIFO_FULL_R 0x0
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
#define nOVERRUN_R 0x0
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
#define nDATAERROR_R 0x0
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
#define nFLUSHFIFO_R 0x0
#define STALL_SEND_R 0x20 /* issue a Stall handshake */ #define STALL_SEND_R 0x20 /* issue a Stall handshake */
#define nSTALL_SEND_R 0x0
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ #define STALL_SENT_R 0x40 /* Stall handshake transmitted */
#define nSTALL_SENT_R 0x0
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
#define nCLEAR_DATATOGGLE_R 0x0
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ #define INCOMPRX_R 0x100 /* indicates that a large packet is split */
#define nINCOMPRX_R 0x0
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
#define nDMAREQMODE_R 0x0
#define DISNYET_R 0x1000 /* disable Nyet handshakes */ #define DISNYET_R 0x1000 /* disable Nyet handshakes */
#define nDISNYET_R 0x0
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
#define nDMAREQ_ENA_R 0x0
#define ISO_R 0x4000 /* enable Isochronous transfers */ #define ISO_R 0x4000 /* enable Isochronous transfers */
#define nISO_R 0x0
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
#define nAUTOCLEAR_R 0x0
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
#define nERROR_RH 0x0
#define REQPKT_RH 0x20 /* request an IN transaction host mode */ #define REQPKT_RH 0x20 /* request an IN transaction host mode */
#define nREQPKT_RH 0x0
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
#define nSTALL_RECEIVED_RH 0x0
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
#define nINCOMPRX_RH 0x0
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
#define nDMAREQMODE_RH 0x0
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
#define nAUTOREQ_RH 0x0
/* Bit masks for USB_RXCOUNT */ /* Bit masks for USB_RXCOUNT */
@ -1151,35 +883,22 @@
/* Bit masks for USB_DMA_INTERRUPT */ /* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */
#define nDMA0_INT 0x0
#define DMA1_INT 0x2 /* DMA1 pending interrupt */ #define DMA1_INT 0x2 /* DMA1 pending interrupt */
#define nDMA1_INT 0x0
#define DMA2_INT 0x4 /* DMA2 pending interrupt */ #define DMA2_INT 0x4 /* DMA2 pending interrupt */
#define nDMA2_INT 0x0
#define DMA3_INT 0x8 /* DMA3 pending interrupt */ #define DMA3_INT 0x8 /* DMA3 pending interrupt */
#define nDMA3_INT 0x0
#define DMA4_INT 0x10 /* DMA4 pending interrupt */ #define DMA4_INT 0x10 /* DMA4 pending interrupt */
#define nDMA4_INT 0x0
#define DMA5_INT 0x20 /* DMA5 pending interrupt */ #define DMA5_INT 0x20 /* DMA5 pending interrupt */
#define nDMA5_INT 0x0
#define DMA6_INT 0x40 /* DMA6 pending interrupt */ #define DMA6_INT 0x40 /* DMA6 pending interrupt */
#define nDMA6_INT 0x0
#define DMA7_INT 0x80 /* DMA7 pending interrupt */ #define DMA7_INT 0x80 /* DMA7 pending interrupt */
#define nDMA7_INT 0x0
/* Bit masks for USB_DMAxCONTROL */ /* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */ #define DMA_ENA 0x1 /* DMA enable */
#define nDMA_ENA 0x0
#define DIRECTION 0x2 /* direction of DMA transfer */ #define DIRECTION 0x2 /* direction of DMA transfer */
#define nDIRECTION 0x0
#define MODE 0x4 /* DMA Bus error */ #define MODE 0x4 /* DMA Bus error */
#define nMODE 0x0
#define INT_ENA 0x8 /* Interrupt enable */ #define INT_ENA 0x8 /* Interrupt enable */
#define nINT_ENA 0x0
#define EPNUM 0xf0 /* EP number */ #define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */ #define BUSERROR 0x100 /* DMA Bus error */
#define nBUSERROR 0x0
/* Bit masks for USB_DMAxADDRHIGH */ /* Bit masks for USB_DMAxADDRHIGH */

60
include/asm-blackfin/mach-bf548/defBF544.h
View File

@ -538,21 +538,13 @@
/* Bit masks for PIXC_CTL */ /* Bit masks for PIXC_CTL */
#define PIXC_EN 0x1 /* Pixel Compositor Enable */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */
#define nPIXC_EN 0x0
#define OVR_A_EN 0x2 /* Overlay A Enable */ #define OVR_A_EN 0x2 /* Overlay A Enable */
#define nOVR_A_EN 0x0
#define OVR_B_EN 0x4 /* Overlay B Enable */ #define OVR_B_EN 0x4 /* Overlay B Enable */
#define nOVR_B_EN 0x0
#define IMG_FORM 0x8 /* Image Data Format */ #define IMG_FORM 0x8 /* Image Data Format */
#define nIMG_FORM 0x0
#define OVR_FORM 0x10 /* Overlay Data Format */ #define OVR_FORM 0x10 /* Overlay Data Format */
#define nOVR_FORM 0x0
#define OUT_FORM 0x20 /* Output Data Format */ #define OUT_FORM 0x20 /* Output Data Format */
#define nOUT_FORM 0x0
#define UDS_MOD 0x40 /* Resampling Mode */ #define UDS_MOD 0x40 /* Resampling Mode */
#define nUDS_MOD 0x0
#define TC_EN 0x80 /* Transparent Color Enable */ #define TC_EN 0x80 /* Transparent Color Enable */
#define nTC_EN 0x0
#define IMG_STAT 0x300 /* Image FIFO Status */ #define IMG_STAT 0x300 /* Image FIFO Status */
#define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */
#define WM_LVL 0x3000 /* FIFO Watermark Level */ #define WM_LVL 0x3000 /* FIFO Watermark Level */
@ -600,13 +592,9 @@
/* Bit masks for PIXC_INTRSTAT */ /* Bit masks for PIXC_INTRSTAT */
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
#define nOVR_INT_EN 0x0
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
#define nFRM_INT_EN 0x0
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
#define nOVR_INT_STAT 0x0
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
#define nFRM_INT_STAT 0x0
/* Bit masks for PIXC_RYCON */ /* Bit masks for PIXC_RYCON */
@ -614,7 +602,6 @@
#define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A12 0xffc00 /* A12 in the Coefficient Matrix */
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */
#define nRY_MULT4 0x0
/* Bit masks for PIXC_GUCON */ /* Bit masks for PIXC_GUCON */
@ -622,7 +609,6 @@
#define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A22 0xffc00 /* A22 in the Coefficient Matrix */
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */
#define nGU_MULT4 0x0
/* Bit masks for PIXC_BVCON */ /* Bit masks for PIXC_BVCON */
@ -630,7 +616,6 @@
#define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A32 0xffc00 /* A32 in the Coefficient Matrix */
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */
#define nBV_MULT4 0x0
/* Bit masks for PIXC_CCBIAS */ /* Bit masks for PIXC_CCBIAS */
@ -647,48 +632,28 @@
/* Bit masks for HOST_CONTROL */ /* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1 /* Host Enable */ #define HOST_EN 0x1 /* Host Enable */
#define nHOST_EN 0x0
#define HOST_END 0x2 /* Host Endianess */ #define HOST_END 0x2 /* Host Endianess */
#define nHOST_END 0x0
#define DATA_SIZE 0x4 /* Data Size */ #define DATA_SIZE 0x4 /* Data Size */
#define nDATA_SIZE 0x0
#define HOST_RST 0x8 /* Host Reset */ #define HOST_RST 0x8 /* Host Reset */
#define nHOST_RST 0x0
#define HRDY_OVR 0x20 /* Host Ready Override */ #define HRDY_OVR 0x20 /* Host Ready Override */
#define nHRDY_OVR 0x0
#define INT_MODE 0x40 /* Interrupt Mode */ #define INT_MODE 0x40 /* Interrupt Mode */
#define nINT_MODE 0x0
#define BT_EN 0x80 /* Bus Timeout Enable */ #define BT_EN 0x80 /* Bus Timeout Enable */
#define nBT_EN 0x0
#define EHW 0x100 /* Enable Host Write */ #define EHW 0x100 /* Enable Host Write */
#define nEHW 0x0
#define EHR 0x200 /* Enable Host Read */ #define EHR 0x200 /* Enable Host Read */
#define nEHR 0x0
#define BDR 0x400 /* Burst DMA Requests */ #define BDR 0x400 /* Burst DMA Requests */
#define nBDR 0x0
/* Bit masks for HOST_STATUS */ /* Bit masks for HOST_STATUS */
#define READY 0x1 /* DMA Ready */ #define READY 0x1 /* DMA Ready */
#define nREADY 0x0
#define FIFOFULL 0x2 /* FIFO Full */ #define FIFOFULL 0x2 /* FIFO Full */
#define nFIFOFULL 0x0
#define FIFOEMPTY 0x4 /* FIFO Empty */ #define FIFOEMPTY 0x4 /* FIFO Empty */
#define nFIFOEMPTY 0x0
#define COMPLETE 0x8 /* DMA Complete */ #define COMPLETE 0x8 /* DMA Complete */
#define nCOMPLETE 0x0
#define HSHK 0x10 /* Host Handshake */ #define HSHK 0x10 /* Host Handshake */
#define nHSHK 0x0
#define TIMEOUT 0x20 /* Host Timeout */ #define TIMEOUT 0x20 /* Host Timeout */
#define nTIMEOUT 0x0
#define HIRQ 0x40 /* Host Interrupt Request */ #define HIRQ 0x40 /* Host Interrupt Request */
#define nHIRQ 0x0
#define ALLOW_CNFG 0x80 /* Allow New Configuration */ #define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define nALLOW_CNFG 0x0
#define DMA_DIR 0x100 /* DMA Direction */ #define DMA_DIR 0x100 /* DMA Direction */
#define nDMA_DIR 0x0
#define BTE 0x200 /* Bus Timeout Enabled */ #define BTE 0x200 /* Bus Timeout Enabled */
#define nBTE 0x0
/* Bit masks for HOST_TIMEOUT */ /* Bit masks for HOST_TIMEOUT */
@ -697,67 +662,42 @@
/* Bit masks for TIMER_ENABLE1 */ /* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */ #define TIMEN8 0x1 /* Timer 8 Enable */
#define nTIMEN8 0x0
#define TIMEN9 0x2 /* Timer 9 Enable */ #define TIMEN9 0x2 /* Timer 9 Enable */
#define nTIMEN9 0x0
#define TIMEN10 0x4 /* Timer 10 Enable */ #define TIMEN10 0x4 /* Timer 10 Enable */
#define nTIMEN10 0x0
/* Bit masks for TIMER_DISABLE1 */ /* Bit masks for TIMER_DISABLE1 */
#define TIMDIS8 0x1 /* Timer 8 Disable */ #define TIMDIS8 0x1 /* Timer 8 Disable */
#define nTIMDIS8 0x0
#define TIMDIS9 0x2 /* Timer 9 Disable */ #define TIMDIS9 0x2 /* Timer 9 Disable */
#define nTIMDIS9 0x0
#define TIMDIS10 0x4 /* Timer 10 Disable */ #define TIMDIS10 0x4 /* Timer 10 Disable */
#define nTIMDIS10 0x0
/* Bit masks for TIMER_STATUS1 */ /* Bit masks for TIMER_STATUS1 */
#define TIMIL8 0x1 /* Timer 8 Interrupt */ #define TIMIL8 0x1 /* Timer 8 Interrupt */
#define nTIMIL8 0x0
#define TIMIL9 0x2 /* Timer 9 Interrupt */ #define TIMIL9 0x2 /* Timer 9 Interrupt */
#define nTIMIL9 0x0
#define TIMIL10 0x4 /* Timer 10 Interrupt */ #define TIMIL10 0x4 /* Timer 10 Interrupt */
#define nTIMIL10 0x0
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
#define nTOVF_ERR8 0x0
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
#define nTOVF_ERR9 0x0
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
#define nTOVF_ERR10 0x0
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
#define nTRUN8 0x0
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
#define nTRUN9 0x0
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
#define nTRUN10 0x0
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
/* Bit masks for HMDMAx_CONTROL */ /* Bit masks for HMDMAx_CONTROL */
#define HMDMAEN 0x1 /* Handshake MDMA Enable */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */
#define nHMDMAEN 0x0
#define REP 0x2 /* Handshake MDMA Request Polarity */ #define REP 0x2 /* Handshake MDMA Request Polarity */
#define nREP 0x0
#define UTE 0x8 /* Urgency Threshold Enable */ #define UTE 0x8 /* Urgency Threshold Enable */
#define nUTE 0x0
#define OIE 0x10 /* Overflow Interrupt Enable */ #define OIE 0x10 /* Overflow Interrupt Enable */
#define nOIE 0x0
#define BDIE 0x20 /* Block Done Interrupt Enable */ #define BDIE 0x20 /* Block Done Interrupt Enable */
#define nBDIE 0x0
#define MBDI 0x40 /* Mask Block Done Interrupt */ #define MBDI 0x40 /* Mask Block Done Interrupt */
#define nMBDI 0x0
#define DRQ 0x300 /* Handshake MDMA Request Type */ #define DRQ 0x300 /* Handshake MDMA Request Type */
#define RBC 0x1000 /* Force Reload of BCOUNT */ #define RBC 0x1000 /* Force Reload of BCOUNT */
#define nRBC 0x0
#define PS 0x2000 /* Pin Status */ #define PS 0x2000 /* Pin Status */
#define nPS 0x0
#define OI 0x4000 /* Overflow Interrupt Generated */ #define OI 0x4000 /* Overflow Interrupt Generated */
#define nOI 0x0
#define BDI 0x8000 /* Block Done Interrupt Generated */ #define BDI 0x8000 /* Block Done Interrupt Generated */
#define nBDI 0x0
/* ******************************************* */ /* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */ /* MULTI BIT MACRO ENUMERATIONS */

341
include/asm-blackfin/mach-bf548/defBF548.h
View File

@ -899,21 +899,13 @@
/* Bit masks for PIXC_CTL */ /* Bit masks for PIXC_CTL */
#define PIXC_EN 0x1 /* Pixel Compositor Enable */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */
#define nPIXC_EN 0x0
#define OVR_A_EN 0x2 /* Overlay A Enable */ #define OVR_A_EN 0x2 /* Overlay A Enable */
#define nOVR_A_EN 0x0
#define OVR_B_EN 0x4 /* Overlay B Enable */ #define OVR_B_EN 0x4 /* Overlay B Enable */
#define nOVR_B_EN 0x0
#define IMG_FORM 0x8 /* Image Data Format */ #define IMG_FORM 0x8 /* Image Data Format */
#define nIMG_FORM 0x0
#define OVR_FORM 0x10 /* Overlay Data Format */ #define OVR_FORM 0x10 /* Overlay Data Format */
#define nOVR_FORM 0x0
#define OUT_FORM 0x20 /* Output Data Format */ #define OUT_FORM 0x20 /* Output Data Format */
#define nOUT_FORM 0x0
#define UDS_MOD 0x40 /* Resampling Mode */ #define UDS_MOD 0x40 /* Resampling Mode */
#define nUDS_MOD 0x0
#define TC_EN 0x80 /* Transparent Color Enable */ #define TC_EN 0x80 /* Transparent Color Enable */
#define nTC_EN 0x0
#define IMG_STAT 0x300 /* Image FIFO Status */ #define IMG_STAT 0x300 /* Image FIFO Status */
#define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */
#define WM_LVL 0x3000 /* FIFO Watermark Level */ #define WM_LVL 0x3000 /* FIFO Watermark Level */
@ -961,13 +953,9 @@
/* Bit masks for PIXC_INTRSTAT */ /* Bit masks for PIXC_INTRSTAT */
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
#define nOVR_INT_EN 0x0
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
#define nFRM_INT_EN 0x0
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
#define nOVR_INT_STAT 0x0
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
#define nFRM_INT_STAT 0x0
/* Bit masks for PIXC_RYCON */ /* Bit masks for PIXC_RYCON */
@ -975,7 +963,6 @@
#define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A12 0xffc00 /* A12 in the Coefficient Matrix */
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */
#define nRY_MULT4 0x0
/* Bit masks for PIXC_GUCON */ /* Bit masks for PIXC_GUCON */
@ -983,7 +970,6 @@
#define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A22 0xffc00 /* A22 in the Coefficient Matrix */
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */
#define nGU_MULT4 0x0
/* Bit masks for PIXC_BVCON */ /* Bit masks for PIXC_BVCON */
@ -991,7 +977,6 @@
#define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A32 0xffc00 /* A32 in the Coefficient Matrix */
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */
#define nBV_MULT4 0x0
/* Bit masks for PIXC_CCBIAS */ /* Bit masks for PIXC_CCBIAS */
@ -1008,48 +993,28 @@
/* Bit masks for HOST_CONTROL */ /* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1 /* Host Enable */ #define HOST_EN 0x1 /* Host Enable */
#define nHOST_EN 0x0
#define HOST_END 0x2 /* Host Endianess */ #define HOST_END 0x2 /* Host Endianess */
#define nHOST_END 0x0
#define DATA_SIZE 0x4 /* Data Size */ #define DATA_SIZE 0x4 /* Data Size */
#define nDATA_SIZE 0x0
#define HOST_RST 0x8 /* Host Reset */ #define HOST_RST 0x8 /* Host Reset */
#define nHOST_RST 0x0
#define HRDY_OVR 0x20 /* Host Ready Override */ #define HRDY_OVR 0x20 /* Host Ready Override */
#define nHRDY_OVR 0x0
#define INT_MODE 0x40 /* Interrupt Mode */ #define INT_MODE 0x40 /* Interrupt Mode */
#define nINT_MODE 0x0
#define BT_EN 0x80 /* Bus Timeout Enable */ #define BT_EN 0x80 /* Bus Timeout Enable */
#define nBT_EN 0x0
#define EHW 0x100 /* Enable Host Write */ #define EHW 0x100 /* Enable Host Write */
#define nEHW 0x0
#define EHR 0x200 /* Enable Host Read */ #define EHR 0x200 /* Enable Host Read */
#define nEHR 0x0
#define BDR 0x400 /* Burst DMA Requests */ #define BDR 0x400 /* Burst DMA Requests */
#define nBDR 0x0
/* Bit masks for HOST_STATUS */ /* Bit masks for HOST_STATUS */
#define READY 0x1 /* DMA Ready */ #define READY 0x1 /* DMA Ready */
#define nREADY 0x0
#define FIFOFULL 0x2 /* FIFO Full */ #define FIFOFULL 0x2 /* FIFO Full */
#define nFIFOFULL 0x0
#define FIFOEMPTY 0x4 /* FIFO Empty */ #define FIFOEMPTY 0x4 /* FIFO Empty */
#define nFIFOEMPTY 0x0
#define COMPLETE 0x8 /* DMA Complete */ #define COMPLETE 0x8 /* DMA Complete */
#define nCOMPLETE 0x0
#define HSHK 0x10 /* Host Handshake */ #define HSHK 0x10 /* Host Handshake */
#define nHSHK 0x0
#define TIMEOUT 0x20 /* Host Timeout */ #define TIMEOUT 0x20 /* Host Timeout */
#define nTIMEOUT 0x0
#define HIRQ 0x40 /* Host Interrupt Request */ #define HIRQ 0x40 /* Host Interrupt Request */
#define nHIRQ 0x0
#define ALLOW_CNFG 0x80 /* Allow New Configuration */ #define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define nALLOW_CNFG 0x0
#define DMA_DIR 0x100 /* DMA Direction */ #define DMA_DIR 0x100 /* DMA Direction */
#define nDMA_DIR 0x0
#define BTE 0x200 /* Bus Timeout Enabled */ #define BTE 0x200 /* Bus Timeout Enabled */
#define nBTE 0x0
/* Bit masks for HOST_TIMEOUT */ /* Bit masks for HOST_TIMEOUT */
@ -1058,7 +1023,6 @@
/* Bit masks for KPAD_CTL */ /* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1 /* Keypad Enable */ #define KPAD_EN 0x1 /* Keypad Enable */
#define nKPAD_EN 0x0
#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */
@ -1080,29 +1044,21 @@
/* Bit masks for KPAD_STAT */ /* Bit masks for KPAD_STAT */
#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
#define nKPAD_IRQ 0x0
#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
#define KPAD_PRESSED 0x8 /* Key press current status */ #define KPAD_PRESSED 0x8 /* Key press current status */
#define nKPAD_PRESSED 0x0
/* Bit masks for KPAD_SOFTEVAL */ /* Bit masks for KPAD_SOFTEVAL */
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
#define nKPAD_SOFTEVAL_E 0x0
/* Bit masks for SDH_COMMAND */ /* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */ #define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */ #define CMD_RSP 0x40 /* Response */
#define nCMD_RSP 0x0
#define CMD_L_RSP 0x80 /* Long Response */ #define CMD_L_RSP 0x80 /* Long Response */
#define nCMD_L_RSP 0x0
#define CMD_INT_E 0x100 /* Command Interrupt */ #define CMD_INT_E 0x100 /* Command Interrupt */
#define nCMD_INT_E 0x0
#define CMD_PEND_E 0x200 /* Command Pending */ #define CMD_PEND_E 0x200 /* Command Pending */
#define nCMD_PEND_E 0x0
#define CMD_E 0x400 /* Command Enable */ #define CMD_E 0x400 /* Command Enable */
#define nCMD_E 0x0
/* Bit masks for SDH_PWR_CTL */ /* Bit masks for SDH_PWR_CTL */
@ -1111,21 +1067,15 @@
#define TBD 0x3c /* TBD */ #define TBD 0x3c /* TBD */
#endif #endif
#define SD_CMD_OD 0x40 /* Open Drain Output */ #define SD_CMD_OD 0x40 /* Open Drain Output */
#define nSD_CMD_OD 0x0
#define ROD_CTL 0x80 /* Rod Control */ #define ROD_CTL 0x80 /* Rod Control */
#define nROD_CTL 0x0
/* Bit masks for SDH_CLK_CTL */ /* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */ #define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
#define nCLK_E 0x0
#define PWR_SV_E 0x200 /* Power Save Enable */ #define PWR_SV_E 0x200 /* Power Save Enable */
#define nPWR_SV_E 0x0
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
#define nCLKDIV_BYPASS 0x0
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
#define nWIDE_BUS 0x0
/* Bit masks for SDH_RESP_CMD */ /* Bit masks for SDH_RESP_CMD */
@ -1134,133 +1084,74 @@
/* Bit masks for SDH_DATA_CTL */ /* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */ #define DTX_E 0x1 /* Data Transfer Enable */
#define nDTX_E 0x0
#define DTX_DIR 0x2 /* Data Transfer Direction */ #define DTX_DIR 0x2 /* Data Transfer Direction */
#define nDTX_DIR 0x0
#define DTX_MODE 0x4 /* Data Transfer Mode */ #define DTX_MODE 0x4 /* Data Transfer Mode */
#define nDTX_MODE 0x0
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
#define nDTX_DMA_E 0x0
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */ /* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define nCMD_CRC_FAIL 0x0
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
#define nDAT_CRC_FAIL 0x0
#define CMD_TIMEOUT 0x4 /* CMD Time Out */ #define CMD_TIMEOUT 0x4 /* CMD Time Out */
#define nCMD_TIMEOUT 0x0
#define DAT_TIMEOUT 0x8 /* Data Time Out */ #define DAT_TIMEOUT 0x8 /* Data Time Out */
#define nDAT_TIMEOUT 0x0
#define TX_UNDERRUN 0x10 /* Transmit Underrun */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define nTX_UNDERRUN 0x0
#define RX_OVERRUN 0x20 /* Receive Overrun */ #define RX_OVERRUN 0x20 /* Receive Overrun */
#define nRX_OVERRUN 0x0
#define CMD_RESP_END 0x40 /* CMD Response End */ #define CMD_RESP_END 0x40 /* CMD Response End */
#define nCMD_RESP_END 0x0
#define CMD_SENT 0x80 /* CMD Sent */ #define CMD_SENT 0x80 /* CMD Sent */
#define nCMD_SENT 0x0
#define DAT_END 0x100 /* Data End */ #define DAT_END 0x100 /* Data End */
#define nDAT_END 0x0
#define START_BIT_ERR 0x200 /* Start Bit Error */ #define START_BIT_ERR 0x200 /* Start Bit Error */
#define nSTART_BIT_ERR 0x0
#define DAT_BLK_END 0x400 /* Data Block End */ #define DAT_BLK_END 0x400 /* Data Block End */
#define nDAT_BLK_END 0x0
#define CMD_ACT 0x800 /* CMD Active */ #define CMD_ACT 0x800 /* CMD Active */
#define nCMD_ACT 0x0
#define TX_ACT 0x1000 /* Transmit Active */ #define TX_ACT 0x1000 /* Transmit Active */
#define nTX_ACT 0x0
#define RX_ACT 0x2000 /* Receive Active */ #define RX_ACT 0x2000 /* Receive Active */
#define nRX_ACT 0x0
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
#define nTX_FIFO_STAT 0x0
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
#define nRX_FIFO_STAT 0x0
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
#define nTX_FIFO_FULL 0x0
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
#define nRX_FIFO_FULL 0x0
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
#define nTX_FIFO_ZERO 0x0
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
#define nRX_DAT_ZERO 0x0
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ #define TX_DAT_RDY 0x100000 /* Transmit Data Available */
#define nTX_DAT_RDY 0x0
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ #define RX_FIFO_RDY 0x200000 /* Receive Data Available */
#define nRX_FIFO_RDY 0x0
/* Bit masks for SDH_STATUS_CLR */ /* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
#define nCMD_CRC_FAIL_STAT 0x0
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
#define nDAT_CRC_FAIL_STAT 0x0
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
#define nCMD_TIMEOUT_STAT 0x0
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
#define nDAT_TIMEOUT_STAT 0x0
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
#define nTX_UNDERRUN_STAT 0x0
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
#define nRX_OVERRUN_STAT 0x0
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
#define nCMD_RESP_END_STAT 0x0
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ #define CMD_SENT_STAT 0x80 /* CMD Sent Status */
#define nCMD_SENT_STAT 0x0
#define DAT_END_STAT 0x100 /* Data End Status */ #define DAT_END_STAT 0x100 /* Data End Status */
#define nDAT_END_STAT 0x0
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
#define nSTART_BIT_ERR_STAT 0x0
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
#define nDAT_BLK_END_STAT 0x0
/* Bit masks for SDH_MASK0 */ /* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
#define nCMD_CRC_FAIL_MASK 0x0
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
#define nDAT_CRC_FAIL_MASK 0x0
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
#define nCMD_TIMEOUT_MASK 0x0
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
#define nDAT_TIMEOUT_MASK 0x0
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
#define nTX_UNDERRUN_MASK 0x0
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
#define nRX_OVERRUN_MASK 0x0
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
#define nCMD_RESP_END_MASK 0x0
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
#define nCMD_SENT_MASK 0x0
#define DAT_END_MASK 0x100 /* Data End Mask */ #define DAT_END_MASK 0x100 /* Data End Mask */
#define nDAT_END_MASK 0x0
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
#define nSTART_BIT_ERR_MASK 0x0
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
#define nDAT_BLK_END_MASK 0x0
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ #define CMD_ACT_MASK 0x800 /* CMD Active Mask */
#define nCMD_ACT_MASK 0x0
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
#define nTX_ACT_MASK 0x0
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ #define RX_ACT_MASK 0x2000 /* Receive Active Mask */
#define nRX_ACT_MASK 0x0
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
#define nTX_FIFO_STAT_MASK 0x0
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
#define nRX_FIFO_STAT_MASK 0x0
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
#define nTX_FIFO_FULL_MASK 0x0
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
#define nRX_FIFO_FULL_MASK 0x0
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
#define nTX_FIFO_ZERO_MASK 0x0
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
#define nRX_DAT_ZERO_MASK 0x0
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
#define nTX_DAT_RDY_MASK 0x0
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
#define nRX_FIFO_RDY_MASK 0x0
/* Bit masks for SDH_FIFO_CNT */ /* Bit masks for SDH_FIFO_CNT */
@ -1269,73 +1160,47 @@
/* Bit masks for SDH_E_STATUS */ /* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */
#define nSDIO_INT_DET 0x0
#define SD_CARD_DET 0x10 /* SD Card Detect */ #define SD_CARD_DET 0x10 /* SD Card Detect */
#define nSD_CARD_DET 0x0
/* Bit masks for SDH_E_MASK */ /* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
#define nSDIO_MSK 0x0
#define SCD_MSK 0x40 /* Mask Card Detect */ #define SCD_MSK 0x40 /* Mask Card Detect */
#define nSCD_MSK 0x0
/* Bit masks for SDH_CFG */ /* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */ #define CLKS_EN 0x1 /* Clocks Enable */
#define nCLKS_EN 0x0
#define SD4E 0x4 /* SDIO 4-Bit Enable */ #define SD4E 0x4 /* SDIO 4-Bit Enable */
#define nSD4E 0x0
#define MWE 0x8 /* Moving Window Enable */ #define MWE 0x8 /* Moving Window Enable */
#define nMWE 0x0
#define SD_RST 0x10 /* SDMMC Reset */ #define SD_RST 0x10 /* SDMMC Reset */
#define nSD_RST 0x0
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
#define nPUP_SDDAT 0x0
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
#define nPUP_SDDAT3 0x0
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
#define nPD_SDDAT3 0x0
/* Bit masks for SDH_RD_WAIT_EN */ /* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */ #define RWR 0x1 /* Read Wait Request */
#define nRWR 0x0
/* Bit masks for ATAPI_CONTROL */ /* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */ #define PIO_START 0x1 /* Start PIO/Reg Op */
#define nPIO_START 0x0
#define MULTI_START 0x2 /* Start Multi-DMA Op */ #define MULTI_START 0x2 /* Start Multi-DMA Op */
#define nMULTI_START 0x0
#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ #define ULTRA_START 0x4 /* Start Ultra-DMA Op */
#define nULTRA_START 0x0
#define XFER_DIR 0x8 /* Transfer Direction */ #define XFER_DIR 0x8 /* Transfer Direction */
#define nXFER_DIR 0x0
#define IORDY_EN 0x10 /* IORDY Enable */ #define IORDY_EN 0x10 /* IORDY Enable */
#define nIORDY_EN 0x0
#define FIFO_FLUSH 0x20 /* Flush FIFOs */ #define FIFO_FLUSH 0x20 /* Flush FIFOs */
#define nFIFO_FLUSH 0x0
#define SOFT_RST 0x40 /* Soft Reset */ #define SOFT_RST 0x40 /* Soft Reset */
#define nSOFT_RST 0x0
#define DEV_RST 0x80 /* Device Reset */ #define DEV_RST 0x80 /* Device Reset */
#define nDEV_RST 0x0
#define TFRCNT_RST 0x100 /* Trans Count Reset */ #define TFRCNT_RST 0x100 /* Trans Count Reset */
#define nTFRCNT_RST 0x0
#define END_ON_TERM 0x200 /* End/Terminate Select */ #define END_ON_TERM 0x200 /* End/Terminate Select */
#define nEND_ON_TERM 0x0
#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
#define nPIO_USE_DMA 0x0
#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
/* Bit masks for ATAPI_STATUS */ /* Bit masks for ATAPI_STATUS */
#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */
#define nPIO_XFER_ON 0x0
#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
#define nMULTI_XFER_ON 0x0
#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
#define nULTRA_XFER_ON 0x0
#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
/* Bit masks for ATAPI_DEV_ADDR */ /* Bit masks for ATAPI_DEV_ADDR */
@ -1345,66 +1210,39 @@
/* Bit masks for ATAPI_INT_MASK */ /* Bit masks for ATAPI_INT_MASK */
#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
#define nATAPI_DEV_INT_MASK 0x0
#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
#define nPIO_DONE_MASK 0x0
#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
#define nMULTI_DONE_MASK 0x0
#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
#define nUDMAIN_DONE_MASK 0x0
#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
#define nUDMAOUT_DONE_MASK 0x0
#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
#define nHOST_TERM_XFER_MASK 0x0
#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
#define nMULTI_TERM_MASK 0x0
#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
#define nUDMAIN_TERM_MASK 0x0
#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
#define nUDMAOUT_TERM_MASK 0x0
/* Bit masks for ATAPI_INT_STATUS */ /* Bit masks for ATAPI_INT_STATUS */
#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */
#define nATAPI_DEV_INT 0x0
#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
#define nPIO_DONE_INT 0x0
#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
#define nMULTI_DONE_INT 0x0
#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
#define nUDMAIN_DONE_INT 0x0
#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
#define nUDMAOUT_DONE_INT 0x0
#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
#define nHOST_TERM_XFER_INT 0x0
#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
#define nMULTI_TERM_INT 0x0
#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
#define nUDMAIN_TERM_INT 0x0
#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
#define nUDMAOUT_TERM_INT 0x0
/* Bit masks for ATAPI_LINE_STATUS */ /* Bit masks for ATAPI_LINE_STATUS */
#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */
#define nATAPI_INTR 0x0
#define ATAPI_DASP 0x2 /* Device dasp to host line status */ #define ATAPI_DASP 0x2 /* Device dasp to host line status */
#define nATAPI_DASP 0x0
#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
#define nATAPI_CS0N 0x0
#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
#define nATAPI_CS1N 0x0
#define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_ADDR 0x70 /* ATAPI address line status */
#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
#define nATAPI_DMAREQ 0x0
#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
#define nATAPI_DMAACKN 0x0
#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ #define ATAPI_DIOWN 0x200 /* ATAPI write line status */
#define nATAPI_DIOWN 0x0
#define ATAPI_DIORN 0x400 /* ATAPI read line status */ #define ATAPI_DIORN 0x400 /* ATAPI read line status */
#define nATAPI_DIORN 0x0
#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
#define nATAPI_IORDY 0x0
/* Bit masks for ATAPI_SM_STATE */ /* Bit masks for ATAPI_SM_STATE */
@ -1416,7 +1254,6 @@
/* Bit masks for ATAPI_TERMINATE */ /* Bit masks for ATAPI_TERMINATE */
#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */
#define nATAPI_HOST_TERM 0x0
/* Bit masks for ATAPI_REG_TIM_0 */ /* Bit masks for ATAPI_REG_TIM_0 */
@ -1471,41 +1308,26 @@
/* Bit masks for TIMER_ENABLE1 */ /* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */ #define TIMEN8 0x1 /* Timer 8 Enable */
#define nTIMEN8 0x0
#define TIMEN9 0x2 /* Timer 9 Enable */ #define TIMEN9 0x2 /* Timer 9 Enable */
#define nTIMEN9 0x0
#define TIMEN10 0x4 /* Timer 10 Enable */ #define TIMEN10 0x4 /* Timer 10 Enable */
#define nTIMEN10 0x0
/* Bit masks for TIMER_DISABLE1 */ /* Bit masks for TIMER_DISABLE1 */
#define TIMDIS8 0x1 /* Timer 8 Disable */ #define TIMDIS8 0x1 /* Timer 8 Disable */
#define nTIMDIS8 0x0
#define TIMDIS9 0x2 /* Timer 9 Disable */ #define TIMDIS9 0x2 /* Timer 9 Disable */
#define nTIMDIS9 0x0
#define TIMDIS10 0x4 /* Timer 10 Disable */ #define TIMDIS10 0x4 /* Timer 10 Disable */
#define nTIMDIS10 0x0
/* Bit masks for TIMER_STATUS1 */ /* Bit masks for TIMER_STATUS1 */
#define TIMIL8 0x1 /* Timer 8 Interrupt */ #define TIMIL8 0x1 /* Timer 8 Interrupt */
#define nTIMIL8 0x0
#define TIMIL9 0x2 /* Timer 9 Interrupt */ #define TIMIL9 0x2 /* Timer 9 Interrupt */
#define nTIMIL9 0x0
#define TIMIL10 0x4 /* Timer 10 Interrupt */ #define TIMIL10 0x4 /* Timer 10 Interrupt */
#define nTIMIL10 0x0
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
#define nTOVF_ERR8 0x0
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
#define nTOVF_ERR9 0x0
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
#define nTOVF_ERR10 0x0
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
#define nTRUN8 0x0
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
#define nTRUN9 0x0
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
#define nTRUN10 0x0
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
@ -1516,131 +1338,77 @@
/* Bit masks for USB_POWER */ /* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
#define nENABLE_SUSPENDM 0x0
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
#define nSUSPEND_MODE 0x0
#define RESUME_MODE 0x4 /* DMA Mode */ #define RESUME_MODE 0x4 /* DMA Mode */
#define nRESUME_MODE 0x0
#define RESET 0x8 /* Reset indicator */ #define RESET 0x8 /* Reset indicator */
#define nRESET 0x0
#define HS_MODE 0x10 /* High Speed mode indicator */ #define HS_MODE 0x10 /* High Speed mode indicator */
#define nHS_MODE 0x0
#define HS_ENABLE 0x20 /* high Speed Enable */ #define HS_ENABLE 0x20 /* high Speed Enable */
#define nHS_ENABLE 0x0
#define SOFT_CONN 0x40 /* Soft connect */ #define SOFT_CONN 0x40 /* Soft connect */
#define nSOFT_CONN 0x0
#define ISO_UPDATE 0x80 /* Isochronous update */ #define ISO_UPDATE 0x80 /* Isochronous update */
#define nISO_UPDATE 0x0
/* Bit masks for USB_INTRTX */ /* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
#define nEP0_TX 0x0
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
#define nEP1_TX 0x0
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
#define nEP2_TX 0x0
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
#define nEP3_TX 0x0
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
#define nEP4_TX 0x0
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
#define nEP5_TX 0x0
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
#define nEP6_TX 0x0
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
#define nEP7_TX 0x0
/* Bit masks for USB_INTRRX */ /* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
#define nEP1_RX 0x0
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
#define nEP2_RX 0x0
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
#define nEP3_RX 0x0
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
#define nEP4_RX 0x0
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
#define nEP5_RX 0x0
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
#define nEP6_RX 0x0
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
#define nEP7_RX 0x0
/* Bit masks for USB_INTRTXE */ /* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
#define nEP0_TX_E 0x0
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
#define nEP1_TX_E 0x0
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
#define nEP2_TX_E 0x0
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
#define nEP3_TX_E 0x0
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
#define nEP4_TX_E 0x0
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
#define nEP5_TX_E 0x0
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
#define nEP6_TX_E 0x0
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
#define nEP7_TX_E 0x0
/* Bit masks for USB_INTRRXE */ /* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
#define nEP1_RX_E 0x0
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
#define nEP2_RX_E 0x0
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
#define nEP3_RX_E 0x0
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
#define nEP4_RX_E 0x0
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
#define nEP5_RX_E 0x0
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
#define nEP6_RX_E 0x0
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
#define nEP7_RX_E 0x0
/* Bit masks for USB_INTRUSB */ /* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */ #define SUSPEND_B 0x1 /* Suspend indicator */
#define nSUSPEND_B 0x0
#define RESUME_B 0x2 /* Resume indicator */ #define RESUME_B 0x2 /* Resume indicator */
#define nRESUME_B 0x0
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
#define nRESET_OR_BABLE_B 0x0
#define SOF_B 0x8 /* Start of frame */ #define SOF_B 0x8 /* Start of frame */
#define nSOF_B 0x0
#define CONN_B 0x10 /* Connection indicator */ #define CONN_B 0x10 /* Connection indicator */
#define nCONN_B 0x0
#define DISCON_B 0x20 /* Disconnect indicator */ #define DISCON_B 0x20 /* Disconnect indicator */
#define nDISCON_B 0x0
#define SESSION_REQ_B 0x40 /* Session Request */ #define SESSION_REQ_B 0x40 /* Session Request */
#define nSESSION_REQ_B 0x0
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
#define nVBUS_ERROR_B 0x0
/* Bit masks for USB_INTRUSBE */ /* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */
#define nSUSPEND_BE 0x0
#define RESUME_BE 0x2 /* Resume indicator int enable */ #define RESUME_BE 0x2 /* Resume indicator int enable */
#define nRESUME_BE 0x0
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
#define nRESET_OR_BABLE_BE 0x0
#define SOF_BE 0x8 /* Start of frame int enable */ #define SOF_BE 0x8 /* Start of frame int enable */
#define nSOF_BE 0x0
#define CONN_BE 0x10 /* Connection indicator int enable */ #define CONN_BE 0x10 /* Connection indicator int enable */
#define nCONN_BE 0x0
#define DISCON_BE 0x20 /* Disconnect indicator int enable */ #define DISCON_BE 0x20 /* Disconnect indicator int enable */
#define nDISCON_BE 0x0
#define SESSION_REQ_BE 0x40 /* Session Request int enable */ #define SESSION_REQ_BE 0x40 /* Session Request int enable */
#define nSESSION_REQ_BE 0x0
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
#define nVBUS_ERROR_BE 0x0
/* Bit masks for USB_FRAME */ /* Bit masks for USB_FRAME */
@ -1653,117 +1421,67 @@
/* Bit masks for USB_GLOBAL_CTL */ /* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */ #define GLOBAL_ENA 0x1 /* enables USB module */
#define nGLOBAL_ENA 0x0
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
#define nEP1_TX_ENA 0x0
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
#define nEP2_TX_ENA 0x0
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
#define nEP3_TX_ENA 0x0
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
#define nEP4_TX_ENA 0x0
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
#define nEP5_TX_ENA 0x0
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
#define nEP6_TX_ENA 0x0
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
#define nEP7_TX_ENA 0x0
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
#define nEP1_RX_ENA 0x0
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
#define nEP2_RX_ENA 0x0
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
#define nEP3_RX_ENA 0x0
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
#define nEP4_RX_ENA 0x0
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
#define nEP5_RX_ENA 0x0
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
#define nEP6_RX_ENA 0x0
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
#define nEP7_RX_ENA 0x0
/* Bit masks for USB_OTG_DEV_CTL */ /* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */ #define SESSION 0x1 /* session indicator */
#define nSESSION 0x0
#define HOST_REQ 0x2 /* Host negotiation request */ #define HOST_REQ 0x2 /* Host negotiation request */
#define nHOST_REQ 0x0
#define HOST_MODE 0x4 /* indicates USBDRC is a host */ #define HOST_MODE 0x4 /* indicates USBDRC is a host */
#define nHOST_MODE 0x0
#define VBUS0 0x8 /* Vbus level indicator[0] */ #define VBUS0 0x8 /* Vbus level indicator[0] */
#define nVBUS0 0x0
#define VBUS1 0x10 /* Vbus level indicator[1] */ #define VBUS1 0x10 /* Vbus level indicator[1] */
#define nVBUS1 0x0
#define LSDEV 0x20 /* Low-speed indicator */ #define LSDEV 0x20 /* Low-speed indicator */
#define nLSDEV 0x0
#define FSDEV 0x40 /* Full or High-speed indicator */ #define FSDEV 0x40 /* Full or High-speed indicator */
#define nFSDEV 0x0
#define B_DEVICE 0x80 /* A' or 'B' device indicator */ #define B_DEVICE 0x80 /* A' or 'B' device indicator */
#define nB_DEVICE 0x0
/* Bit masks for USB_OTG_VBUS_IRQ */ /* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
#define nDRIVE_VBUS_ON 0x0
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
#define nDRIVE_VBUS_OFF 0x0
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
#define nCHRG_VBUS_START 0x0
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
#define nCHRG_VBUS_END 0x0
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
#define nDISCHRG_VBUS_START 0x0
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
#define nDISCHRG_VBUS_END 0x0
/* Bit masks for USB_OTG_VBUS_MASK */ /* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
#define nDRIVE_VBUS_ON_ENA 0x0
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
#define nDRIVE_VBUS_OFF_ENA 0x0
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
#define nCHRG_VBUS_START_ENA 0x0
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
#define nCHRG_VBUS_END_ENA 0x0
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
#define nDISCHRG_VBUS_START_ENA 0x0
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
#define nDISCHRG_VBUS_END_ENA 0x0
/* Bit masks for USB_CSR0 */ /* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */ #define RXPKTRDY 0x1 /* data packet receive indicator */
#define nRXPKTRDY 0x0
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ #define TXPKTRDY 0x2 /* data packet in FIFO indicator */
#define nTXPKTRDY 0x0
#define STALL_SENT 0x4 /* STALL handshake sent */ #define STALL_SENT 0x4 /* STALL handshake sent */
#define nSTALL_SENT 0x0
#define DATAEND 0x8 /* Data end indicator */ #define DATAEND 0x8 /* Data end indicator */
#define nDATAEND 0x0
#define SETUPEND 0x10 /* Setup end */ #define SETUPEND 0x10 /* Setup end */
#define nSETUPEND 0x0
#define SENDSTALL 0x20 /* Send STALL handshake */ #define SENDSTALL 0x20 /* Send STALL handshake */
#define nSENDSTALL 0x0
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
#define nSERVICED_RXPKTRDY 0x0
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
#define nSERVICED_SETUPEND 0x0
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ #define FLUSHFIFO 0x100 /* flush endpoint FIFO */
#define nFLUSHFIFO 0x0
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
#define nSTALL_RECEIVED_H 0x0
#define SETUPPKT_H 0x8 /* send Setup token host mode */ #define SETUPPKT_H 0x8 /* send Setup token host mode */
#define nSETUPPKT_H 0x0
#define ERROR_H 0x10 /* timeout error indicator host mode */ #define ERROR_H 0x10 /* timeout error indicator host mode */
#define nERROR_H 0x0
#define REQPKT_H 0x20 /* Request an IN transaction host mode */ #define REQPKT_H 0x20 /* Request an IN transaction host mode */
#define nREQPKT_H 0x0
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ #define STATUSPKT_H 0x40 /* Status stage transaction host mode */
#define nSTATUSPKT_H 0x0
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
#define nNAK_TIMEOUT_H 0x0
/* Bit masks for USB_COUNT0 */ /* Bit masks for USB_COUNT0 */
@ -1784,37 +1502,21 @@
/* Bit masks for USB_TXCSR */ /* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
#define nTXPKTRDY_T 0x0
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
#define nFIFO_NOT_EMPTY_T 0x0
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
#define nUNDERRUN_T 0x0
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
#define nFLUSHFIFO_T 0x0
#define STALL_SEND_T 0x10 /* issue a Stall handshake */ #define STALL_SEND_T 0x10 /* issue a Stall handshake */
#define nSTALL_SEND_T 0x0
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ #define STALL_SENT_T 0x20 /* Stall handshake transmitted */
#define nSTALL_SENT_T 0x0
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
#define nCLEAR_DATATOGGLE_T 0x0
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ #define INCOMPTX_T 0x80 /* indicates that a large packet is split */
#define nINCOMPTX_T 0x0
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
#define nDMAREQMODE_T 0x0
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
#define nFORCE_DATATOGGLE_T 0x0
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
#define nDMAREQ_ENA_T 0x0
#define ISO_T 0x4000 /* enable Isochronous transfers */ #define ISO_T 0x4000 /* enable Isochronous transfers */
#define nISO_T 0x0
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
#define nAUTOSET_T 0x0
#define ERROR_TH 0x4 /* error condition host mode */ #define ERROR_TH 0x4 /* error condition host mode */
#define nERROR_TH 0x0
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
#define nSTALL_RECEIVED_TH 0x0
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
#define nNAK_TIMEOUT_TH 0x0
/* Bit masks for USB_TXCOUNT */ /* Bit masks for USB_TXCOUNT */
@ -1823,45 +1525,25 @@
/* Bit masks for USB_RXCSR */ /* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
#define nRXPKTRDY_R 0x0
#define FIFO_FULL_R 0x2 /* FIFO not empty */ #define FIFO_FULL_R 0x2 /* FIFO not empty */
#define nFIFO_FULL_R 0x0
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
#define nOVERRUN_R 0x0
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
#define nDATAERROR_R 0x0
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
#define nFLUSHFIFO_R 0x0
#define STALL_SEND_R 0x20 /* issue a Stall handshake */ #define STALL_SEND_R 0x20 /* issue a Stall handshake */
#define nSTALL_SEND_R 0x0
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ #define STALL_SENT_R 0x40 /* Stall handshake transmitted */
#define nSTALL_SENT_R 0x0
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
#define nCLEAR_DATATOGGLE_R 0x0
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ #define INCOMPRX_R 0x100 /* indicates that a large packet is split */
#define nINCOMPRX_R 0x0
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
#define nDMAREQMODE_R 0x0
#define DISNYET_R 0x1000 /* disable Nyet handshakes */ #define DISNYET_R 0x1000 /* disable Nyet handshakes */
#define nDISNYET_R 0x0
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
#define nDMAREQ_ENA_R 0x0
#define ISO_R 0x4000 /* enable Isochronous transfers */ #define ISO_R 0x4000 /* enable Isochronous transfers */
#define nISO_R 0x0
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
#define nAUTOCLEAR_R 0x0
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
#define nERROR_RH 0x0
#define REQPKT_RH 0x20 /* request an IN transaction host mode */ #define REQPKT_RH 0x20 /* request an IN transaction host mode */
#define nREQPKT_RH 0x0
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
#define nSTALL_RECEIVED_RH 0x0
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
#define nINCOMPRX_RH 0x0
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
#define nDMAREQMODE_RH 0x0
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
#define nAUTOREQ_RH 0x0
/* Bit masks for USB_RXCOUNT */ /* Bit masks for USB_RXCOUNT */
@ -1888,35 +1570,22 @@
/* Bit masks for USB_DMA_INTERRUPT */ /* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */
#define nDMA0_INT 0x0
#define DMA1_INT 0x2 /* DMA1 pending interrupt */ #define DMA1_INT 0x2 /* DMA1 pending interrupt */
#define nDMA1_INT 0x0
#define DMA2_INT 0x4 /* DMA2 pending interrupt */ #define DMA2_INT 0x4 /* DMA2 pending interrupt */
#define nDMA2_INT 0x0
#define DMA3_INT 0x8 /* DMA3 pending interrupt */ #define DMA3_INT 0x8 /* DMA3 pending interrupt */
#define nDMA3_INT 0x0
#define DMA4_INT 0x10 /* DMA4 pending interrupt */ #define DMA4_INT 0x10 /* DMA4 pending interrupt */
#define nDMA4_INT 0x0
#define DMA5_INT 0x20 /* DMA5 pending interrupt */ #define DMA5_INT 0x20 /* DMA5 pending interrupt */
#define nDMA5_INT 0x0
#define DMA6_INT 0x40 /* DMA6 pending interrupt */ #define DMA6_INT 0x40 /* DMA6 pending interrupt */
#define nDMA6_INT 0x0
#define DMA7_INT 0x80 /* DMA7 pending interrupt */ #define DMA7_INT 0x80 /* DMA7 pending interrupt */
#define nDMA7_INT 0x0
/* Bit masks for USB_DMAxCONTROL */ /* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */ #define DMA_ENA 0x1 /* DMA enable */
#define nDMA_ENA 0x0
#define DIRECTION 0x2 /* direction of DMA transfer */ #define DIRECTION 0x2 /* direction of DMA transfer */
#define nDIRECTION 0x0
#define MODE 0x4 /* DMA Bus error */ #define MODE 0x4 /* DMA Bus error */
#define nMODE 0x0
#define INT_ENA 0x8 /* Interrupt enable */ #define INT_ENA 0x8 /* Interrupt enable */
#define nINT_ENA 0x0
#define EPNUM 0xf0 /* EP number */ #define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */ #define BUSERROR 0x100 /* DMA Bus error */
#define nBUSERROR 0x0
/* Bit masks for USB_DMAxADDRHIGH */ /* Bit masks for USB_DMAxADDRHIGH */
@ -1937,26 +1606,16 @@
/* Bit masks for HMDMAx_CONTROL */ /* Bit masks for HMDMAx_CONTROL */
#define HMDMAEN 0x1 /* Handshake MDMA Enable */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */
#define nHMDMAEN 0x0
#define REP 0x2 /* Handshake MDMA Request Polarity */ #define REP 0x2 /* Handshake MDMA Request Polarity */
#define nREP 0x0
#define UTE 0x8 /* Urgency Threshold Enable */ #define UTE 0x8 /* Urgency Threshold Enable */
#define nUTE 0x0
#define OIE 0x10 /* Overflow Interrupt Enable */ #define OIE 0x10 /* Overflow Interrupt Enable */
#define nOIE 0x0
#define BDIE 0x20 /* Block Done Interrupt Enable */ #define BDIE 0x20 /* Block Done Interrupt Enable */
#define nBDIE 0x0
#define MBDI 0x40 /* Mask Block Done Interrupt */ #define MBDI 0x40 /* Mask Block Done Interrupt */
#define nMBDI 0x0
#define DRQ 0x300 /* Handshake MDMA Request Type */ #define DRQ 0x300 /* Handshake MDMA Request Type */
#define RBC 0x1000 /* Force Reload of BCOUNT */ #define RBC 0x1000 /* Force Reload of BCOUNT */
#define nRBC 0x0
#define PS 0x2000 /* Pin Status */ #define PS 0x2000 /* Pin Status */
#define nPS 0x0
#define OI 0x4000 /* Overflow Interrupt Generated */ #define OI 0x4000 /* Overflow Interrupt Generated */
#define nOI 0x0
#define BDI 0x8000 /* Block Done Interrupt Generated */ #define BDI 0x8000 /* Block Done Interrupt Generated */
#define nBDI 0x0
/* ******************************************* */ /* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */ /* MULTI BIT MACRO ENUMERATIONS */

763
include/asm-blackfin/mach-bf548/defBF549.h
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1275
include/asm-blackfin/mach-bf548/defBF54x_base.h
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14
include/asm-blackfin/mach-bf548/dma.h
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@ -44,7 +44,6 @@
#define CH_UART1_TX 9 #define CH_UART1_TX 9
#define CH_ATAPI_RX 10 #define CH_ATAPI_RX 10
#define CH_ATAPI_TX 11 #define CH_ATAPI_TX 11
#define CH_EPPI0 12 #define CH_EPPI0 12
#define CH_EPPI1 13 #define CH_EPPI1 13
#define CH_EPPI2 14 #define CH_EPPI2 14
@ -58,6 +57,17 @@
#define CH_SDH 22 #define CH_SDH 22
#define CH_SPI2 23 #define CH_SPI2 23
#define MAX_BLACKFIN_DMA_CHANNEL CH_SPI2 #define CH_MEM_STREAM0_DEST 24
#define CH_MEM_STREAM0_SRC 25
#define CH_MEM_STREAM1_DEST 26
#define CH_MEM_STREAM1_SRC 27
#define CH_MEM_STREAM2_DEST 28
#define CH_MEM_STREAM2_SRC 29
#define CH_MEM_STREAM3_DEST 30
#define CH_MEM_STREAM3_SRC 31
#define MAX_BLACKFIN_DMA_CHANNEL 32
extern int channel2irq(unsigned int channel);
extern struct dma_register *base_addr[];
#endif #endif

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include/asm-blackfin/mach-bf548/gpio.h Normal file
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@ -0,0 +1,212 @@
/*
* File: include/asm-blackfin/mach-bf548/gpio.h
* Based on:
* Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
*
* Created:
* Description:
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define GPIO_PA0 0
#define GPIO_PA1 1
#define GPIO_PA2 2
#define GPIO_PA3 3
#define GPIO_PA4 4
#define GPIO_PA5 5
#define GPIO_PA6 6
#define GPIO_PA7 7
#define GPIO_PA8 8
#define GPIO_PA9 9
#define GPIO_PA10 10
#define GPIO_PA11 11
#define GPIO_PA12 12
#define GPIO_PA13 13
#define GPIO_PA14 14
#define GPIO_PA15 15
#define GPIO_PB0 16
#define GPIO_PB1 17
#define GPIO_PB2 18
#define GPIO_PB3 19
#define GPIO_PB4 20
#define GPIO_PB5 21
#define GPIO_PB6 22
#define GPIO_PB7 23
#define GPIO_PB8 24
#define GPIO_PB9 25
#define GPIO_PB10 26
#define GPIO_PB11 27
#define GPIO_PB12 28
#define GPIO_PB13 29
#define GPIO_PB14 30
#define GPIO_PB15 31 /* N/A */
#define GPIO_PC0 32
#define GPIO_PC1 33
#define GPIO_PC2 34
#define GPIO_PC3 35
#define GPIO_PC4 36
#define GPIO_PC5 37
#define GPIO_PC6 38
#define GPIO_PC7 39
#define GPIO_PC8 40
#define GPIO_PC9 41
#define GPIO_PC10 42
#define GPIO_PC11 43
#define GPIO_PC12 44
#define GPIO_PC13 45
#define GPIO_PC14 46 /* N/A */
#define GPIO_PC15 47 /* N/A */
#define GPIO_PD0 48
#define GPIO_PD1 49
#define GPIO_PD2 50
#define GPIO_PD3 51
#define GPIO_PD4 52
#define GPIO_PD5 53
#define GPIO_PD6 54
#define GPIO_PD7 55
#define GPIO_PD8 56
#define GPIO_PD9 57
#define GPIO_PD10 58
#define GPIO_PD11 59
#define GPIO_PD12 60
#define GPIO_PD13 61
#define GPIO_PD14 62
#define GPIO_PD15 63
#define GPIO_PE0 64
#define GPIO_PE1 65
#define GPIO_PE2 66
#define GPIO_PE3 67
#define GPIO_PE4 68
#define GPIO_PE5 69
#define GPIO_PE6 70
#define GPIO_PE7 71
#define GPIO_PE8 72
#define GPIO_PE9 73
#define GPIO_PE10 74
#define GPIO_PE11 75
#define GPIO_PE12 76
#define GPIO_PE13 77
#define GPIO_PE14 78
#define GPIO_PE15 79
#define GPIO_PF0 80
#define GPIO_PF1 81
#define GPIO_PF2 82
#define GPIO_PF3 83
#define GPIO_PF4 84
#define GPIO_PF5 85
#define GPIO_PF6 86
#define GPIO_PF7 87
#define GPIO_PF8 88
#define GPIO_PF9 89
#define GPIO_PF10 90
#define GPIO_PF11 91
#define GPIO_PF12 92
#define GPIO_PF13 93
#define GPIO_PF14 94
#define GPIO_PF15 95
#define GPIO_PG0 96
#define GPIO_PG1 97
#define GPIO_PG2 98
#define GPIO_PG3 99
#define GPIO_PG4 100
#define GPIO_PG5 101
#define GPIO_PG6 102
#define GPIO_PG7 103
#define GPIO_PG8 104
#define GPIO_PG9 105
#define GPIO_PG10 106
#define GPIO_PG11 107
#define GPIO_PG12 108
#define GPIO_PG13 109
#define GPIO_PG14 110
#define GPIO_PG15 111
#define GPIO_PH0 112
#define GPIO_PH1 113
#define GPIO_PH2 114
#define GPIO_PH3 115
#define GPIO_PH4 116
#define GPIO_PH5 117
#define GPIO_PH6 118
#define GPIO_PH7 119
#define GPIO_PH8 120
#define GPIO_PH9 121
#define GPIO_PH10 122
#define GPIO_PH11 123
#define GPIO_PH12 124
#define GPIO_PH13 125
#define GPIO_PH14 126 /* N/A */
#define GPIO_PH15 127 /* N/A */
#define GPIO_PI0 128
#define GPIO_PI1 129
#define GPIO_PI2 130
#define GPIO_PI3 131
#define GPIO_PI4 132
#define GPIO_PI5 133
#define GPIO_PI6 134
#define GPIO_PI7 135
#define GPIO_PI8 136
#define GPIO_PI9 137
#define GPIO_PI10 138
#define GPIO_PI11 139
#define GPIO_PI12 140
#define GPIO_PI13 141
#define GPIO_PI14 142
#define GPIO_PI15 143
#define GPIO_PJ0 144
#define GPIO_PJ1 145
#define GPIO_PJ2 146
#define GPIO_PJ3 147
#define GPIO_PJ4 148
#define GPIO_PJ5 149
#define GPIO_PJ6 150
#define GPIO_PJ7 151
#define GPIO_PJ8 152
#define GPIO_PJ9 153
#define GPIO_PJ10 154
#define GPIO_PJ11 155
#define GPIO_PJ12 156
#define GPIO_PJ13 157
#define GPIO_PJ14 158
#define GPIO_PJ15 159
#define MAX_BLACKFIN_GPIOS 160
struct gpio_port_t {
unsigned short port_fer;
unsigned short dummy1;
unsigned short port_data;
unsigned short dummy2;
unsigned short port_set;
unsigned short dummy3;
unsigned short port_clear;
unsigned short dummy4;
unsigned short port_dir_set;
unsigned short dummy5;
unsigned short port_dir_clear;
unsigned short dummy6;
unsigned short port_inen;
unsigned short dummy7;
unsigned int port_mux;
};

164
include/asm-blackfin/mach-bf548/irq.h
View File

@ -51,7 +51,7 @@ Events (highest priority) EMU 0
(lowest priority) IVG15 32 * (lowest priority) IVG15 32 *
*/ */
#define NR_PERI_INTS 32 #define NR_PERI_INTS (32 * 3)
/* The ABSTRACT IRQ definitions */ /* The ABSTRACT IRQ definitions */
/** the first seven of the following are fixed, the rest you change if you need to **/ /** the first seven of the following are fixed, the rest you change if you need to **/
@ -92,7 +92,7 @@ Events (highest priority) EMU 0
#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ #define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ #define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ #define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
#define IRQ_MXVR BFIN_IRQ(27) /* SPORT3 Error Interrupt */ #define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ #define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ #define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ #define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
@ -102,8 +102,8 @@ Events (highest priority) EMU 0
#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
#define IRQ_EPP1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
#define IRQ_EPP2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ #define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ #define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
@ -143,14 +143,14 @@ Events (highest priority) EMU 0
#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ #define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ #define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ #define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
#define IRQ_TMR0 BFIN_IRQ(86) /* Timer 0 Interrupt */ #define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
#define IRQ_TMR1 BFIN_IRQ(87) /* Timer 1 Interrupt */ #define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
#define IRQ_TMR2 BFIN_IRQ(88) /* Timer 2 Interrupt */ #define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
#define IRQ_TMR3 BFIN_IRQ(89) /* Timer 3 Interrupt */ #define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
#define IRQ_TMR4 BFIN_IRQ(90) /* Timer 4 Interrupt */ #define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
#define IRQ_TMR5 BFIN_IRQ(91) /* Timer 5 Interrupt */ #define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
#define IRQ_TMR6 BFIN_IRQ(92) /* Timer 6 Interrupt */ #define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
#define IRQ_TMR7 BFIN_IRQ(93) /* Timer 7 Interrupt */ #define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
@ -248,9 +248,9 @@ Events (highest priority) EMU 0
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PH15+1) #define NR_IRQS (IRQ_PE15+1)
#else #else
#define NR_IRQS (IRQ_UART1_ERROR+1) #define NR_IRQS (SYS_IRQS+1)
#endif #endif
#define IVG7 7 #define IVG7 7
@ -265,42 +265,114 @@ Events (highest priority) EMU 0
/* IAR0 BIT FIELDS */ /* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0 #define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMA_ERROR_POS 4 #define IRQ_DMAC0_ERR_POS 4
#define IRQ_ERROR_POS 8 #define IRQ_EPPI0_ERR_POS 8
#define IRQ_RTC_POS 12 #define IRQ_SPORT0_ERR_POS 12
#define IRQ_PPI_POS 16 #define IRQ_SPORT1_ERR_POS 16
#define IRQ_SPORT0_RX_POS 20 #define IRQ_SPI0_ERR_POS 20
#define IRQ_SPORT0_TX_POS 24 #define IRQ_UART0_ERR_POS 24
#define IRQ_SPORT1_RX_POS 28 #define IRQ_RTC_POS 28
/* IAR1 BIT FIELDS */ /* IAR1 BIT FIELDS */
#define IRQ_SPORT1_TX_POS 0 #define IRQ_EPPI0_POS 0
#define IRQ_TWI_POS 4 #define IRQ_SPORT0_RX_POS 4
#define IRQ_SPI_POS 8 #define IRQ_SPORT0_TX_POS 8
#define IRQ_UART0_RX_POS 12 #define IRQ_SPORT1_RX_POS 12
#define IRQ_UART0_TX_POS 16 #define IRQ_SPORT1_TX_POS 16
#define IRQ_UART1_RX_POS 20 #define IRQ_SPI0_POS 20
#define IRQ_UART1_TX_POS 24 #define IRQ_UART0_RX_POS 24
#define IRQ_CAN_RX_POS 28 #define IRQ_UART0_TX_POS 28
/* IAR2 BIT FIELDS */ /* IAR2 BIT FIELDS */
#define IRQ_CAN_TX_POS 0 #define IRQ_TIMER8_POS 0
#define IRQ_MAC_RX_POS 4 #define IRQ_TIMER9_POS 4
#define IRQ_MAC_TX_POS 8 #define IRQ_TIMER10_POS 8
#define IRQ_TMR0_POS 12 #define IRQ_PINT0_POS 12
#define IRQ_TMR1_POS 16 #define IRQ_PINT1_POS 16
#define IRQ_TMR2_POS 20 #define IRQ_MDMAS0_POS 20
#define IRQ_TMR3_POS 24 #define IRQ_MDMAS1_POS 24
#define IRQ_TMR4_POS 28 #define IRQ_WATCHDOG_POS 28
/* IAR3 BIT FIELDS */ /* IAR3 BIT FIELDS */
#define IRQ_TMR5_POS 0 #define IRQ_DMAC1_ERR_POS 0
#define IRQ_TMR6_POS 4 #define IRQ_SPORT2_ERR_POS 4
#define IRQ_TMR7_POS 8 #define IRQ_SPORT3_ERR_POS 8
#define IRQ_PROG_INTA_POS 12 #define IRQ_MXVR_DATA_POS 12
#define IRQ_PORTG_INTB_POS 16 #define IRQ_SPI1_ERR_POS 16
#define IRQ_MEM_DMA0_POS 20 #define IRQ_SPI2_ERR_POS 20
#define IRQ_MEM_DMA1_POS 24 #define IRQ_UART1_ERR_POS 24
#define IRQ_WATCH_POS 28 #define IRQ_UART2_ERR_POS 28
#endif /* _BF537_IRQ_H_ */ /* IAR4 BIT FILEDS */
#define IRQ_CAN0_ERR_POS 0
#define IRQ_SPORT2_RX_POS 4
#define IRQ_SPORT2_TX_POS 8
#define IRQ_SPORT3_RX_POS 12
#define IRQ_SPORT3_TX_POS 16
#define IRQ_EPPI1_POS 20
#define IRQ_EPPI2_POS 24
#define IRQ_SPI1_POS 28
/* IAR5 BIT FIELDS */
#define IRQ_SPI2_POS 0
#define IRQ_UART1_RX_POS 4
#define IRQ_UART1_TX_POS 8
#define IRQ_ATAPI_RX_POS 12
#define IRQ_ATAPI_TX_POS 16
#define IRQ_TWI0_POS 20
#define IRQ_TWI1_POS 24
#define IRQ_CAN0_RX_POS 28
/* IAR6 BIT FIELDS */
#define IRQ_CAN0_TX_POS 0
#define IRQ_MDMAS2_POS 4
#define IRQ_MDMAS3_POS 8
#define IRQ_MXVR_ERR_POS 12
#define IRQ_MXVR_MSG_POS 16
#define IRQ_MXVR_PKT_POS 20
#define IRQ_EPPI1_ERR_POS 24
#define IRQ_EPPI2_ERR_POS 28
/* IAR7 BIT FIELDS */
#define IRQ_UART3_ERR_POS 0
#define IRQ_HOST_ERR_POS 4
#define IRQ_PIXC_ERR_POS 12
#define IRQ_NFC_ERR_POS 16
#define IRQ_ATAPI_ERR_POS 20
#define IRQ_CAN1_ERR_POS 24
#define IRQ_HS_DMA_ERR_POS 28
/* IAR8 BIT FIELDS */
#define IRQ_PIXC_IN0_POS 0
#define IRQ_PIXC_IN1_POS 4
#define IRQ_PIXC_OUT_POS 8
#define IRQ_SDH_POS 12
#define IRQ_CNT_POS 16
#define IRQ_KEY_POS 20
#define IRQ_CAN1_RX_POS 24
#define IRQ_CAN1_TX_POS 28
/* IAR9 BIT FIELDS */
#define IRQ_SDH_MASK0_POS 0
#define IRQ_SDH_MASK1_POS 4
#define IRQ_USB_INT0_POS 12
#define IRQ_USB_INT1_POS 16
#define IRQ_USB_INT2_POS 20
#define IRQ_USB_DMA_POS 24
#define IRQ_OTPSEC_POS 28
/* IAR10 BIT FIELDS */
#define IRQ_TIMER0_POS 24
#define IRQ_TIMER1_POS 28
/* IAR11 BIT FIELDS */
#define IRQ_TIMER2_POS 0
#define IRQ_TIMER3_POS 4
#define IRQ_TIMER4_POS 8
#define IRQ_TIMER5_POS 12
#define IRQ_TIMER6_POS 16
#define IRQ_TIMER7_POS 20
#define IRQ_PINT2_POS 24
#define IRQ_PINT3_POS 28
#endif /* _BF548_IRQ_H_ */

3
include/asm-blackfin/mach-bf561/dma.h
View File

@ -32,4 +32,7 @@
#define CH_IMEM_STREAM1_SRC 34 #define CH_IMEM_STREAM1_SRC 34
#define CH_IMEM_STREAM1_DEST 35 #define CH_IMEM_STREAM1_DEST 35
extern int channel2irq(unsigned int channel);
extern struct dma_register *base_addr[];
#endif #endif