i2c: rk3x: handle dynamic clock rate changes correctly
The i2c input clock can change dynamically, e.g. on the RK3066 where pclk_i2c0 and pclk_i2c1 are connected to the armclk, which changes rate on cpu frequency scaling. Until now, we incorrectly called clk_get_rate() while holding the i2c->lock in rk3x_i2c_xfer() to adapt to clock rate changes. Thanks to Huang Tao for reporting this issue. Do it properly now using the clk notifier framework. The callback logic was taken from i2c-cadence.c. Also rename all misleading "i2c_rate" variables to "clk_rate", as they describe the *input* clk rate. Signed-off-by: Max Schwarz <max.schwarz@online.de> Tested-by: Doug Anderson <dianders@chromium.org> on RK3288 Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Max Schwarz
Wolfram Sang
parent
727f9c2dad
commit
249051f499
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@ -98,6 +98,7 @@ struct rk3x_i2c {
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/* Hardware resources */
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void __iomem *regs;
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struct clk *clk;
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struct notifier_block clk_rate_nb;
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/* Settings */
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unsigned int scl_frequency;
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@ -429,15 +430,27 @@ out:
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return IRQ_HANDLED;
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}
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static int rk3x_i2c_calc_divs(unsigned long i2c_rate, unsigned long scl_rate,
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unsigned long *div_low, unsigned long *div_high)
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/**
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* Calculate divider values for desired SCL frequency
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*
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* @clk_rate: I2C input clock rate
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* @scl_rate: Desired SCL rate
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* @div_low: Divider output for low
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* @div_high: Divider output for high
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*
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* Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
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* a best-effort divider value is returned in divs. If the target rate is
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* too high, we silently use the highest possible rate.
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*/
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static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate,
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unsigned long *div_low, unsigned long *div_high)
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{
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unsigned long min_low_ns, min_high_ns;
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unsigned long max_data_hold_ns;
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unsigned long data_hold_buffer_ns;
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unsigned long max_low_ns, min_total_ns;
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unsigned long i2c_rate_khz, scl_rate_khz;
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unsigned long clk_rate_khz, scl_rate_khz;
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unsigned long min_low_div, min_high_div;
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unsigned long max_low_div;
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@ -445,6 +458,8 @@ static int rk3x_i2c_calc_divs(unsigned long i2c_rate, unsigned long scl_rate,
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unsigned long min_div_for_hold, min_total_div;
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unsigned long extra_div, extra_low_div, ideal_low_div;
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int ret = 0;
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/* Only support standard-mode and fast-mode */
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if (WARN_ON(scl_rate > 400000))
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scl_rate = 400000;
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@ -480,25 +495,25 @@ static int rk3x_i2c_calc_divs(unsigned long i2c_rate, unsigned long scl_rate,
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min_total_ns = min_low_ns + min_high_ns;
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/* Adjust to avoid overflow */
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i2c_rate_khz = DIV_ROUND_UP(i2c_rate, 1000);
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clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
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scl_rate_khz = scl_rate / 1000;
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/*
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* We need the total div to be >= this number
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* so we don't clock too fast.
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*/
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min_total_div = DIV_ROUND_UP(i2c_rate_khz, scl_rate_khz * 8);
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min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
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/* These are the min dividers needed for min hold times. */
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min_low_div = DIV_ROUND_UP(i2c_rate_khz * min_low_ns, 8 * 1000000);
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min_high_div = DIV_ROUND_UP(i2c_rate_khz * min_high_ns, 8 * 1000000);
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min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
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min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
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min_div_for_hold = (min_low_div + min_high_div);
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/*
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* This is the maximum divider so we don't go over the max.
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* We don't round up here (we round down) since this is a max.
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*/
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max_low_div = i2c_rate_khz * max_low_ns / (8 * 1000000);
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max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
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if (min_low_div > max_low_div) {
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WARN_ONCE(true,
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@ -526,7 +541,7 @@ static int rk3x_i2c_calc_divs(unsigned long i2c_rate, unsigned long scl_rate,
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* biasing slightly towards having a higher div
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* for low (spend more time low).
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*/
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ideal_low_div = DIV_ROUND_UP(i2c_rate_khz * min_low_ns,
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ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
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scl_rate_khz * 8 * min_total_ns);
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/* Don't allow it to go over the max */
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@ -547,42 +562,101 @@ static int rk3x_i2c_calc_divs(unsigned long i2c_rate, unsigned long scl_rate,
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}
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/*
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* Adjust to the fact that the hardware has an implicit "+1".
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* NOTE: Above calculations always produce div_low > 0 and div_high > 0.
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*/
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* Adjust to the fact that the hardware has an implicit "+1".
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* NOTE: Above calculations always produce div_low > 0 and div_high > 0.
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*/
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*div_low = *div_low - 1;
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*div_high = *div_high - 1;
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if (*div_low >= 0xffff || *div_high >= 0xffff)
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return -EINVAL;
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else
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return 0;
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}
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/* Maximum divider supported by hw is 0xffff */
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if (*div_low > 0xffff) {
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*div_low = 0xffff;
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ret = -EINVAL;
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}
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static int rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
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{
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unsigned long i2c_rate = clk_get_rate(i2c->clk);
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unsigned long div_low, div_high;
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u64 t_low_ns, t_high_ns;
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int ret = 0;
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ret = rk3x_i2c_calc_divs(i2c_rate, scl_rate, &div_low, &div_high);
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if (ret < 0)
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return ret;
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i2c_writel(i2c, (div_high << 16) | (div_low & 0xffff), REG_CLKDIV);
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t_low_ns = div_u64(((u64)div_low + 1) * 8 * 1000000000, i2c_rate);
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t_high_ns = div_u64(((u64)div_high + 1) * 8 * 1000000000, i2c_rate);
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dev_dbg(i2c->dev,
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"CLK %lukhz, Req %luns, Act low %lluns high %lluns\n",
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i2c_rate / 1000,
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1000000000 / scl_rate,
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t_low_ns, t_high_ns);
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if (*div_high > 0xffff) {
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*div_high = 0xffff;
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ret = -EINVAL;
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}
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return ret;
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}
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static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
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{
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unsigned long div_low, div_high;
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u64 t_low_ns, t_high_ns;
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int ret;
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ret = rk3x_i2c_calc_divs(clk_rate, i2c->scl_frequency, &div_low,
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&div_high);
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WARN_ONCE(ret != 0, "Could not reach SCL freq %u", i2c->scl_frequency);
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clk_enable(i2c->clk);
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i2c_writel(i2c, (div_high << 16) | (div_low & 0xffff), REG_CLKDIV);
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clk_disable(i2c->clk);
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t_low_ns = div_u64(((u64)div_low + 1) * 8 * 1000000000, clk_rate);
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t_high_ns = div_u64(((u64)div_high + 1) * 8 * 1000000000, clk_rate);
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dev_dbg(i2c->dev,
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"CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
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clk_rate / 1000,
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1000000000 / i2c->scl_frequency,
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t_low_ns, t_high_ns);
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}
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/**
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* rk3x_i2c_clk_notifier_cb - Clock rate change callback
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* @nb: Pointer to notifier block
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* @event: Notification reason
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* @data: Pointer to notification data object
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*
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* The callback checks whether a valid bus frequency can be generated after the
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* change. If so, the change is acknowledged, otherwise the change is aborted.
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* New dividers are written to the HW in the pre- or post change notification
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* depending on the scaling direction.
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*
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* Code adapted from i2c-cadence.c.
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*
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* Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
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* to acknowedge the change, NOTIFY_DONE if the notification is
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* considered irrelevant.
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*/
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static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
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event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
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unsigned long div_low, div_high;
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switch (event) {
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case PRE_RATE_CHANGE:
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if (rk3x_i2c_calc_divs(ndata->new_rate, i2c->scl_frequency,
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&div_low, &div_high) != 0) {
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return NOTIFY_STOP;
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}
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/* scale up */
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if (ndata->new_rate > ndata->old_rate)
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rk3x_i2c_adapt_div(i2c, ndata->new_rate);
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return NOTIFY_OK;
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case POST_RATE_CHANGE:
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/* scale down */
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if (ndata->new_rate < ndata->old_rate)
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rk3x_i2c_adapt_div(i2c, ndata->new_rate);
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return NOTIFY_OK;
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case ABORT_RATE_CHANGE:
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/* scale up */
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if (ndata->new_rate > ndata->old_rate)
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rk3x_i2c_adapt_div(i2c, ndata->old_rate);
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return NOTIFY_OK;
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default:
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return NOTIFY_DONE;
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}
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}
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/**
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* Setup I2C registers for an I2C operation specified by msgs, num.
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*
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@ -677,11 +751,6 @@ static int rk3x_i2c_xfer(struct i2c_adapter *adap,
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clk_enable(i2c->clk);
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/* The clock rate might have changed, so setup the divider again */
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ret = rk3x_i2c_set_scl_rate(i2c, i2c->scl_frequency);
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if (ret < 0)
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goto exit;
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i2c->is_last_msg = false;
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/*
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@ -728,7 +797,6 @@ static int rk3x_i2c_xfer(struct i2c_adapter *adap,
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}
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}
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exit:
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clk_disable(i2c->clk);
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spin_unlock_irqrestore(&i2c->lock, flags);
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@ -768,6 +836,7 @@ static int rk3x_i2c_probe(struct platform_device *pdev)
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int bus_nr;
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u32 value;
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int irq;
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unsigned long clk_rate;
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i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
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if (!i2c)
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@ -868,16 +937,28 @@ static int rk3x_i2c_probe(struct platform_device *pdev)
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return ret;
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}
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i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
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ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
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if (ret != 0) {
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dev_err(&pdev->dev, "Unable to register clock notifier\n");
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goto err_clk;
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}
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clk_rate = clk_get_rate(i2c->clk);
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rk3x_i2c_adapt_div(i2c, clk_rate);
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ret = i2c_add_adapter(&i2c->adap);
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if (ret < 0) {
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dev_err(&pdev->dev, "Could not register adapter\n");
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goto err_clk;
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goto err_clk_notifier;
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}
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dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs);
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return 0;
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err_clk_notifier:
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clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
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err_clk:
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clk_unprepare(i2c->clk);
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return ret;
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@ -888,6 +969,8 @@ static int rk3x_i2c_remove(struct platform_device *pdev)
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struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
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i2c_del_adapter(&i2c->adap);
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clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
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clk_unprepare(i2c->clk);
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return 0;
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