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[ARM] 3366/1: Allow the 16bpp mode configuration in the CLCD control register 

Patch from Catalin Marinas

Starting with PL111, the 5551 or 565 modes can be configured in the
primecell's control register directly. This patch detects the required mode
and sets the correct value.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas 2006-03-16 14:10:19 +00:00 committed by Russell King
parent 5466eb5d0a
commit 243f196d57
1 changed files with 11 additions and 1 deletions
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12
include/linux/amba/clcd.h
View File

@ -54,6 +54,7 @@
#define CNTL_LCDBPP4 (2 << 1)
#define CNTL_LCDBPP8 (3 << 1)
#define CNTL_LCDBPP16 (4 << 1)
#define CNTL_LCDBPP16_565 (6 << 1)
#define CNTL_LCDBPP24 (5 << 1)
#define CNTL_LCDBW (1 << 4)
#define CNTL_LCDTFT (1 << 5)
@ -209,7 +210,16 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
val |= CNTL_LCDBPP8;
break;
case 16:
val |= CNTL_LCDBPP16;
/*
* PL110 cannot choose between 5551 and 565 modes in
* its control register
*/
if ((fb->dev->periphid & 0x000fffff) == 0x00041110)
val |= CNTL_LCDBPP16;
else if (fb->fb.var.green.length == 5)
val |= CNTL_LCDBPP16;
else
val |= CNTL_LCDBPP16_565;
break;
case 32:
val |= CNTL_LCDBPP24;