drm/i915: Fix scanline counter fixup on BDW
The display interrupts changed on BDW, so the current ILK-HSW specific code in ilk_pipe_in_vblank_locked() doesn't work there. Add the required bits for BDW, and while at it, change the existing code to use nicer looking vblank status bit macros. Also remove the now stale __raw_i915_read16() definition which was left over from the failed gen2 ISR experiment. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73962 Tested-by: Lu Hua <huax.lu@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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@ -618,33 +618,25 @@ static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
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/* raw reads, only for fast reads of display block, no need for forcewake etc. */
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#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
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#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
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static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t status;
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int reg;
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if (INTEL_INFO(dev)->gen < 7) {
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status = pipe == PIPE_A ?
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DE_PIPEA_VBLANK :
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DE_PIPEB_VBLANK;
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if (INTEL_INFO(dev)->gen >= 8) {
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status = GEN8_PIPE_VBLANK;
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reg = GEN8_DE_PIPE_ISR(pipe);
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} else if (INTEL_INFO(dev)->gen >= 7) {
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status = DE_PIPE_VBLANK_IVB(pipe);
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reg = DEISR;
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} else {
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switch (pipe) {
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default:
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case PIPE_A:
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status = DE_PIPEA_VBLANK_IVB;
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break;
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case PIPE_B:
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status = DE_PIPEB_VBLANK_IVB;
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break;
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case PIPE_C:
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status = DE_PIPEC_VBLANK_IVB;
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break;
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}
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status = DE_PIPE_VBLANK(pipe);
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reg = DEISR;
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}
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return __raw_i915_read32(dev_priv, DEISR) & status;
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return __raw_i915_read32(dev_priv, reg) & status;
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}
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static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
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