cxgb4: Add macros, structures and inline functions for T5
Signed-off-by: Santosh Rastapur <santosh@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Santosh Rastapur
David S. Miller
parent
b2decadd83
commit
2422d9a327
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@ -54,6 +54,10 @@
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#define FW_VERSION_MINOR 1
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#define FW_VERSION_MICRO 0
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#define FW_VERSION_MAJOR_T5 0
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#define FW_VERSION_MINOR_T5 0
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#define FW_VERSION_MICRO_T5 0
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#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
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enum {
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@ -66,7 +70,9 @@ enum {
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enum {
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MEM_EDC0,
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MEM_EDC1,
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MEM_MC
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MEM_MC,
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MEM_MC0 = MEM_MC,
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MEM_MC1
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};
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enum {
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@ -74,8 +80,10 @@ enum {
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MEMWIN0_BASE = 0x1b800,
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MEMWIN1_APERTURE = 32768,
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MEMWIN1_BASE = 0x28000,
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MEMWIN1_BASE_T5 = 0x52000,
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MEMWIN2_APERTURE = 65536,
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MEMWIN2_BASE = 0x30000,
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MEMWIN2_BASE_T5 = 0x54000,
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};
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enum dev_master {
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@ -504,6 +512,35 @@ struct sge {
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struct l2t_data;
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#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
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#define CHELSIO_CHIP_VERSION(code) ((code) >> 4)
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#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
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#define CHELSIO_T4 0x4
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#define CHELSIO_T5 0x5
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enum chip_type {
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T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 0),
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T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
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T4_A3 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
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T4_FIRST_REV = T4_A1,
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T4_LAST_REV = T4_A3,
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T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
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T5_FIRST_REV = T5_A1,
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T5_LAST_REV = T5_A1,
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};
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#ifdef CONFIG_PCI_IOV
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/* T4 - 4 PFs support SRIOV
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* T5 - 8 PFs support SRIOV
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*/
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#define NUM_OF_PF_WITH_SRIOV_T4 4
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#define NUM_OF_PF_WITH_SRIOV_T5 8
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#endif
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struct adapter {
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void __iomem *regs;
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struct pci_dev *pdev;
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@ -511,6 +548,7 @@ struct adapter {
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unsigned int mbox;
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unsigned int fn;
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unsigned int flags;
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enum chip_type chip;
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int msg_enable;
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@ -673,6 +711,16 @@ enum {
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VLAN_REWRITE
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};
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static inline int is_t5(enum chip_type chip)
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{
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return (chip >= T5_FIRST_REV && chip <= T5_LAST_REV);
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}
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static inline int is_t4(enum chip_type chip)
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{
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return (chip >= T4_FIRST_REV && chip <= T4_LAST_REV);
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}
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static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
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{
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return readl(adap->regs + reg_addr);
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@ -74,6 +74,7 @@ enum {
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CPL_PASS_ESTABLISH = 0x41,
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CPL_RX_DATA_DDP = 0x42,
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CPL_PASS_ACCEPT_REQ = 0x44,
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CPL_TRACE_PKT_T5 = 0x48,
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CPL_RDMA_READ_REQ = 0x60,
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@ -287,6 +288,23 @@ struct cpl_act_open_req {
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__be32 opt2;
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};
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#define S_FILTER_TUPLE 24
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#define M_FILTER_TUPLE 0xFFFFFFFFFF
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#define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
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#define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
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struct cpl_t5_act_open_req {
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WR_HDR;
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union opcode_tid ot;
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__be16 local_port;
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__be16 peer_port;
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__be32 local_ip;
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__be32 peer_ip;
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__be64 opt0;
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__be32 rsvd;
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__be32 opt2;
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__be64 params;
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};
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struct cpl_act_open_req6 {
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WR_HDR;
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union opcode_tid ot;
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@ -566,6 +584,11 @@ struct cpl_rx_pkt {
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#define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
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#define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
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#define S_RX_T5_ETHHDR_LEN 0
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#define M_RX_T5_ETHHDR_LEN 0x3F
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#define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
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#define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
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#define S_RX_MACIDX 8
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#define M_RX_MACIDX 0x1FF
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#define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
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@ -612,6 +635,28 @@ struct cpl_trace_pkt {
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__be64 tstamp;
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};
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struct cpl_t5_trace_pkt {
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__u8 opcode;
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__u8 intf;
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#if defined(__LITTLE_ENDIAN_BITFIELD)
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__u8 runt:4;
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__u8 filter_hit:4;
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__u8:6;
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__u8 err:1;
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__u8 trunc:1;
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#else
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__u8 filter_hit:4;
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__u8 runt:4;
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__u8 trunc:1;
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__u8 err:1;
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__u8:6;
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#endif
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__be16 rsvd;
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__be16 len;
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__be64 tstamp;
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__be64 rsvd1;
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};
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struct cpl_l2t_write_req {
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WR_HDR;
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union opcode_tid ot;
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@ -574,7 +574,7 @@ struct fw_eth_tx_pkt_vm_wr {
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__be16 vlantci;
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};
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#define FW_CMD_MAX_TIMEOUT 3000
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#define FW_CMD_MAX_TIMEOUT 10000
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/*
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* If a host driver does a HELLO and discovers that there's already a MASTER
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