OMAPDSS: Add interlace parameter to omap_video_timings
Add a parameter called interlace which tells whether the timings are in interlaced or progressive mode. This aligns the omap_video_timings struct with the Xorg modeline configuration. It also removes the hack needed to write to divide the manager height by 2 if the connected interface is VENC. Signed-off-by: Archit Taneja <archit@ti.com>
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@ -2754,11 +2754,7 @@ void dispc_mgr_set_timings(enum omap_channel channel,
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DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
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} else {
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enum dss_hdmi_venc_clk_source_select source;
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source = dss_get_hdmi_venc_clk_source();
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if (source == DSS_VENC_TV_CLK)
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if (t.interlace == true)
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t.y_res /= 2;
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}
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@ -46,6 +46,7 @@ static int hdmi_panel_probe(struct omap_dss_device *dssdev)
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dssdev->panel.timings = (struct omap_video_timings)
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{ 640, 480, 25175, 96, 16, 48, 2, 11, 31,
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OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
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false,
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};
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DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n",
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@ -272,6 +272,8 @@ const struct omap_video_timings omap_dss_pal_timings = {
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.vsw = 5,
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.vfp = 5,
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.vbp = 41,
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.interlace = true,
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};
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EXPORT_SYMBOL(omap_dss_pal_timings);
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@ -285,6 +287,8 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
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.vsw = 6,
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.vfp = 6,
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.vbp = 31,
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.interlace = true,
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};
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EXPORT_SYMBOL(omap_dss_ntsc_timings);
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@ -344,6 +344,8 @@ struct omap_video_timings {
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enum omap_dss_signal_level vsync_level;
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/* Hsync logic level */
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enum omap_dss_signal_level hsync_level;
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/* Interlaced or Progressive timings */
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bool interlace;
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/* Pixel clock edge to drive LCD data */
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enum omap_dss_signal_edge data_pclk_edge;
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/* Data enable logic level */
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