octeontx2-af: Config NPC KPU engines with parser profile
This patch configures all 16 KPUs and iKPU (pkinds) with the KPU parser profile defined in npc_profile.h. Each KPU engine has a 128 entry CAM, only CAM entries which are listed in the profile are enabled and rest are left disabled. Also - Memory is allocated for pkind's bitmap and PFFUNC, interface channel mapping. - Added all CSR offsets of NPC HW block. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sunil Goutham
David S. Miller
parent
21e6699e5c
commit
23923ea4b1
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@ -8,4 +8,4 @@ obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o
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octeontx2_mbox-y := mbox.o
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octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
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rvu_reg.o
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rvu_reg.o rvu_npc.o
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@ -140,4 +140,104 @@ struct npc_kpu_profile {
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struct npc_kpu_profile_action *action;
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};
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/* NPC KPU register formats */
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struct npc_kpu_cam {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u64 rsvd_63_56 : 8;
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u64 state : 8;
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u64 dp2_data : 16;
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u64 dp1_data : 16;
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u64 dp0_data : 16;
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#else
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u64 dp0_data : 16;
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u64 dp1_data : 16;
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u64 dp2_data : 16;
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u64 state : 8;
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u64 rsvd_63_56 : 8;
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#endif
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};
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struct npc_kpu_action0 {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u64 rsvd_63_57 : 7;
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u64 byp_count : 3;
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u64 capture_ena : 1;
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u64 parse_done : 1;
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u64 next_state : 8;
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u64 rsvd_43 : 1;
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u64 capture_lid : 3;
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u64 capture_ltype : 4;
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u64 capture_flags : 8;
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u64 ptr_advance : 8;
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u64 var_len_offset : 8;
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u64 var_len_mask : 8;
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u64 var_len_right : 1;
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u64 var_len_shift : 3;
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#else
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u64 var_len_shift : 3;
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u64 var_len_right : 1;
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u64 var_len_mask : 8;
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u64 var_len_offset : 8;
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u64 ptr_advance : 8;
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u64 capture_flags : 8;
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u64 capture_ltype : 4;
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u64 capture_lid : 3;
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u64 rsvd_43 : 1;
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u64 next_state : 8;
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u64 parse_done : 1;
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u64 capture_ena : 1;
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u64 byp_count : 3;
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u64 rsvd_63_57 : 7;
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#endif
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};
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struct npc_kpu_action1 {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u64 rsvd_63_36 : 28;
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u64 errlev : 4;
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u64 errcode : 8;
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u64 dp2_offset : 8;
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u64 dp1_offset : 8;
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u64 dp0_offset : 8;
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#else
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u64 dp0_offset : 8;
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u64 dp1_offset : 8;
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u64 dp2_offset : 8;
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u64 errcode : 8;
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u64 errlev : 4;
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u64 rsvd_63_36 : 28;
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#endif
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};
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struct npc_kpu_pkind_cpi_def {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u64 ena : 1;
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u64 rsvd_62_59 : 4;
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u64 lid : 3;
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u64 ltype_match : 4;
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u64 ltype_mask : 4;
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u64 flags_match : 8;
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u64 flags_mask : 8;
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u64 add_offset : 8;
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u64 add_mask : 8;
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u64 rsvd_15 : 1;
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u64 add_shift : 3;
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u64 rsvd_11_10 : 2;
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u64 cpi_base : 10;
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#else
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u64 cpi_base : 10;
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u64 rsvd_11_10 : 2;
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u64 add_shift : 3;
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u64 rsvd_15 : 1;
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u64 add_mask : 8;
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u64 add_offset : 8;
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u64 flags_mask : 8;
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u64 flags_match : 8;
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u64 ltype_mask : 4;
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u64 ltype_match : 4;
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u64 lid : 3;
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u64 rsvd_62_59 : 4;
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u64 ena : 1;
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#endif
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};
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#endif /* NPC_H */
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@ -180,6 +180,9 @@ int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc)
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bool is_pf;
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switch (blktype) {
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case BLKTYPE_NPC:
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blkaddr = BLKADDR_NPC;
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goto exit;
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case BLKTYPE_NPA:
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blkaddr = BLKADDR_NPA;
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goto exit;
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@ -566,6 +569,7 @@ static void rvu_free_hw_resources(struct rvu *rvu)
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u64 cfg;
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rvu_npa_freemem(rvu);
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rvu_npc_freemem(rvu);
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rvu_nix_freemem(rvu);
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/* Free block LF bitmaps */
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@ -771,6 +775,10 @@ init:
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rvu_scan_block(rvu, block);
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}
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err = rvu_npc_init(rvu);
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if (err)
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return err;
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err = rvu_npa_init(rvu);
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if (err)
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return err;
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@ -100,6 +100,11 @@ struct nix_txsch {
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u16 *pfvf_map;
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};
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struct npc_pkind {
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struct rsrc_bmap rsrc;
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u32 *pfchan_map;
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};
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struct nix_hw {
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struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
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};
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@ -113,9 +118,12 @@ struct rvu_hwinfo {
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u8 cgx_links;
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u8 lbk_links;
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u8 sdp_links;
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u8 npc_kpus; /* No of parser units */
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struct rvu_block block[BLK_COUNT]; /* Block info */
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struct nix_hw *nix0;
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struct npc_pkind pkind;
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};
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struct rvu {
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@ -290,4 +298,8 @@ int rvu_mbox_handler_NIX_TXSCHQ_CFG(struct rvu *rvu,
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struct msg_rsp *rsp);
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int rvu_mbox_handler_NIX_STATS_RST(struct rvu *rvu, struct msg_req *req,
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struct msg_rsp *rsp);
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/* NPC APIs */
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int rvu_npc_init(struct rvu *rvu);
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void rvu_npc_freemem(struct rvu *rvu);
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#endif /* RVU_H */
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@ -0,0 +1,203 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Marvell OcteonTx2 RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "rvu_struct.h"
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#include "rvu_reg.h"
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#include "rvu.h"
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#include "npc.h"
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#include "npc_profile.h"
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static void npc_config_kpuaction(struct rvu *rvu, int blkaddr,
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struct npc_kpu_profile_action *kpuaction,
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int kpu, int entry, bool pkind)
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{
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struct npc_kpu_action0 action0 = {0};
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struct npc_kpu_action1 action1 = {0};
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u64 reg;
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action1.errlev = kpuaction->errlev;
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action1.errcode = kpuaction->errcode;
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action1.dp0_offset = kpuaction->dp0_offset;
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action1.dp1_offset = kpuaction->dp1_offset;
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action1.dp2_offset = kpuaction->dp2_offset;
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if (pkind)
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reg = NPC_AF_PKINDX_ACTION1(entry);
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else
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reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry);
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rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1);
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action0.byp_count = kpuaction->bypass_count;
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action0.capture_ena = kpuaction->cap_ena;
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action0.parse_done = kpuaction->parse_done;
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action0.next_state = kpuaction->next_state;
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action0.capture_lid = kpuaction->lid;
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action0.capture_ltype = kpuaction->ltype;
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action0.capture_flags = kpuaction->flags;
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action0.ptr_advance = kpuaction->ptr_advance;
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action0.var_len_offset = kpuaction->offset;
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action0.var_len_mask = kpuaction->mask;
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action0.var_len_right = kpuaction->right;
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action0.var_len_shift = kpuaction->shift;
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if (pkind)
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reg = NPC_AF_PKINDX_ACTION0(entry);
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else
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reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry);
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rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0);
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}
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static void npc_config_kpucam(struct rvu *rvu, int blkaddr,
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struct npc_kpu_profile_cam *kpucam,
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int kpu, int entry)
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{
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struct npc_kpu_cam cam0 = {0};
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struct npc_kpu_cam cam1 = {0};
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cam1.state = kpucam->state & kpucam->state_mask;
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cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask;
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cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask;
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cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask;
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cam0.state = ~kpucam->state & kpucam->state_mask;
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cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask;
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cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask;
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cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask;
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rvu_write64(rvu, blkaddr,
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NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0);
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rvu_write64(rvu, blkaddr,
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NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1);
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}
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static inline u64 enable_mask(int count)
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{
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return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL));
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}
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static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu,
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struct npc_kpu_profile *profile)
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{
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int entry, num_entries, max_entries;
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if (profile->cam_entries != profile->action_entries) {
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dev_err(rvu->dev,
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"KPU%d: CAM and action entries [%d != %d] not equal\n",
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kpu, profile->cam_entries, profile->action_entries);
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}
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max_entries = rvu_read64(rvu, blkaddr, NPC_AF_CONST1) & 0xFFF;
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/* Program CAM match entries for previous KPU extracted data */
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num_entries = min_t(int, profile->cam_entries, max_entries);
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for (entry = 0; entry < num_entries; entry++)
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npc_config_kpucam(rvu, blkaddr,
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&profile->cam[entry], kpu, entry);
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/* Program this KPU's actions */
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num_entries = min_t(int, profile->action_entries, max_entries);
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for (entry = 0; entry < num_entries; entry++)
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npc_config_kpuaction(rvu, blkaddr, &profile->action[entry],
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kpu, entry, false);
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/* Enable all programmed entries */
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num_entries = min_t(int, profile->action_entries, profile->cam_entries);
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rvu_write64(rvu, blkaddr,
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NPC_AF_KPUX_ENTRY_DISX(kpu, 0), enable_mask(num_entries));
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if (num_entries > 64) {
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rvu_write64(rvu, blkaddr,
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NPC_AF_KPUX_ENTRY_DISX(kpu, 1),
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enable_mask(num_entries - 64));
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}
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/* Enable this KPU */
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rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01);
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}
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static void npc_parser_profile_init(struct rvu *rvu, int blkaddr)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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int num_pkinds, num_kpus, idx;
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struct npc_pkind *pkind;
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/* Get HW limits */
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hw->npc_kpus = (rvu_read64(rvu, blkaddr, NPC_AF_CONST) >> 8) & 0x1F;
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/* Disable all KPUs and their entries */
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for (idx = 0; idx < hw->npc_kpus; idx++) {
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rvu_write64(rvu, blkaddr,
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NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL);
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rvu_write64(rvu, blkaddr,
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NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL);
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rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00);
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}
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/* First program IKPU profile i.e PKIND configs.
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* Check HW max count to avoid configuring junk or
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* writing to unsupported CSR addresses.
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*/
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pkind = &hw->pkind;
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num_pkinds = ARRAY_SIZE(ikpu_action_entries);
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num_pkinds = min_t(int, pkind->rsrc.max, num_pkinds);
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for (idx = 0; idx < num_pkinds; idx++)
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npc_config_kpuaction(rvu, blkaddr,
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&ikpu_action_entries[idx], 0, idx, true);
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/* Program KPU CAM and Action profiles */
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num_kpus = ARRAY_SIZE(npc_kpu_profiles);
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num_kpus = min_t(int, hw->npc_kpus, num_kpus);
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for (idx = 0; idx < num_kpus; idx++)
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npc_program_kpu_profile(rvu, blkaddr,
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idx, &npc_kpu_profiles[idx]);
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}
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int rvu_npc_init(struct rvu *rvu)
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{
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struct npc_pkind *pkind = &rvu->hw->pkind;
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int blkaddr, err;
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
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if (blkaddr < 0) {
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dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
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return -ENODEV;
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}
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/* Allocate resource bimap for pkind*/
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pkind->rsrc.max = (rvu_read64(rvu, blkaddr,
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NPC_AF_CONST1) >> 12) & 0xFF;
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err = rvu_alloc_bitmap(&pkind->rsrc);
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if (err)
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return err;
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/* Allocate mem for pkind to PF and channel mapping info */
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pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max,
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sizeof(u32), GFP_KERNEL);
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if (!pkind->pfchan_map)
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return -ENOMEM;
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/* Configure KPU profile */
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npc_parser_profile_init(rvu, blkaddr);
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return 0;
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}
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void rvu_npc_freemem(struct rvu *rvu)
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{
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struct npc_pkind *pkind = &rvu->hw->pkind;
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kfree(pkind->rsrc.bmap);
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}
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@ -438,4 +438,65 @@
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#define NDC_AF_BLK_RST (0x002F0)
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#define NPC_AF_BLK_RST (0x00040)
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/* NPC */
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#define NPC_AF_CFG (0x00000)
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#define NPC_AF_ACTIVE_PC (0x00010)
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#define NPC_AF_CONST (0x00020)
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#define NPC_AF_CONST1 (0x00030)
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#define NPC_AF_BLK_RST (0x00040)
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#define NPC_AF_MCAM_SCRUB_CTL (0x000a0)
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#define NPC_AF_KCAM_SCRUB_CTL (0x000b0)
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#define NPC_AF_KPUX_CFG(a) (0x00500 | (a) << 3)
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#define NPC_AF_PCK_CFG (0x00600)
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#define NPC_AF_PCK_DEF_OL2 (0x00610)
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#define NPC_AF_PCK_DEF_OIP4 (0x00620)
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#define NPC_AF_PCK_DEF_OIP6 (0x00630)
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#define NPC_AF_PCK_DEF_IIP4 (0x00640)
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#define NPC_AF_KEX_LDATAX_FLAGS_CFG(a) (0x00800 | (a) << 3)
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#define NPC_AF_INTFX_KEX_CFG(a) (0x01010 | (a) << 8)
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#define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (a) << 6)
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#define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (a) << 6)
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#define NPC_AF_PKINDX_CPI_DEFX(a, b) (0x80020ull | (a) << 6 | (b) << 3)
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#define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \
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(0x100000 | (a) << 14 | (b) << 6 | (c) << 3)
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#define NPC_AF_KPUX_ENTRYX_ACTION0(a, b) \
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(0x100020 | (a) << 14 | (b) << 6)
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#define NPC_AF_KPUX_ENTRYX_ACTION1(a, b) \
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(0x100028 | (a) << 14 | (b) << 6)
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#define NPC_AF_KPUX_ENTRY_DISX(a, b) (0x180000 | (a) << 6 | (b) << 3)
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#define NPC_AF_CPIX_CFG(a) (0x200000 | (a) << 3)
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#define NPC_AF_INTFX_LIDX_LTX_LDX_CFG(a, b, c, d) \
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(0x900000 | (a) << 16 | (b) << 12 | (c) << 5 | (d) << 3)
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#define NPC_AF_INTFX_LDATAX_FLAGSX_CFG(a, b, c) \
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(0x980000 | (a) << 16 | (b) << 12 | (c) << 3)
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#define NPC_AF_MCAMEX_BANKX_CAMX_INTF(a, b, c) \
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(0x1000000ull | (a) << 10 | (b) << 6 | (c) << 3)
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#define NPC_AF_MCAMEX_BANKX_CAMX_W0(a, b, c) \
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(0x1000010ull | (a) << 10 | (b) << 6 | (c) << 3)
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#define NPC_AF_MCAMEX_BANKX_CAMX_W1(a, b, c) \
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(0x1000020ull | (a) << 10 | (b) << 6 | (c) << 3)
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#define NPC_AF_MCAMEX_BANKX_CFG(a, b) (0x1800000ull | (a) << 8 | (b) << 4)
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#define NPC_AF_MCAMEX_BANKX_STAT_ACT(a, b) \
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(0x1880000 | (a) << 8 | (b) << 4)
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#define NPC_AF_MATCH_STATX(a) (0x1880008 | (a) << 8)
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#define NPC_AF_INTFX_MISS_STAT_ACT(a) (0x1880040 + (a) * 0x8)
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#define NPC_AF_MCAMEX_BANKX_ACTION(a, b) (0x1900000ull | (a) << 8 | (b) << 4)
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#define NPC_AF_MCAMEX_BANKX_TAG_ACT(a, b) \
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(0x1900008 | (a) << 8 | (b) << 4)
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#define NPC_AF_INTFX_MISS_ACT(a) (0x1a00000 | (a) << 4)
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#define NPC_AF_INTFX_MISS_TAG_ACT(a) (0x1b00008 | (a) << 4)
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#define NPC_AF_MCAM_BANKX_HITX(a, b) (0x1c80000 | (a) << 8 | (b) << 4)
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#define NPC_AF_LKUP_CTL (0x2000000)
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#define NPC_AF_LKUP_DATAX(a) (0x2000200 | (a) << 4)
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#define NPC_AF_LKUP_RESULTX(a) (0x2000400 | (a) << 4)
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#define NPC_AF_INTFX_STAT(a) (0x2000800 | (a) << 4)
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#define NPC_AF_DBG_CTL (0x3000000)
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#define NPC_AF_DBG_STATUS (0x3000010)
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#define NPC_AF_KPUX_DBG(a) (0x3000020 | (a) << 8)
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#define NPC_AF_IKPU_ERR_CTL (0x3000080)
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#define NPC_AF_KPUX_ERR_CTL(a) (0x30000a0 | (a) << 8)
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||||
#define NPC_AF_MCAM_DBG (0x3001000)
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#define NPC_AF_DBG_DATAX(a) (0x3001400 | (a) << 4)
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#define NPC_AF_DBG_RESULTX(a) (0x3001800 | (a) << 4)
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||||
|
||||
#endif /* RVU_REG_H */
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|
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Loading…
Reference in New Issue