powerpc/44x: Enable DYNAMIC_MEMSTART for 440x
DYNAMIC_MEMSTART(old RELOCATABLE) was restricted only to PPC_47x variants of 44x. This patch enables DYNAMIC_MEMSTART for 440x based chipsets. Signed-off-by: Suzuki K. Poulose <suzuki@in.ibm.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linux ppc dev <linuxppc-dev@lists.ozlabs.org> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
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@ -833,7 +833,7 @@ config LOWMEM_CAM_NUM
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config DYNAMIC_MEMSTART
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config DYNAMIC_MEMSTART
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bool "Enable page aligned dynamic load address for kernel (EXPERIMENTAL)"
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bool "Enable page aligned dynamic load address for kernel (EXPERIMENTAL)"
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depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || PPC_47x)
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depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || 44x)
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select NONSTATIC_KERNEL
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select NONSTATIC_KERNEL
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help
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help
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This option enables the kernel to be loaded at any page aligned
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This option enables the kernel to be loaded at any page aligned
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@ -804,12 +804,24 @@ skpinv: addi r4,r4,1 /* Increment */
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/*
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/*
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* Configure and load pinned entry into TLB slot 63.
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* Configure and load pinned entry into TLB slot 63.
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*/
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*/
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#ifdef CONFIG_DYNAMIC_MEMSTART
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/* Read the XLAT entry for our current mapping */
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tlbre r25,r23,PPC44x_TLB_XLAT
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lis r3,KERNELBASE@h
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ori r3,r3,KERNELBASE@l
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/* Use our current RPN entry */
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mr r4,r25
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#else
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lis r3,PAGE_OFFSET@h
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lis r3,PAGE_OFFSET@h
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ori r3,r3,PAGE_OFFSET@l
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ori r3,r3,PAGE_OFFSET@l
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/* Kernel is at the base of RAM */
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/* Kernel is at the base of RAM */
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li r4, 0 /* Load the kernel physical address */
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li r4, 0 /* Load the kernel physical address */
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#endif
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/* Load the kernel PID = 0 */
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/* Load the kernel PID = 0 */
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li r0,0
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li r0,0
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