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net/mlx4_core: Use firmware driven flow steering hash mode 

The Firmware dynamically changes flow steering hash configuration from covering
L2 only to "full" L2/L3/L4 mode needed.  The dynamic change allows the driver
to set hard coded hash configuration which is changed by the firmware from L2
to L2/L3/L4 when attaching the first L3/L4 flow steering rule and back to L2
when there are no more such rules.

Signed-off-by: Hadar Hen Zion <hadarh@mellanox.com>
Signed-off-by: Amir Vadai <amirv@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Hadar Hen Zion 2013-01-30 23:07:09 +00:00 committed by David S. Miller
parent 0d256c0e93
commit 23537b732f
4 changed files with 2 additions and 24 deletions
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4
drivers/net/ethernet/mellanox/mlx4/fw.c
View File

@ -1287,14 +1287,14 @@ int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
/* Enable Ethernet flow steering /* Enable Ethernet flow steering
* with udp unicast and tcp unicast * with udp unicast and tcp unicast
*/ */
MLX4_PUT(inbox, param->fs_hash_enable_bits, MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
INIT_HCA_FS_ETH_BITS_OFFSET); INIT_HCA_FS_ETH_BITS_OFFSET);
MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
/* Enable IPoIB flow steering /* Enable IPoIB flow steering
* with udp unicast and tcp unicast * with udp unicast and tcp unicast
*/ */
MLX4_PUT(inbox, param->fs_hash_enable_bits, MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
INIT_HCA_FS_IB_BITS_OFFSET); INIT_HCA_FS_IB_BITS_OFFSET);
MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);

1
drivers/net/ethernet/mellanox/mlx4/fw.h
View File

@ -171,7 +171,6 @@ struct mlx4_init_hca_param {
u8 log_mpt_sz; u8 log_mpt_sz;
u8 log_uar_sz; u8 log_uar_sz;
u8 uar_page_sz; /* log pg sz in 4k chunks */ u8 uar_page_sz; /* log pg sz in 4k chunks */
u8 fs_hash_enable_bits;
u8 steering_mode; /* for QUERY_HCA */ u8 steering_mode; /* for QUERY_HCA */
u64 dev_cap_enabled; u64 dev_cap_enabled;
}; };

16
drivers/net/ethernet/mellanox/mlx4/main.c
View File

@ -1415,22 +1415,6 @@ static int mlx4_init_hca(struct mlx4_dev *dev)
if (mlx4_is_master(dev)) if (mlx4_is_master(dev))
mlx4_parav_master_pf_caps(dev); mlx4_parav_master_pf_caps(dev);
priv->fs_hash_mode = MLX4_FS_L2_HASH;
switch (priv->fs_hash_mode) {
case MLX4_FS_L2_HASH:
init_hca.fs_hash_enable_bits = 0;
break;
case MLX4_FS_L2_L3_L4_HASH:
/* Enable flow steering with
* udp unicast and tcp unicast
*/
init_hca.fs_hash_enable_bits =
MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN;
break;
}
profile = default_profile; profile = default_profile;
if (dev->caps.steering_mode == if (dev->caps.steering_mode ==
MLX4_STEERING_MODE_DEVICE_MANAGED) MLX4_STEERING_MODE_DEVICE_MANAGED)

5
drivers/net/ethernet/mellanox/mlx4/mlx4.h
View File

@ -60,11 +60,6 @@
#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
#define MLX4_FS_NUM_MCG (1 << 17) #define MLX4_FS_NUM_MCG (1 << 17)
enum {
MLX4_FS_L2_HASH = 0,
MLX4_FS_L2_L3_L4_HASH,
};
#define MLX4_NUM_UP 8 #define MLX4_NUM_UP 8
#define MLX4_NUM_TC 8 #define MLX4_NUM_TC 8
#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */ #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */