ARM: OMAP2: Add pinmux support for omap34xx
This patch adds pinmux support for OMAP3. Incorporated review comments from Tony to make mux_value as bit mask. Tested on 3430SDP. Also merge in adding of I2C pins from Jarkko Nikula. Acked-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Vikram Pandita
Tony Lindgren
parent
0e56484869
commit
2351872c44
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@ -1,7 +1,7 @@
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/*
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* linux/arch/arm/mach-omap2/mux.c
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*
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* OMAP2 pin multiplexing configurations
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* OMAP2 and OMAP3 pin multiplexing configurations
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*
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* Copyright (C) 2004 - 2008 Texas Instruments Inc.
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* Copyright (C) 2003 - 2008 Nokia Corporation
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@ -219,16 +219,179 @@ MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
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#define OMAP24XX_PINS_SZ 0
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#endif /* CONFIG_ARCH_OMAP24XX */
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#define OMAP24XX_PULL_ENA (1 << 3)
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#define OMAP24XX_PULL_UP (1 << 4)
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#ifdef CONFIG_ARCH_OMAP34XX
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static struct pin_config __initdata_or_module omap34xx_pins[] = {
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/*
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* Name, reg-offset,
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* mux-mode | [active-mode | off-mode]
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*/
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/* 34xx I2C */
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MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
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OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
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OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
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OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
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OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
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OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
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OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
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OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
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OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
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/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
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MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
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MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
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OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
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/* TLL - HSUSB: 12-pin TLL Port 1*/
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MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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/* TLL - HSUSB: 12-pin TLL Port 2*/
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MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
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OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
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OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
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OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
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OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
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OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
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OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
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OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
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/* TLL - HSUSB: 12-pin TLL Port 3*/
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MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
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MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
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MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
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OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
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};
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#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
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#else
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#define omap34xx_pins NULL
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#define OMAP34XX_PINS_SZ 0
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#endif /* CONFIG_ARCH_OMAP34XX */
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#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
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void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
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static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
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{
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u16 orig;
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u8 warn = 0, debug = 0;
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orig = omap_ctrl_readb(cfg->mux_reg);
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if (cpu_is_omap24xx())
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orig = omap_ctrl_readb(cfg->mux_reg);
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else
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orig = omap_ctrl_readw(cfg->mux_reg);
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#ifdef CONFIG_OMAP_MUX_DEBUG
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debug = cfg->debug;
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@ -254,9 +417,9 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
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spin_lock_irqsave(&mux_spin_lock, flags);
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reg |= cfg->mask & 0x7;
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if (cfg->pull_val)
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reg |= OMAP24XX_PULL_ENA;
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reg |= OMAP2_PULL_ENA;
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if (cfg->pu_pd_val)
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reg |= OMAP24XX_PULL_UP;
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reg |= OMAP2_PULL_UP;
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omap2_cfg_debug(cfg, reg);
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omap_ctrl_writeb(reg, cfg->mux_reg);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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@ -264,7 +427,26 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
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return 0;
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}
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#else
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#define omap24xx_cfg_reg 0
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#define omap24xx_cfg_reg NULL
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#endif
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#ifdef CONFIG_ARCH_OMAP34XX
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static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
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{
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static DEFINE_SPINLOCK(mux_spin_lock);
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unsigned long flags;
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u16 reg = 0;
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spin_lock_irqsave(&mux_spin_lock, flags);
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reg |= cfg->mux_val;
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omap2_cfg_debug(cfg, reg);
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omap_ctrl_writew(reg, cfg->mux_reg);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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return 0;
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}
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#else
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#define omap34xx_cfg_reg NULL
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#endif
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int __init omap2_mux_init(void)
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@ -273,6 +455,10 @@ int __init omap2_mux_init(void)
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arch_mux_cfg.pins = omap24xx_pins;
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arch_mux_cfg.size = OMAP24XX_PINS_SZ;
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arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
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} else if (cpu_is_omap34xx()) {
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arch_mux_cfg.pins = omap34xx_pins;
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arch_mux_cfg.size = OMAP34XX_PINS_SZ;
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arch_mux_cfg.cfg_reg = omap34xx_cfg_reg;
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}
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return omap_mux_register(&arch_mux_cfg);
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@ -125,20 +125,64 @@
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.pu_pd_val = pull_mode, \
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},
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/* 24xx/34xx mux bit defines */
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#define OMAP2_PULL_ENA (1 << 3)
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#define OMAP2_PULL_UP (1 << 4)
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#define OMAP2_ALTELECTRICALSEL (1 << 5)
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#define PULL_DISABLED 0
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#define PULL_ENABLED 1
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/* 34xx specific mux bit defines */
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#define OMAP3_INPUT_EN (1 << 8)
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#define OMAP3_OFF_EN (1 << 9)
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#define OMAP3_OFFOUT_EN (1 << 10)
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#define OMAP3_OFFOUT_VAL (1 << 11)
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#define OMAP3_OFF_PULL_EN (1 << 12)
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#define OMAP3_OFF_PULL_UP (1 << 13)
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#define OMAP3_WAKEUP_EN (1 << 14)
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#define PULL_DOWN 0
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#define PULL_UP 1
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/* 34xx mux mode options for each pin. See TRM for options */
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#define OMAP34XX_MUX_MODE0 0
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#define OMAP34XX_MUX_MODE1 1
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#define OMAP34XX_MUX_MODE2 2
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#define OMAP34XX_MUX_MODE3 3
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#define OMAP34XX_MUX_MODE4 4
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#define OMAP34XX_MUX_MODE5 5
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#define OMAP34XX_MUX_MODE6 6
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#define OMAP34XX_MUX_MODE7 7
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/* 34xx active pin states */
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#define OMAP34XX_PIN_OUTPUT 0
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#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
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#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
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| OMAP2_PULL_UP)
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#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
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/* 34xx off mode states */
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#define OMAP34XX_PIN_OFF_NONE 0
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#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
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| OMAP3_OFFOUT_VAL)
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#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
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#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
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| OMAP3_OFF_PULL_UP)
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#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
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#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
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#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
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.name = desc, \
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.debug = 0, \
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.mux_reg = reg_offset, \
|
||||
.mux_val = mux_value \
|
||||
},
|
||||
|
||||
struct pin_config {
|
||||
char *name;
|
||||
unsigned char busy;
|
||||
unsigned char debug;
|
||||
char *name;
|
||||
const unsigned int mux_reg;
|
||||
unsigned char debug;
|
||||
|
||||
const char *mux_reg_name;
|
||||
const unsigned int mux_reg;
|
||||
#if defined(CONFIG_ARCH_OMAP34XX)
|
||||
u16 mux_val; /* Wake-up, off mode, pull, mux mode */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
|
||||
const unsigned char mask_offset;
|
||||
const unsigned char mask;
|
||||
|
||||
|
|
@ -150,6 +194,12 @@ struct pin_config {
|
|||
const char *pu_pd_name;
|
||||
const unsigned int pu_pd_reg;
|
||||
const unsigned char pu_pd_val;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
|
||||
const char *mux_reg_name;
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
enum omap730_index {
|
||||
|
|
@ -593,6 +643,90 @@ enum omap24xx_index {
|
|||
|
||||
};
|
||||
|
||||
enum omap34xx_index {
|
||||
/* 34xx I2C */
|
||||
K21_34XX_I2C1_SCL,
|
||||
J21_34XX_I2C1_SDA,
|
||||
AF15_34XX_I2C2_SCL,
|
||||
AE15_34XX_I2C2_SDA,
|
||||
AF14_34XX_I2C3_SCL,
|
||||
AG14_34XX_I2C3_SDA,
|
||||
AD26_34XX_I2C4_SCL,
|
||||
AE26_34XX_I2C4_SDA,
|
||||
|
||||
/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
|
||||
Y8_3430_USB1HS_PHY_CLK,
|
||||
Y9_3430_USB1HS_PHY_STP,
|
||||
AA14_3430_USB1HS_PHY_DIR,
|
||||
AA11_3430_USB1HS_PHY_NXT,
|
||||
W13_3430_USB1HS_PHY_DATA0,
|
||||
W12_3430_USB1HS_PHY_DATA1,
|
||||
W11_3430_USB1HS_PHY_DATA2,
|
||||
Y11_3430_USB1HS_PHY_DATA3,
|
||||
W9_3430_USB1HS_PHY_DATA4,
|
||||
Y12_3430_USB1HS_PHY_DATA5,
|
||||
W8_3430_USB1HS_PHY_DATA6,
|
||||
Y13_3430_USB1HS_PHY_DATA7,
|
||||
|
||||
/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
|
||||
AA8_3430_USB2HS_PHY_CLK,
|
||||
AA10_3430_USB2HS_PHY_STP,
|
||||
AA9_3430_USB2HS_PHY_DIR,
|
||||
AB11_3430_USB2HS_PHY_NXT,
|
||||
AB10_3430_USB2HS_PHY_DATA0,
|
||||
AB9_3430_USB2HS_PHY_DATA1,
|
||||
W3_3430_USB2HS_PHY_DATA2,
|
||||
T4_3430_USB2HS_PHY_DATA3,
|
||||
T3_3430_USB2HS_PHY_DATA4,
|
||||
R3_3430_USB2HS_PHY_DATA5,
|
||||
R4_3430_USB2HS_PHY_DATA6,
|
||||
T2_3430_USB2HS_PHY_DATA7,
|
||||
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 1*/
|
||||
Y8_3430_USB1HS_TLL_CLK,
|
||||
Y9_3430_USB1HS_TLL_STP,
|
||||
AA14_3430_USB1HS_TLL_DIR,
|
||||
AA11_3430_USB1HS_TLL_NXT,
|
||||
W13_3430_USB1HS_TLL_DATA0,
|
||||
W12_3430_USB1HS_TLL_DATA1,
|
||||
W11_3430_USB1HS_TLL_DATA2,
|
||||
Y11_3430_USB1HS_TLL_DATA3,
|
||||
W9_3430_USB1HS_TLL_DATA4,
|
||||
Y12_3430_USB1HS_TLL_DATA5,
|
||||
W8_3430_USB1HS_TLL_DATA6,
|
||||
Y13_3430_USB1HS_TLL_DATA7,
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 2*/
|
||||
AA8_3430_USB2HS_TLL_CLK,
|
||||
AA10_3430_USB2HS_TLL_STP,
|
||||
AA9_3430_USB2HS_TLL_DIR,
|
||||
AB11_3430_USB2HS_TLL_NXT,
|
||||
AB10_3430_USB2HS_TLL_DATA0,
|
||||
AB9_3430_USB2HS_TLL_DATA1,
|
||||
W3_3430_USB2HS_TLL_DATA2,
|
||||
T4_3430_USB2HS_TLL_DATA3,
|
||||
T3_3430_USB2HS_TLL_DATA4,
|
||||
R3_3430_USB2HS_TLL_DATA5,
|
||||
R4_3430_USB2HS_TLL_DATA6,
|
||||
T2_3430_USB2HS_TLL_DATA7,
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 3*/
|
||||
AA6_3430_USB3HS_TLL_CLK,
|
||||
AB3_3430_USB3HS_TLL_STP,
|
||||
AA3_3430_USB3HS_TLL_DIR,
|
||||
Y3_3430_USB3HS_TLL_NXT,
|
||||
AA5_3430_USB3HS_TLL_DATA0,
|
||||
Y4_3430_USB3HS_TLL_DATA1,
|
||||
Y5_3430_USB3HS_TLL_DATA2,
|
||||
W5_3430_USB3HS_TLL_DATA3,
|
||||
AB12_3430_USB3HS_TLL_DATA4,
|
||||
AB13_3430_USB3HS_TLL_DATA5,
|
||||
AA13_3430_USB3HS_TLL_DATA6,
|
||||
AA12_3430_USB3HS_TLL_DATA7
|
||||
|
||||
};
|
||||
|
||||
struct omap_mux_cfg {
|
||||
struct pin_config *pins;
|
||||
unsigned long size;
|
||||
|
|
|
|||
Loading…
Reference in New Issue