dmaengine: ti: k3-psil: Add initial map for AM64
Add initial PSI-L map file for AM64. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20201208090440.31792-15-peter.ujfalusi@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Peter Ujfalusi
Vinod Koul
parent
b9366e2577
commit
2329725d1a
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@ -7,5 +7,6 @@ obj-$(CONFIG_TI_K3_UDMA_GLUE_LAYER) += k3-udma-glue.o
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obj-$(CONFIG_TI_K3_PSIL) += k3-psil.o \
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k3-psil-am654.o \
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k3-psil-j721e.o \
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k3-psil-j7200.o
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k3-psil-j7200.o \
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k3-psil-am64.o
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obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o
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@ -0,0 +1,158 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
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* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
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*/
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#include <linux/kernel.h>
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#include "k3-psil-priv.h"
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#define PSIL_PDMA_XY_TR(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.mapped_channel_id = -1, \
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.default_flow_id = -1, \
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}, \
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}
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#define PSIL_PDMA_XY_PKT(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.mapped_channel_id = -1, \
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.default_flow_id = -1, \
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.pkt_mode = 1, \
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}, \
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}
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#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 16, \
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.mapped_channel_id = ch, \
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.flow_start = flow_base, \
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.flow_num = flow_cnt, \
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.default_flow_id = flow_base, \
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}, \
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}
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#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 64, \
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.mapped_channel_id = ch, \
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.flow_start = flow_base, \
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.flow_num = flow_cnt, \
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.default_flow_id = default_flow, \
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.notdpkt = tx, \
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}, \
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}
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/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
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static struct psil_ep am64_src_ep_map[] = {
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/* SAUL */
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PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
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PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
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PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
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PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
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/* ICSS_G0 */
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PSIL_ETHERNET(0x4100, 21, 48, 16),
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PSIL_ETHERNET(0x4101, 22, 64, 16),
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PSIL_ETHERNET(0x4102, 23, 80, 16),
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PSIL_ETHERNET(0x4103, 24, 96, 16),
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/* ICSS_G1 */
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PSIL_ETHERNET(0x4200, 25, 112, 16),
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PSIL_ETHERNET(0x4201, 26, 128, 16),
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PSIL_ETHERNET(0x4202, 27, 144, 16),
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PSIL_ETHERNET(0x4203, 28, 160, 16),
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/* PDMA_MAIN0 - SPI0-3 */
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PSIL_PDMA_XY_PKT(0x4300),
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PSIL_PDMA_XY_PKT(0x4301),
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PSIL_PDMA_XY_PKT(0x4302),
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PSIL_PDMA_XY_PKT(0x4303),
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PSIL_PDMA_XY_PKT(0x4304),
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PSIL_PDMA_XY_PKT(0x4305),
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PSIL_PDMA_XY_PKT(0x4306),
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PSIL_PDMA_XY_PKT(0x4307),
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PSIL_PDMA_XY_PKT(0x4308),
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PSIL_PDMA_XY_PKT(0x4309),
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PSIL_PDMA_XY_PKT(0x430a),
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PSIL_PDMA_XY_PKT(0x430b),
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PSIL_PDMA_XY_PKT(0x430c),
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PSIL_PDMA_XY_PKT(0x430d),
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PSIL_PDMA_XY_PKT(0x430e),
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PSIL_PDMA_XY_PKT(0x430f),
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/* PDMA_MAIN0 - USART0-1 */
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PSIL_PDMA_XY_PKT(0x4310),
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PSIL_PDMA_XY_PKT(0x4311),
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/* PDMA_MAIN1 - SPI4 */
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PSIL_PDMA_XY_PKT(0x4400),
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PSIL_PDMA_XY_PKT(0x4401),
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PSIL_PDMA_XY_PKT(0x4402),
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PSIL_PDMA_XY_PKT(0x4403),
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/* PDMA_MAIN1 - USART2-6 */
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PSIL_PDMA_XY_PKT(0x4404),
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PSIL_PDMA_XY_PKT(0x4405),
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PSIL_PDMA_XY_PKT(0x4406),
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PSIL_PDMA_XY_PKT(0x4407),
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PSIL_PDMA_XY_PKT(0x4408),
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/* PDMA_MAIN1 - ADCs */
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PSIL_PDMA_XY_TR(0x440f),
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PSIL_PDMA_XY_TR(0x4410),
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/* CPSW2 */
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PSIL_ETHERNET(0x4500, 16, 16, 16),
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};
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/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
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static struct psil_ep am64_dst_ep_map[] = {
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/* SAUL */
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PSIL_SAUL(0xc000, 24, 80, 8, 80, 1),
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PSIL_SAUL(0xc001, 25, 88, 8, 88, 1),
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/* ICSS_G0 */
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PSIL_ETHERNET(0xc100, 26, 96, 1),
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PSIL_ETHERNET(0xc101, 27, 97, 1),
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PSIL_ETHERNET(0xc102, 28, 98, 1),
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PSIL_ETHERNET(0xc103, 29, 99, 1),
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PSIL_ETHERNET(0xc104, 30, 100, 1),
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PSIL_ETHERNET(0xc105, 31, 101, 1),
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PSIL_ETHERNET(0xc106, 32, 102, 1),
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PSIL_ETHERNET(0xc107, 33, 103, 1),
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/* ICSS_G1 */
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PSIL_ETHERNET(0xc200, 34, 104, 1),
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PSIL_ETHERNET(0xc201, 35, 105, 1),
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PSIL_ETHERNET(0xc202, 36, 106, 1),
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PSIL_ETHERNET(0xc203, 37, 107, 1),
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PSIL_ETHERNET(0xc204, 38, 108, 1),
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PSIL_ETHERNET(0xc205, 39, 109, 1),
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PSIL_ETHERNET(0xc206, 40, 110, 1),
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PSIL_ETHERNET(0xc207, 41, 111, 1),
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/* CPSW2 */
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PSIL_ETHERNET(0xc500, 16, 16, 8),
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PSIL_ETHERNET(0xc501, 17, 24, 8),
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PSIL_ETHERNET(0xc502, 18, 32, 8),
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PSIL_ETHERNET(0xc503, 19, 40, 8),
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PSIL_ETHERNET(0xc504, 20, 48, 8),
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PSIL_ETHERNET(0xc505, 21, 56, 8),
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PSIL_ETHERNET(0xc506, 22, 64, 8),
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PSIL_ETHERNET(0xc507, 23, 72, 8),
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};
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struct psil_ep_map am64_ep_map = {
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.name = "am64",
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.src = am64_src_ep_map,
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.src_count = ARRAY_SIZE(am64_src_ep_map),
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.dst = am64_dst_ep_map,
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.dst_count = ARRAY_SIZE(am64_dst_ep_map),
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};
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@ -40,5 +40,6 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id);
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extern struct psil_ep_map am654_ep_map;
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extern struct psil_ep_map j721e_ep_map;
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extern struct psil_ep_map j7200_ep_map;
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extern struct psil_ep_map am64_ep_map;
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#endif /* K3_PSIL_PRIV_H_ */
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@ -20,6 +20,7 @@ static const struct soc_device_attribute k3_soc_devices[] = {
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{ .family = "AM65X", .data = &am654_ep_map },
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{ .family = "J721E", .data = &j721e_ep_map },
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{ .family = "J7200", .data = &j7200_ep_map },
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{ .family = "AM64X", .data = &am64_ep_map },
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{ /* sentinel */ }
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};
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