ath5k: remove ATH_TRACE macro
Now that we have ftrace, it is not needed any more. Signed-off-by: Bruno Randolf <br1@einfach.org> Acked-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
afe86286a1
commit
230fc4f3b2
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@ -351,8 +351,6 @@ err_free:
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*/
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void ath5k_hw_detach(struct ath5k_hw *ah)
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{
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ATH5K_TRACE(ah->ah_sc);
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__set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
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if (ah->ah_rf_banks != NULL)
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@ -34,7 +34,6 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
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{
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u16 ee_header;
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ATH5K_TRACE(ah->ah_sc);
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/* Capabilities stored in the EEPROM */
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ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
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@ -123,8 +122,6 @@ int ath5k_hw_get_capability(struct ath5k_hw *ah,
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enum ath5k_capability_type cap_type,
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u32 capability, u32 *result)
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{
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ATH5K_TRACE(ah->ah_sc);
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switch (cap_type) {
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case AR5K_CAP_NUM_TXQUEUES:
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if (result) {
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@ -173,8 +170,6 @@ yes:
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int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
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u16 assoc_id)
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{
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ATH5K_TRACE(ah->ah_sc);
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if (ah->ah_version == AR5K_AR5210) {
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AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
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AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
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@ -186,8 +181,6 @@ int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
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int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
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{
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ATH5K_TRACE(ah->ah_sc);
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if (ah->ah_version == AR5K_AR5210) {
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AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
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AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
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@ -307,7 +307,6 @@ static const struct {
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{ ATH5K_DEBUG_DUMP_RX, "dumprx", "print received skb content" },
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{ ATH5K_DEBUG_DUMP_TX, "dumptx", "print transmit skb content" },
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{ ATH5K_DEBUG_DUMPBANDS, "dumpbands", "dump bands" },
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{ ATH5K_DEBUG_TRACE, "trace", "trace function calls" },
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{ ATH5K_DEBUG_ANI, "ani", "adaptive noise immunity" },
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{ ATH5K_DEBUG_ANY, "all", "show all debug levels" },
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};
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@ -115,18 +115,12 @@ enum ath5k_debug_level {
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ATH5K_DEBUG_DUMP_RX = 0x00000100,
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ATH5K_DEBUG_DUMP_TX = 0x00000200,
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ATH5K_DEBUG_DUMPBANDS = 0x00000400,
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ATH5K_DEBUG_TRACE = 0x00001000,
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ATH5K_DEBUG_ANI = 0x00002000,
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ATH5K_DEBUG_ANY = 0xffffffff
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};
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#ifdef CONFIG_ATH5K_DEBUG
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#define ATH5K_TRACE(_sc) do { \
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if (unlikely((_sc)->debug.level & ATH5K_DEBUG_TRACE)) \
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printk(KERN_DEBUG "ath5k trace %s:%d\n", __func__, __LINE__); \
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} while (0)
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#define ATH5K_DBG(_sc, _m, _fmt, ...) do { \
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if (unlikely((_sc)->debug.level & (_m) && net_ratelimit())) \
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ATH5K_PRINTK(_sc, KERN_DEBUG, "(%s:%d): " _fmt, \
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@ -168,8 +162,6 @@ ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf);
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#include <linux/compiler.h>
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#define ATH5K_TRACE(_sc) typecheck(struct ath5k_softc *, (_sc))
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static inline void __attribute__ ((format (printf, 3, 4)))
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ATH5K_DBG(struct ath5k_softc *sc, unsigned int m, const char *fmt, ...) {}
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@ -176,7 +176,6 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
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struct ath5k_hw_4w_tx_ctl *tx_ctl;
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unsigned int frame_len;
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ATH5K_TRACE(ah->ah_sc);
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tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
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/*
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@ -342,8 +341,6 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
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struct ath5k_hw_2w_tx_ctl *tx_ctl;
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struct ath5k_hw_tx_status *tx_status;
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ATH5K_TRACE(ah->ah_sc);
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tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
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tx_status = &desc->ud.ds_tx5210.tx_stat;
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@ -396,8 +393,6 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
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struct ath5k_hw_4w_tx_ctl *tx_ctl;
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struct ath5k_hw_tx_status *tx_status;
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ATH5K_TRACE(ah->ah_sc);
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tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
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tx_status = &desc->ud.ds_tx5212.tx_stat;
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@ -490,7 +485,6 @@ static int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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{
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struct ath5k_hw_rx_ctl *rx_ctl;
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ATH5K_TRACE(ah->ah_sc);
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rx_ctl = &desc->ud.ds_rx.rx_ctl;
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/*
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@ -593,7 +587,6 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
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struct ath5k_hw_rx_status *rx_status;
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struct ath5k_hw_rx_error *rx_err;
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ATH5K_TRACE(ah->ah_sc);
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rx_status = &desc->ud.ds_rx.u.rx_stat;
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/* Overlay on error */
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@ -48,7 +48,6 @@
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*/
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void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
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{
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ATH5K_TRACE(ah->ah_sc);
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ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
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ath5k_hw_reg_read(ah, AR5K_CR);
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}
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@ -62,7 +61,6 @@ int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
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{
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unsigned int i;
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ATH5K_TRACE(ah->ah_sc);
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ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
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/*
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@ -96,8 +94,6 @@ u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
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*/
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void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
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{
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ATH5K_TRACE(ah->ah_sc);
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ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
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}
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@ -125,7 +121,6 @@ int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
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{
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u32 tx_queue;
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ATH5K_TRACE(ah->ah_sc);
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AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
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/* Return if queue is declared inactive */
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@ -186,7 +181,6 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
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unsigned int i = 40;
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u32 tx_queue, pending;
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ATH5K_TRACE(ah->ah_sc);
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AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
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/* Return if queue is declared inactive */
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@ -297,7 +291,6 @@ u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
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{
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u16 tx_reg;
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ATH5K_TRACE(ah->ah_sc);
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AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
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/*
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@ -340,7 +333,6 @@ int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
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{
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u16 tx_reg;
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ATH5K_TRACE(ah->ah_sc);
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AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
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/*
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@ -400,8 +392,6 @@ int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
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u32 trigger_level, imr;
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int ret = -EIO;
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ATH5K_TRACE(ah->ah_sc);
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/*
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* Disable interrupts by setting the mask
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*/
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@ -451,7 +441,6 @@ done:
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*/
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bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
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{
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ATH5K_TRACE(ah->ah_sc);
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return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
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}
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@ -475,8 +464,6 @@ int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
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{
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u32 data;
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ATH5K_TRACE(ah->ah_sc);
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/*
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* Read interrupt status from the Interrupt Status register
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* on 5210
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@ -35,7 +35,6 @@ static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
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{
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u32 status, timeout;
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ATH5K_TRACE(ah->ah_sc);
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/*
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* Initialize EEPROM access
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*/
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@ -34,8 +34,6 @@ void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
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/*5210 has different led mode handling*/
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u32 led_5210;
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ATH5K_TRACE(ah->ah_sc);
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/*Reset led status*/
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if (ah->ah_version != AR5K_AR5210)
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AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
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@ -82,7 +80,6 @@ void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
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*/
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int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
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{
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ATH5K_TRACE(ah->ah_sc);
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if (gpio >= AR5K_NUM_GPIO)
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return -EINVAL;
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@ -98,7 +95,6 @@ int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
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*/
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int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
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{
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ATH5K_TRACE(ah->ah_sc);
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if (gpio >= AR5K_NUM_GPIO)
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return -EINVAL;
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@ -114,7 +110,6 @@ int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
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*/
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u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
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{
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ATH5K_TRACE(ah->ah_sc);
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if (gpio >= AR5K_NUM_GPIO)
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return 0xffffffff;
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@ -129,7 +124,6 @@ u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
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int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
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{
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u32 data;
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ATH5K_TRACE(ah->ah_sc);
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if (gpio >= AR5K_NUM_GPIO)
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return -EINVAL;
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@ -153,7 +147,6 @@ void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
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{
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u32 data;
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ATH5K_TRACE(ah->ah_sc);
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if (gpio >= AR5K_NUM_GPIO)
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return;
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@ -59,8 +59,6 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
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beacon_reg = 0;
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ATH5K_TRACE(ah->ah_sc);
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switch (op_mode) {
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case NL80211_IFTYPE_ADHOC:
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pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
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@ -173,7 +171,6 @@ void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
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*/
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static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
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{
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ATH5K_TRACE(ah->ah_sc);
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if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
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<= timeout)
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return -EINVAL;
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@ -192,7 +189,6 @@ static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
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*/
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static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
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{
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ATH5K_TRACE(ah->ah_sc);
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if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
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<= timeout)
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return -EINVAL;
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@ -297,7 +293,6 @@ int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
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u32 low_id, high_id;
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u32 pcu_reg;
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ATH5K_TRACE(ah->ah_sc);
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/* Set new station ID */
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memcpy(common->macaddr, mac, ETH_ALEN);
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@ -357,7 +352,6 @@ void ath5k_hw_set_associd(struct ath5k_hw *ah)
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void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
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{
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struct ath_common *common = ath5k_hw_common(ah);
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ATH5K_TRACE(ah->ah_sc);
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/* Cache bssid mask so that we can restore it
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* on reset */
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@ -382,7 +376,6 @@ void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
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*/
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void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
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{
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ATH5K_TRACE(ah->ah_sc);
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AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
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}
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@ -397,7 +390,6 @@ void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
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*/
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void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
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{
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ATH5K_TRACE(ah->ah_sc);
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AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
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}
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@ -406,8 +398,6 @@ void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
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*/
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void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
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{
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ATH5K_TRACE(ah->ah_sc);
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/* Set the multicat filter */
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ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
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ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
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}
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@ -427,7 +417,6 @@ u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
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{
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u32 data, filter = 0;
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ATH5K_TRACE(ah->ah_sc);
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filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
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/*Radar detection for 5212*/
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@ -457,8 +446,6 @@ void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
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{
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u32 data = 0;
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ATH5K_TRACE(ah->ah_sc);
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/* Set PHY error filter register on 5212*/
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if (ah->ah_version == AR5K_AR5212) {
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if (filter & AR5K_RX_FILTER_RADARERR)
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@ -533,8 +520,6 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
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WARN_ON( i == ATH5K_MAX_TSF_READ );
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ATH5K_TRACE(ah->ah_sc);
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return (((u64)tsf_upper1 << 32) | tsf_lower);
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}
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@ -548,8 +533,6 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
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*/
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void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
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{
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ATH5K_TRACE(ah->ah_sc);
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ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
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ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
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}
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@ -565,8 +548,6 @@ void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
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{
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u32 val;
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ATH5K_TRACE(ah->ah_sc);
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val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
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/*
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@ -586,7 +567,6 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
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{
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u32 timer1, timer2, timer3;
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ATH5K_TRACE(ah->ah_sc);
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/*
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* Set the additional timers by mode
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*/
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@ -674,7 +654,6 @@ int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
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unsigned int i, type;
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u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
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ATH5K_TRACE(ah->ah_sc);
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AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
|
||||
|
||||
type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry));
|
||||
|
@ -749,8 +728,6 @@ int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
|
|||
bool is_tkip;
|
||||
const u8 *key_ptr;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
is_tkip = (key->alg == ALG_TKIP);
|
||||
|
||||
/*
|
||||
|
@ -836,7 +813,6 @@ int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
|
|||
{
|
||||
u32 low_id, high_id;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
/* Invalid entry (key table overflow) */
|
||||
AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
|
||||
|
||||
|
|
|
@ -378,8 +378,6 @@ enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
|
|||
u32 data, type;
|
||||
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
if (ah->ah_rf_banks == NULL ||
|
||||
ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
|
||||
return AR5K_RFGAIN_INACTIVE;
|
||||
|
@ -1353,7 +1351,6 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
|
|||
u32 i_pwr, q_pwr;
|
||||
s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
|
||||
int i;
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
if (!ah->ah_calibration ||
|
||||
ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
|
||||
|
@ -1680,7 +1677,6 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
|
|||
|
||||
int ath5k_hw_phy_disable(struct ath5k_hw *ah)
|
||||
{
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
/*Just a try M.F.*/
|
||||
ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
|
||||
|
||||
|
@ -1696,8 +1692,6 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
|
|||
u32 srev;
|
||||
u16 ret;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
/*
|
||||
* Set the radio chip access register
|
||||
*/
|
||||
|
@ -1742,8 +1736,6 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
|
|||
static void /*TODO:Boundary check*/
|
||||
ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
|
||||
{
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
if (ah->ah_version != AR5K_AR5210)
|
||||
ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
|
||||
}
|
||||
|
@ -1803,8 +1795,6 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
|
|||
|
||||
def_ant = ah->ah_def_ant;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
switch (channel->hw_value & CHANNEL_MODES) {
|
||||
case CHANNEL_A:
|
||||
case CHANNEL_T:
|
||||
|
@ -2968,7 +2958,6 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
|
|||
u8 type;
|
||||
int ret;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
if (txpower > AR5K_TUNE_MAX_TXPOWER) {
|
||||
ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
|
||||
return -EINVAL;
|
||||
|
@ -3064,8 +3053,6 @@ int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
|
|||
struct ieee80211_channel *channel = ah->ah_current_channel;
|
||||
u8 ee_mode;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
switch (channel->hw_value & CHANNEL_MODES) {
|
||||
case CHANNEL_A:
|
||||
case CHANNEL_T:
|
||||
|
|
|
@ -31,7 +31,6 @@ Queue Control Unit, DFS Control Unit Functions
|
|||
int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
|
||||
struct ath5k_txq_info *queue_info)
|
||||
{
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
|
||||
return 0;
|
||||
}
|
||||
|
@ -42,7 +41,6 @@ int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
|
|||
int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
|
||||
const struct ath5k_txq_info *queue_info)
|
||||
{
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
|
||||
|
||||
if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
|
||||
|
@ -69,8 +67,6 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
|
|||
unsigned int queue;
|
||||
int ret;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
/*
|
||||
* Get queue by type
|
||||
*/
|
||||
|
@ -149,7 +145,6 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
|
|||
u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
|
||||
{
|
||||
u32 pending;
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
|
||||
|
||||
/* Return if queue is declared inactive */
|
||||
|
@ -177,7 +172,6 @@ u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
|
|||
*/
|
||||
void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
{
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
|
||||
return;
|
||||
|
||||
|
@ -195,7 +189,6 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
|||
u32 cw_min, cw_max, retry_lg, retry_sh;
|
||||
struct ath5k_txq_info *tq = &ah->ah_txq[queue];
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
|
||||
|
||||
tq = &ah->ah_txq[queue];
|
||||
|
@ -523,8 +516,6 @@ int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
|
|||
{
|
||||
u32 slot_time_clock = ath5k_hw_htoclock(ah, slot_time);
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
if (slot_time < 6 || slot_time_clock > AR5K_SLOT_TIME_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
@ -201,8 +201,6 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
|
|||
int ret;
|
||||
u32 mask = val ? val : ~0U;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
/* Read-and-clear RX Descriptor Pointer*/
|
||||
ath5k_hw_reg_read(ah, AR5K_RXDP);
|
||||
|
||||
|
@ -246,7 +244,6 @@ static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
|
|||
unsigned int i;
|
||||
u32 staid, data;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
|
||||
|
||||
switch (mode) {
|
||||
|
@ -393,8 +390,6 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
|
|||
mode = 0;
|
||||
clock = 0;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
/* Wakeup the device */
|
||||
ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
|
||||
if (ret) {
|
||||
|
@ -896,8 +891,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
|
|||
u8 mode, freq, ee_mode, ant[2];
|
||||
int i, ret;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
|
||||
s_ant = 0;
|
||||
ee_mode = 0;
|
||||
staid1_flags = 0;
|
||||
|
|
Loading…
Reference in New Issue