drm/msm: resync generated headers
resync to latest envytools db, fixes a typo: s/mpd4/mdp4/ Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: David Brown <davidb@codeaurora.org>
This commit is contained in:
Rob Clark
parent
b4b15c865d
commit
22ba8b6b23
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@ -4,16 +4,16 @@
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/* Autogenerated file, DO NOT EDIT manually!
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||||
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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||||
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The rules-ng-ng source files this header was generated from are:
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -317,6 +317,38 @@ static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
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#define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000
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#define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000
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#define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40
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#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f
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#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0
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static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val)
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{
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return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK;
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}
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#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040
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#define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080
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#define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100
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#define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200
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#define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00
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#define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10
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static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val)
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{
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return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK;
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}
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#define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000
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#define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000
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#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000
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#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000
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#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16
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static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
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{
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return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK;
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}
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#define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000
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#define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000
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#define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000
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#define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000
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#define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000
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#define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01
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#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
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#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0
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@ -4,16 +4,16 @@
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/* Autogenerated file, DO NOT EDIT manually!
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||||
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -637,11 +637,12 @@ static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
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#define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070
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#define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
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#define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
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#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007fc
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#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 2
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static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(uint32_t val)
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#define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
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#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
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#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
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static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
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{
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return ((val) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
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return ((((uint32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
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}
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#define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
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@ -745,6 +746,7 @@ static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
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}
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#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
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#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
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#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
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#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000
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#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24
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static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
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@ -767,7 +769,19 @@ static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
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return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK;
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}
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#define REG_A3XX_UNKNOWN_20C3 0x000020c3
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#define REG_A3XX_RB_ALPHA_REF 0x000020c3
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#define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00
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#define A3XX_RB_ALPHA_REF_UINT__SHIFT 8
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static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
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{
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return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK;
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}
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#define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000
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#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
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static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
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{
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return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
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}
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static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
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@ -1002,7 +1016,7 @@ static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endi
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#define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
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#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
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#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
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#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_ENABLE 0x00000008
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#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
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#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
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#define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
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static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
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@ -1038,7 +1052,8 @@ static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
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#define REG_A3XX_RB_STENCIL_CONTROL 0x00002104
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#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
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#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000004
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#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
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#define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
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#define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
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#define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
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static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
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@ -2074,6 +2089,7 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op
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#define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
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#define REG_A3XX_TEX_SAMP_0 0x00000000
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#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
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#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
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#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
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static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val)
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@ -2134,6 +2150,12 @@ static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val)
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{
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return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK;
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}
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#define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
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#define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16
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static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
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{
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return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;
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}
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#define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000
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#define A3XX_TEX_CONST_0_FMT__SHIFT 22
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static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
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@ -4,16 +4,16 @@
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/* Autogenerated file, DO NOT EDIT manually!
|
||||
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||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
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||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
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||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32)
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||||
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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||||
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@ -4,16 +4,16 @@
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|||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
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||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
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||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32)
|
||||
|
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Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
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@ -4,13 +4,13 @@
|
|||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
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||||
|
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|||
|
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@ -4,13 +4,13 @@
|
|||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@
|
|||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@
|
|||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@
|
|||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@
|
|||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
|
||||
git clone git://0x04.net/rules-ng-ng
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
|
|
@ -42,28 +42,28 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
*/
|
||||
|
||||
|
||||
enum mpd4_bpc {
|
||||
enum mdp4_bpc {
|
||||
BPC1 = 0,
|
||||
BPC5 = 1,
|
||||
BPC6 = 2,
|
||||
BPC8 = 3,
|
||||
};
|
||||
|
||||
enum mpd4_bpc_alpha {
|
||||
enum mdp4_bpc_alpha {
|
||||
BPC1A = 0,
|
||||
BPC4A = 1,
|
||||
BPC6A = 2,
|
||||
BPC8A = 3,
|
||||
};
|
||||
|
||||
enum mpd4_alpha_type {
|
||||
enum mdp4_alpha_type {
|
||||
FG_CONST = 0,
|
||||
BG_CONST = 1,
|
||||
FG_PIXEL = 2,
|
||||
BG_PIXEL = 3,
|
||||
};
|
||||
|
||||
enum mpd4_pipe {
|
||||
enum mdp4_pipe {
|
||||
VG1 = 0,
|
||||
VG2 = 1,
|
||||
RGB1 = 2,
|
||||
|
|
@ -73,13 +73,13 @@ enum mpd4_pipe {
|
|||
VG4 = 6,
|
||||
};
|
||||
|
||||
enum mpd4_mixer {
|
||||
enum mdp4_mixer {
|
||||
MIXER0 = 0,
|
||||
MIXER1 = 1,
|
||||
MIXER2 = 2,
|
||||
};
|
||||
|
||||
enum mpd4_mixer_stage_id {
|
||||
enum mdp4_mixer_stage_id {
|
||||
STAGE_UNUSED = 0,
|
||||
STAGE_BASE = 1,
|
||||
STAGE0 = 2,
|
||||
|
|
@ -194,56 +194,56 @@ static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
|
|||
#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
|
||||
}
|
||||
|
|
@ -254,56 +254,56 @@ static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mpd4_mixer_stage_id va
|
|||
#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mpd4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
|
||||
}
|
||||
|
|
@ -369,7 +369,7 @@ static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x
|
|||
static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
|
||||
#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
|
||||
#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
|
||||
static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mpd4_alpha_type val)
|
||||
static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val)
|
||||
{
|
||||
return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
|
||||
}
|
||||
|
|
@ -377,7 +377,7 @@ static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mpd4_alpha_type val)
|
|||
#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
|
||||
#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
|
||||
#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
|
||||
static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mpd4_alpha_type val)
|
||||
static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp4_alpha_type val)
|
||||
{
|
||||
return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
|
||||
}
|
||||
|
|
@ -472,19 +472,19 @@ static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __of
|
|||
static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
|
||||
#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
|
||||
#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
|
||||
static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mpd4_bpc val)
|
||||
static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp4_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
|
||||
}
|
||||
#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
|
||||
#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
|
||||
static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mpd4_bpc val)
|
||||
static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp4_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
|
||||
}
|
||||
#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
|
||||
#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
|
||||
static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mpd4_bpc val)
|
||||
static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp4_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
|
||||
}
|
||||
|
|
@ -601,9 +601,9 @@ static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) {
|
|||
|
||||
static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE(enum mpd4_pipe i0) { return 0x00020000 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mpd4_pipe i0) { return 0x00020000 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
|
||||
#define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
|
||||
#define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
|
||||
static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
|
||||
|
|
@ -617,7 +617,7 @@ static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
|
|||
return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mpd4_pipe i0) { return 0x00020004 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }
|
||||
#define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
|
||||
#define MDP4_PIPE_SRC_XY_Y__SHIFT 16
|
||||
static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
|
||||
|
|
@ -631,7 +631,7 @@ static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
|
|||
return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mpd4_pipe i0) { return 0x00020008 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }
|
||||
#define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
|
||||
#define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16
|
||||
static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
|
||||
|
|
@ -645,7 +645,7 @@ static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
|
|||
return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mpd4_pipe i0) { return 0x0002000c + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }
|
||||
#define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
|
||||
#define MDP4_PIPE_DST_XY_Y__SHIFT 16
|
||||
static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
|
||||
|
|
@ -659,13 +659,13 @@ static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
|
|||
return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mpd4_pipe i0) { return 0x00020010 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mpd4_pipe i0) { return 0x00020014 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mpd4_pipe i0) { return 0x00020018 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mpd4_pipe i0) { return 0x00020040 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
|
||||
#define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
|
||||
#define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
|
||||
static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
|
||||
|
|
@ -679,7 +679,7 @@ static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
|
|||
return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mpd4_pipe i0) { return 0x00020044 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; }
|
||||
#define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
|
||||
#define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
|
||||
static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
|
||||
|
|
@ -693,7 +693,7 @@ static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
|
|||
return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mpd4_pipe i0) { return 0x00020048 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
|
||||
#define MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
|
||||
#define MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT 16
|
||||
static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val)
|
||||
|
|
@ -707,28 +707,28 @@ static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)
|
|||
return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mpd4_pipe i0) { return 0x00020050 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
|
||||
#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
|
||||
#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mpd4_bpc val)
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp4_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
|
||||
}
|
||||
#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
|
||||
#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mpd4_bpc val)
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp4_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
|
||||
}
|
||||
#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
|
||||
#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mpd4_bpc val)
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp4_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
|
||||
}
|
||||
#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
|
||||
#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mpd4_bpc_alpha val)
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp4_bpc_alpha val)
|
||||
{
|
||||
return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
|
||||
}
|
||||
|
|
@ -750,7 +750,7 @@ static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
|
|||
#define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
|
||||
#define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mpd4_pipe i0) { return 0x00020054 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
|
||||
#define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
|
||||
#define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
|
||||
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
|
||||
|
|
@ -776,7 +776,7 @@ static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
|
|||
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mpd4_pipe i0) { return 0x00020058 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
|
||||
#define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
|
||||
#define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
|
||||
#define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
|
||||
|
|
@ -789,36 +789,36 @@ static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mpd4_pipe i0) { return 0x00020
|
|||
#define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
|
||||
#define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mpd4_pipe i0) { return 0x0002005c + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mpd4_pipe i0) { return 0x00020060 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mpd4_pipe i0) { return 0x00021004 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mpd4_pipe i0) { return 0x00021008 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC(enum mpd4_pipe i0) { return 0x00024000 + 0x10000*i0; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }
|
||||
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
|
||||
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
|
||||
static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
|
||||
|
||||
#define REG_MDP4_LCDC 0x000c0000
|
||||
|
||||
|
|
|
|||
|
|
@ -75,8 +75,8 @@ struct mdp4_platform_config {
|
|||
|
||||
struct mdp4_format {
|
||||
struct msm_format base;
|
||||
enum mpd4_bpc bpc_r, bpc_g, bpc_b;
|
||||
enum mpd4_bpc_alpha bpc_a;
|
||||
enum mdp4_bpc bpc_r, bpc_g, bpc_b;
|
||||
enum mdp4_bpc_alpha bpc_a;
|
||||
uint8_t unpack[4];
|
||||
bool alpha_enable, unpack_tight;
|
||||
uint8_t cpp, unpack_count;
|
||||
|
|
@ -93,7 +93,7 @@ static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
|
|||
return msm_readl(mdp4_kms->mmio + reg);
|
||||
}
|
||||
|
||||
static inline uint32_t pipe2flush(enum mpd4_pipe pipe)
|
||||
static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
|
||||
{
|
||||
switch (pipe) {
|
||||
case VG1: return MDP4_OVERLAY_FLUSH_VG1;
|
||||
|
|
@ -158,9 +158,9 @@ int mdp4_plane_mode_set(struct drm_plane *plane,
|
|||
unsigned int crtc_w, unsigned int crtc_h,
|
||||
uint32_t src_x, uint32_t src_y,
|
||||
uint32_t src_w, uint32_t src_h);
|
||||
enum mpd4_pipe mdp4_plane_pipe(struct drm_plane *plane);
|
||||
enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
|
||||
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
|
||||
enum mpd4_pipe pipe_id, bool private_plane);
|
||||
enum mdp4_pipe pipe_id, bool private_plane);
|
||||
|
||||
uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
|
||||
void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc);
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ struct mdp4_plane {
|
|||
struct drm_plane base;
|
||||
const char *name;
|
||||
|
||||
enum mpd4_pipe pipe;
|
||||
enum mdp4_pipe pipe;
|
||||
|
||||
uint32_t nformats;
|
||||
uint32_t formats[32];
|
||||
|
|
@ -101,7 +101,7 @@ void mdp4_plane_set_scanout(struct drm_plane *plane,
|
|||
{
|
||||
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
|
||||
struct mdp4_kms *mdp4_kms = get_kms(plane);
|
||||
enum mpd4_pipe pipe = mdp4_plane->pipe;
|
||||
enum mdp4_pipe pipe = mdp4_plane->pipe;
|
||||
uint32_t iova;
|
||||
|
||||
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe),
|
||||
|
|
@ -129,7 +129,7 @@ int mdp4_plane_mode_set(struct drm_plane *plane,
|
|||
{
|
||||
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
|
||||
struct mdp4_kms *mdp4_kms = get_kms(plane);
|
||||
enum mpd4_pipe pipe = mdp4_plane->pipe;
|
||||
enum mdp4_pipe pipe = mdp4_plane->pipe;
|
||||
const struct mdp4_format *format;
|
||||
uint32_t op_mode = 0;
|
||||
uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
|
||||
|
|
@ -202,7 +202,7 @@ static const char *pipe_names[] = {
|
|||
"VG3", "VG4",
|
||||
};
|
||||
|
||||
enum mpd4_pipe mdp4_plane_pipe(struct drm_plane *plane)
|
||||
enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane)
|
||||
{
|
||||
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
|
||||
return mdp4_plane->pipe;
|
||||
|
|
@ -210,7 +210,7 @@ enum mpd4_pipe mdp4_plane_pipe(struct drm_plane *plane)
|
|||
|
||||
/* initialize plane */
|
||||
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
|
||||
enum mpd4_pipe pipe_id, bool private_plane)
|
||||
enum mdp4_pipe pipe_id, bool private_plane)
|
||||
{
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct drm_plane *plane = NULL;
|
||||
|
|
|
|||
Loading…
Reference in New Issue